intel: Add has_bit6_swizzle to devinfo

There's no good reason to have this rather complex check in three
drivers.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13636>

7 files changed, 23 insertions, 50 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 24c60af711c..a4d49aaeca0 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1011,8 +1011,6 @@ brw_create_context(gl_api api,
    brw->has_hiz = devinfo->has_hiz_and_separate_stencil;
    brw->has_separate_stencil = devinfo->has_hiz_and_separate_stencil;
 
-   brw->has_swizzling = screen->hw_has_swizzling;
-
    /* We don't push UBOs on IVB and earlier because the restrictions on
     * 3DSTATE_CONSTANT_* make it really annoying to use push constants
     * without dynamic state base address.
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 579dcecad05..2061fb24615 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -825,7 +825,6 @@ struct brw_context
 
    bool has_hiz;
    bool has_separate_stencil;
-   bool has_swizzling;
 
    bool can_push_ubos;
 
diff --git a/src/mesa/drivers/dri/i965/brw_mipmap_tree.c b/src/mesa/drivers/dri/i965/brw_mipmap_tree.c
index 2c85f9b3900..b44fd466f39 100644
--- a/src/mesa/drivers/dri/i965/brw_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/brw_mipmap_tree.c
@@ -2484,6 +2484,8 @@ brw_miptree_unmap_tiled_memcpy(struct brw_context *brw,
                                unsigned int level,
                                unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+
    if (map->mode & GL_MAP_WRITE_BIT) {
       unsigned int x1, x2, y1, y2;
       tile_extents(mt, map, level, slice, &x1, &x2, &y1, &y2);
@@ -2493,7 +2495,7 @@ brw_miptree_unmap_tiled_memcpy(struct brw_context *brw,
 
       isl_memcpy_linear_to_tiled(
          x1, x2, y1, y2, dst, map->ptr, mt->surf.row_pitch_B, map->stride,
-         brw->has_swizzling, mt->surf.tiling, ISL_MEMCPY);
+         devinfo->has_bit6_swizzle, mt->surf.tiling, ISL_MEMCPY);
 
       brw_miptree_unmap_raw(mt);
    }
@@ -2567,6 +2569,8 @@ brw_miptree_map_tiled_memcpy(struct brw_context *brw,
                              struct brw_miptree_map *map,
                              unsigned int level, unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+
    brw_miptree_access_raw(brw, mt, level, slice,
                           map->mode & GL_MAP_WRITE_BIT);
 
@@ -2595,7 +2599,7 @@ brw_miptree_map_tiled_memcpy(struct brw_context *brw,
 
       isl_memcpy_tiled_to_linear(
          x1, x2, y1, y2, map->ptr, src, map->stride,
-         mt->surf.row_pitch_B, brw->has_swizzling, mt->surf.tiling,
+         mt->surf.row_pitch_B, devinfo->has_bit6_swizzle, mt->surf.tiling,
          copy_type);
 
       brw_miptree_unmap_raw(mt);
@@ -2748,6 +2752,8 @@ brw_miptree_unmap_s8(struct brw_context *brw,
                      unsigned int level,
                      unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+
    if (map->mode & GL_MAP_WRITE_BIT) {
       unsigned int image_x, image_y;
       uint8_t *untiled_s8_map = map->ptr;
@@ -2760,7 +2766,7 @@ brw_miptree_unmap_s8(struct brw_context *brw,
             ptrdiff_t offset = brw_offset_S8(mt->surf.row_pitch_B,
                                              image_x + x + map->x,
                                              image_y + y + map->y,
-                                             brw->has_swizzling);
+                                             devinfo->has_bit6_swizzle);
             tiled_s8_map[offset] = untiled_s8_map[y * map->w + x];
          }
       }
@@ -2777,6 +2783,8 @@ brw_miptree_map_s8(struct brw_context *brw,
                    struct brw_miptree_map *map,
                    unsigned int level, unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+
    map->stride = map->w;
    map->buffer = map->ptr = malloc(map->stride * map->h);
    if (!map->buffer)
@@ -2802,7 +2810,7 @@ brw_miptree_map_s8(struct brw_context *brw,
             ptrdiff_t offset = brw_offset_S8(mt->surf.row_pitch_B,
                                              x + image_x + map->x,
                                              y + image_y + map->y,
-                                             brw->has_swizzling);
+                                             devinfo->has_bit6_swizzle);
             untiled_s8_map[y * map->w + x] = tiled_s8_map[offset];
          }
       }
@@ -2839,6 +2847,7 @@ brw_miptree_unmap_depthstencil(struct brw_context *brw,
                                unsigned int level,
                                unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
    struct brw_mipmap_tree *z_mt = mt;
    struct brw_mipmap_tree *s_mt = mt->stencil_mt;
    bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32;
@@ -2860,7 +2869,7 @@ brw_miptree_unmap_depthstencil(struct brw_context *brw,
             ptrdiff_t s_offset = brw_offset_S8(s_mt->surf.row_pitch_B,
                                                x + s_image_x + map->x,
                                                y + s_image_y + map->y,
-                                               brw->has_swizzling);
+                                               devinfo->has_bit6_swizzle);
             ptrdiff_t z_offset = ((y + z_image_y + map->y) *
                                   (z_mt->surf.row_pitch_B / 4) +
                                   (x + z_image_x + map->x));
@@ -2897,6 +2906,7 @@ brw_miptree_map_depthstencil(struct brw_context *brw,
                              struct brw_miptree_map *map,
                              unsigned int level, unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
    struct brw_mipmap_tree *z_mt = mt;
    struct brw_mipmap_tree *s_mt = mt->stencil_mt;
    bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32;
@@ -2935,7 +2945,7 @@ brw_miptree_map_depthstencil(struct brw_context *brw,
             ptrdiff_t s_offset = brw_offset_S8(s_mt->surf.row_pitch_B,
                                                  map_x + s_image_x,
                                                  map_y + s_image_y,
-                                                 brw->has_swizzling);
+                                                 devinfo->has_bit6_swizzle);
             ptrdiff_t z_offset = ((map_y + z_image_y) *
                                   (z_mt->surf.row_pitch_B / 4) +
                                   (map_x + z_image_x));
diff --git a/src/mesa/drivers/dri/i965/brw_pixel_read.c b/src/mesa/drivers/dri/i965/brw_pixel_read.c
index 1c874eca2f5..ad0ee97db87 100644
--- a/src/mesa/drivers/dri/i965/brw_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/brw_pixel_read.c
@@ -143,7 +143,7 @@ brw_readpixels_tiled_memcpy(struct gl_context *ctx,
     * parts of the memory aren't swizzled at all. Userspace just can't handle
     * that.
     */
-   if (devinfo->ver < 5 && brw->has_swizzling)
+   if (devinfo->ver < 5 && devinfo->has_bit6_swizzle)
       return false;
 
    /* Since we are going to read raw data to the miptree, we need to resolve
@@ -204,7 +204,7 @@ brw_readpixels_tiled_memcpy(struct gl_context *ctx,
       pixels,
       map + irb->mt->offset,
       dst_pitch, irb->mt->surf.row_pitch_B,
-      brw->has_swizzling,
+      devinfo->has_bit6_swizzle,
       irb->mt->surf.tiling,
       copy_type
    );
diff --git a/src/mesa/drivers/dri/i965/brw_screen.c b/src/mesa/drivers/dri/i965/brw_screen.c
index fbf81e6b60c..96c9ea617df 100644
--- a/src/mesa/drivers/dri/i965/brw_screen.c
+++ b/src/mesa/drivers/dri/i965/brw_screen.c
@@ -1915,37 +1915,6 @@ brw_init_bufmgr(struct brw_screen *screen)
    return true;
 }
 
-static bool
-brw_detect_swizzling(struct brw_screen *screen)
-{
-   /* Broadwell PRM says:
-    *
-    *   "Before Gfx8, there was a historical configuration control field to
-    *    swizzle address bit[6] for in X/Y tiling modes. This was set in three
-    *    different places: TILECTL[1:0], ARB_MODE[5:4], and
-    *    DISP_ARB_CTL[14:13].
-    *
-    *    For Gfx8 and subsequent generations, the swizzle fields are all
-    *    reserved, and the CPU's memory controller performs all address
-    *    swizzling modifications."
-    */
-   if (screen->devinfo.ver >= 8)
-      return false;
-
-   uint32_t tiling = I915_TILING_X;
-   uint32_t swizzle_mode = 0;
-   struct brw_bo *buffer =
-      brw_bo_alloc_tiled(screen->bufmgr, "swizzle test", 32768,
-                         BRW_MEMZONE_OTHER, tiling, 512, 0);
-   if (buffer == NULL)
-      return false;
-
-   brw_bo_get_tiling(buffer, &tiling, &swizzle_mode);
-   brw_bo_unreference(buffer);
-
-   return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
-}
-
 static int
 brw_detect_timestamp(struct brw_screen *screen)
 {
@@ -2603,11 +2572,9 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
 
    screen->aperture_threshold = devinfo->aperture_bytes * 3 / 4;
 
-   screen->hw_has_swizzling = brw_detect_swizzling(screen);
    screen->hw_has_timestamp = brw_detect_timestamp(screen);
 
-   isl_device_init(&screen->isl_dev, &screen->devinfo,
-                   screen->hw_has_swizzling);
+   isl_device_init(&screen->isl_dev, &screen->devinfo);
 
    /* Gfx7-7.5 kernel requirements / command parser saga:
     *
diff --git a/src/mesa/drivers/dri/i965/brw_screen.h b/src/mesa/drivers/dri/i965/brw_screen.h
index d2cefc2be6a..b68c2acecba 100644
--- a/src/mesa/drivers/dri/i965/brw_screen.h
+++ b/src/mesa/drivers/dri/i965/brw_screen.h
@@ -59,7 +59,6 @@ struct brw_screen
    /** DRM fd associated with this screen. Not owned by this object. Do not close. */
    int fd;
 
-   bool hw_has_swizzling;
    bool has_exec_fence; /**< I915_PARAM_HAS_EXEC_FENCE */
 
    int hw_has_timestamp;
diff --git a/src/mesa/drivers/dri/i965/brw_tex_image.c b/src/mesa/drivers/dri/i965/brw_tex_image.c
index 02e9d6438d3..7abe848e64a 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_image.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_image.c
@@ -246,7 +246,7 @@ brw_texsubimage_tiled_memcpy(struct gl_context * ctx,
     * parts of the memory aren't swizzled at all. Userspace just can't handle
     * that.
     */
-   if (devinfo->ver < 5 && brw->has_swizzling)
+   if (devinfo->ver < 5 && devinfo->has_bit6_swizzle)
       return false;
 
    int level = texImage->Level + texImage->TexObject->Attrib.MinLevel;
@@ -297,7 +297,7 @@ brw_texsubimage_tiled_memcpy(struct gl_context * ctx,
       map,
       pixels,
       image->mt->surf.row_pitch_B, src_pitch,
-      brw->has_swizzling,
+      devinfo->has_bit6_swizzle,
       image->mt->surf.tiling,
       copy_type
    );
@@ -798,7 +798,7 @@ brw_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
     * parts of the memory aren't swizzled at all. Userspace just can't handle
     * that.
     */
-   if (devinfo->ver < 5 && brw->has_swizzling)
+   if (devinfo->ver < 5 && devinfo->has_bit6_swizzle)
       return false;
 
    int level = texImage->Level + texImage->TexObject->Attrib.MinLevel;
@@ -846,7 +846,7 @@ brw_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
       pixels,
       map,
       dst_pitch, image->mt->surf.row_pitch_B,
-      brw->has_swizzling,
+      devinfo->has_bit6_swizzle,
       image->mt->surf.tiling,
       copy_type
    );