diff options
author | Nanley Chery <nanley.g.chery@intel.com> | 2018-04-08 14:00:30 -0700 |
---|---|---|
committer | Nanley Chery <nanley.g.chery@intel.com> | 2018-05-17 07:06:41 -0700 |
commit | 82849fb6d54629a0c7c5a118ed8780a3ae573b25 (patch) | |
tree | dde23b35e19bb73458075285f45c989634a48922 /src/mesa/drivers/dri/i965/intel_mipmap_tree.c | |
parent | 5b315f3ad1451b7c24e29f534cd1c7ed0de0fa77 (diff) |
i965: Update the indirect buffer in set_clear_color
For depth buffers, we avoid fast-clearing if the aux_state is already
CLEAR. We do the same for color buffers only if the clear color
doesn't change. We require that the clear colors match because, in
that case, we don't update the indirect clear color outside of BLORP.
Update the indirect clear color for color buffers as well. We'll
enable the same depth buffer optimization for color buffers in a
later patch.
Note that we're now actually updating the indirect clear color twice
in the case where we use BLORP to perform the fast-clear. This is
only temporary. In later patches, we'll prevent BLORP from performing
the update.
v2: Add more context to the commit message (Topi).
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_mipmap_tree.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 88db0fc80b7..0c7c89a9ac4 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -3728,6 +3728,19 @@ intel_miptree_set_clear_color(struct brw_context *brw, { if (memcmp(&mt->fast_clear_color, &clear_color, sizeof(clear_color)) != 0) { mt->fast_clear_color = clear_color; + if (mt->aux_buf->clear_color_bo) { + /* We can't update the clear color while the hardware is still using + * the previous one for a resolve or sampling from it. Make sure that + * there are no pending commands at this point. + */ + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL); + for (int i = 0; i < 4; i++) { + brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo, + mt->aux_buf->clear_color_offset + i * 4, + mt->fast_clear_color.u32[i]); + } + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE); + } brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE; return true; } |