diff options
| author | Anuj Phogat <anuj.phogat@gmail.com> | 2017-11-13 11:23:51 -0800 |
|---|---|---|
| committer | Anuj Phogat <anuj.phogat@gmail.com> | 2017-11-14 13:23:18 -0800 |
| commit | fc59546e9aaf4e13e90c06bb5ad06d77fa67d127 (patch) | |
| tree | 47d64653592f2c067acf737391733d2c89429aa9 /src/mesa/drivers/dri/i965/brw_state_upload.c | |
| parent | 1dc45d75bb3ff3085f7356b8ec658111529ff76d (diff) | |
i965: Make use of brw_load_register_imm32() helper function
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_state_upload.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 22 |
1 files changed, 8 insertions, 14 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index f54e15e92bf..da464ef7b14 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -86,22 +86,16 @@ brw_upload_initial_gpu_state(struct brw_context *brw) /* Recommended optimizations for Victim Cache eviction and floating * point blending. */ - BEGIN_BATCH(3); - OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); - OUT_BATCH(GEN7_CACHE_MODE_1); - OUT_BATCH(REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) | - REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) | - GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE | - GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC); - ADVANCE_BATCH(); + brw_load_register_imm32(brw, GEN7_CACHE_MODE_1, + REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) | + REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) | + GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE | + GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC); if (gen_device_info_is_9lp(devinfo)) { - BEGIN_BATCH(3); - OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); - OUT_BATCH(GEN7_GT_MODE); - OUT_BATCH(GEN9_SUBSLICE_HASHING_MASK_BITS | - GEN9_SUBSLICE_HASHING_16x16); - ADVANCE_BATCH(); + brw_load_register_imm32(brw, GEN7_GT_MODE, + GEN9_SUBSLICE_HASHING_MASK_BITS | + GEN9_SUBSLICE_HASHING_16x16); } } |