diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2021-03-10 09:26:13 -0800 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2021-03-19 09:07:37 +0000 |
| commit | b9a7f9314bc1acb64b778f8d9405e0a0e74a6ff2 (patch) | |
| tree | 8a22226ab3837303004aa6217b696c1826db422d /src/mesa/drivers/dri/i965/brw_state_upload.c | |
| parent | 5057f14cbaa4810995c959a96f1e7047a781ff38 (diff) | |
i965/gen11: Fix must-be-ones bit positions in 3D_MODE
Fixes: f0d29238df3 ("i965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9505>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_state_upload.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 10f8885887f..1816c389824 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -144,7 +144,7 @@ brw_upload_gen11_slice_hashing_state(struct brw_context *brw) */ BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_3D_MODE << 16 | (2 - 2)); - OUT_BATCH(0xffff | SLICE_HASHING_TABLE_ENABLE); + OUT_BATCH(0xffff0000 | SLICE_HASHING_TABLE_ENABLE); ADVANCE_BATCH(); } |