diff options
| author | Iago Toral Quiroga <itoral@igalia.com> | 2014-07-01 13:08:25 +0200 |
|---|---|---|
| committer | Iago Toral Quiroga <itoral@igalia.com> | 2014-09-19 15:01:15 +0200 |
| commit | c09ddf82ffa13173b55a1b51075be2671378c4ea (patch) | |
| tree | ebaf69626cc5aa55e6e449cbd3bce2691379365a /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | 621685ad4c747cc67e1b6c7ba95fa59774196a54 (diff) | |
i965/gen6/gs: Compute URB entry size for user-provided geometry shaders.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 0b5735cc02e..72a21e85d16 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1595,10 +1595,14 @@ enum brw_message_target { # define GEN7_URB_ENTRY_SIZE_SHIFT 16 # define GEN7_URB_STARTING_ADDRESS_SHIFT 25 -/* "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size +/* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size * is 2^9, or 512. It's counted in multiples of 64 bytes. */ -#define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64) +#define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64) +/* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit + * (128 bytes) URB rows and the maximum allowed value is 5 rows. + */ +#define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128) #define _3DSTATE_PUSH_CONSTANT_ALLOC_VS 0x7912 /* GEN7+ */ #define _3DSTATE_PUSH_CONSTANT_ALLOC_GS 0x7915 /* GEN7+ */ |