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path: root/src/mesa/drivers/dri/i965/brw_defines.h
AgeCommit message (Expand)AuthorFilesLines
2015-05-18i965: Add Gen9 surface state decodingBen Widawsky1-0/+2
2015-05-18i965: Add gen8 surface state debug infoBen Widawsky1-1/+3
2015-05-18i965: Add gen7+ sampler state to batch debugBen Widawsky1-0/+1
2015-05-12i965: Use predicate enable bit for conditional rendering w/o stallingNeil Roberts1-0/+1
2015-05-06i965/gen6: setup limits for ARB_viewport_arrayChris Forbes1-1/+1
2015-05-04i965: Introduce the FIND_LIVE_CHANNEL pseudo-opcode.Francisco Jerez1-0/+8
2015-05-04i965: Introduce the BROADCAST pseudo-opcode.Francisco Jerez1-0/+6
2015-05-04i965: Add memory fence opcode.Francisco Jerez1-0/+2
2015-05-04i965: Add typed surface access opcodes.Francisco Jerez1-0/+4
2015-05-04i965: Add untyped surface write opcode.Francisco Jerez1-0/+1
2015-05-02i965/cs: Emit MEDIA_STATE_FLUSH after WALKERJordan Justen1-0/+1
2015-05-02i965/cs: Implement brw_emit_gpgpu_walkerJordan Justen1-0/+13
2015-05-02i965/cs: Upload brw_cs_stateJordan Justen1-0/+20
2015-05-02i965/cs: Add CS_OPCODE_CS_TERMINATEJordan Justen1-0/+5
2015-04-30i965/ps: Use SET_FIELD() for sampler countTopi Pohjolainen1-0/+1
2015-04-21i965/fs: Combine pixel center calculation into one inst.Matt Turner1-0/+2
2015-04-21i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.Matt Turner1-2/+0
2015-04-16i965/skl: Add the header for constant loads outside of the generatorNeil Roberts1-0/+1
2015-03-02i965: Add missing defines for render cache messages.Francisco Jerez1-1/+7
2015-02-19i965/vec4: Add and use byte-MOV instruction for unpack 4x8.Matt Turner1-0/+1
2015-02-09i965: Fix integer border color on Haswell.Kenneth Graunke1-0/+1
2015-01-08i965/skl: Always use a header for SIMD4x2 sampler messagesKristian Høgsberg1-0/+5
2014-12-10i965: Add new SIMD8 VS prog data flagKristian Høgsberg1-0/+2
2014-12-10i965: Add SIMD8 URB write low-level IR instructionKristian Høgsberg1-0/+3
2014-12-05i965/vec4: Allow CSE on uniform-vec4 expansion MOVs.Matt Turner1-0/+1
2014-12-04i965: Move PSCDEPTH calculations from draw time to compile time.Kenneth Graunke1-8/+9
2014-11-27i965/fs: Pass key->render_to_fbo via src1 of FS_OPCODE_DDY_*.Kenneth Graunke1-0/+4
2014-11-27i965/fs: Handle derivative quality decisions in the front-end.Kenneth Graunke1-8/+4
2014-11-25i965/vec4: Add VEC4_OPCODE_PACK_4_BYTES.Matt Turner1-0/+2
2014-11-20i965/disasm: Properly decode branch_ctrl (gen8+)Ben Widawsky1-0/+1
2014-11-08i965: Set Line Width correctly on Cherryview and Skylake.Kenneth Graunke1-0/+1
2014-11-06i965: Convert stride/width/execution size macros into enums.Matt Turner1-28/+33
2014-11-03i965/skl: Use new MOCS for SKLKristian Høgsberg1-0/+7
2014-11-03i965/skl: Update Viewport Z Clip Test Enable bits for Skylake.Kenneth Graunke1-0/+2
2014-11-03i965/skl: Update stencil reference handling for Skylake.Kenneth Graunke1-0/+5
2014-11-03i965/skl: Update 3DSTATE_SBE for Skylake.Damien Lespiau1-0/+6
2014-10-09i965: Add a BRW_MOCS_PTE #define.Kenneth Graunke1-3/+7
2014-10-01i965: Fix spelling of GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHMChris Forbes1-1/+1
2014-09-29i965: Delete intel_chipset.h.Kenneth Graunke1-2/+0
2014-09-25i965: Add BRW_OPCODE_NENOP for G45.Matt Turner1-0/+1
2014-09-19i965/gen6/gs: Add an additional parameter to the FF_SYNC opcode.Samuel Iglesias Gonsalvez1-0/+4
2014-09-19i965/gen6/gs: implement GS_OPCODE_FF_SYNC_SET_PRIMITIVES opcodeSamuel Iglesias Gonsalvez1-0/+15
2014-09-19i965/gen6/gs: implement GS_OPCODE_SVB_SET_DST_INDEX opcodeSamuel Iglesias Gonsalvez1-0/+9
2014-09-19i965/gen6/gs: implement GS_OPCODE_SVB_WRITE opcodeSamuel Iglesias Gonsalvez1-0/+12
2014-09-19i965/gen6/gs: Implement GS_OPCODE_SET_PRIMITIVE_ID.Iago Toral Quiroga1-0/+8
2014-09-19i965/gen6/gs: Implement GS_OPCODE_SET_DWORD_2.Iago Toral Quiroga1-4/+2
2014-09-19i965/gen6/gs: Compute URB entry size for user-provided geometry shaders.Iago Toral Quiroga1-2/+6
2014-09-19i965/gen6/gs: Implement GS_OPCODE_URB_WRITE_ALLOCATE.Iago Toral Quiroga1-0/+8
2014-09-19i965/gen6/gs: Implement GS_OPCODE_FF_SYNC.Iago Toral Quiroga1-0/+15
2014-08-28i965: Mark BRW_CONDITIONAL_R as Gen <= 5.Matt Turner1-1/+1