diff options
| author | Sagar Ghuge <sagar.ghuge@intel.com> | 2021-02-24 23:24:41 -0800 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2021-10-08 18:56:14 +0000 |
| commit | 35fd101ad2146659c52b7376e3104222b570538a (patch) | |
| tree | d08755ba11dd2e86623db59c5cc343dc96534cbb /src/intel | |
| parent | dd54e9125ad6d8160450e4364cc900a265d85198 (diff) | |
isl: Use software programmable render compression format encoding
Instead of relying on hardcoded (legacy) encoding format, use software
programmable encoding for render compression format.
v2: (Nanley)
- Fix param mismatch
- Set RenderCompressionFormat unconditionally
- Fix commit message
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12686>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/isl/isl_emit_depth_stencil.c | 6 | ||||
| -rw-r--r-- | src/intel/isl/isl_surface_state.c | 4 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index 010894d53be..370f98b811d 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -125,6 +125,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #if GFX_VERx10 >= 125 db.TiledMode = isl_encode_tiling[info->depth_surf->tiling]; db.MipTailStartLOD = 15; + db.CompressionMode = isl_aux_usage_has_ccs(info->hiz_usage); + db.RenderCompressionFormat = + isl_get_render_compression_format(info->depth_surf->format); #elif GFX_VER <= 6 db.TiledSurface = info->depth_surf->tiling != ISL_TILING_LINEAR; db.TileWalk = info->depth_surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR : @@ -169,6 +172,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #if GFX_VERx10 >= 125 sb.TiledMode = isl_encode_tiling[info->stencil_surf->tiling]; sb.MipTailStartLOD = 15; + sb.CompressionMode = isl_aux_usage_has_ccs(info->stencil_aux_usage); + sb.RenderCompressionFormat = + isl_get_render_compression_format(info->stencil_surf->format); #endif #if GFX_VER >= 12 sb.StencilWriteEnable = true; diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 40415bd3b92..dbbf2de8942 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -705,6 +705,10 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, } } +#if GFX_VERx10 >= 125 + s.RenderCompressionFormat = + isl_get_render_compression_format(info->surf->format); +#endif #if GFX_VER >= 12 s.MemoryCompressionEnable = info->aux_usage == ISL_AUX_USAGE_MC; #endif |