diff options
author | Mark Janes <markjanes@swizzler.org> | 2020-06-30 15:00:13 -0700 |
---|---|---|
committer | Mark Janes <markjanes@swizzler.org> | 2021-02-01 17:24:57 -0800 |
commit | 0b6209b9081c50657ba81c79d0491afa2904f662 (patch) | |
tree | bdb71c0f08653079b2ec2e098db0769023090fa7 /src/intel | |
parent | 4a2d9e44ff26138fcb0b92d03b6c05bcbbea5b80 (diff) |
blorp: add hook for INTEL_MEASURE
Saves the snapshot type within the blorp parameters.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7354>
Diffstat (limited to 'src/intel')
-rw-r--r-- | src/intel/blorp/blorp.c | 14 | ||||
-rw-r--r-- | src/intel/blorp/blorp_blit.c | 2 | ||||
-rw-r--r-- | src/intel/blorp/blorp_clear.c | 29 | ||||
-rw-r--r-- | src/intel/blorp/blorp_genX_exec.h | 8 | ||||
-rw-r--r-- | src/intel/blorp/blorp_priv.h | 2 | ||||
-rw-r--r-- | src/intel/vulkan/genX_blorp_exec.c | 3 |
6 files changed, 58 insertions, 0 deletions
diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c index 0c0b70f94f1..fe2027fae19 100644 --- a/src/intel/blorp/blorp.c +++ b/src/intel/blorp/blorp.c @@ -328,6 +328,20 @@ blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf, params.hiz_op = op; params.full_surface_hiz_op = true; + switch (op) { + case ISL_AUX_OP_FULL_RESOLVE: + params.snapshot_type = INTEL_SNAPSHOT_HIZ_RESOLVE; + break; + case ISL_AUX_OP_AMBIGUATE: + params.snapshot_type = INTEL_SNAPSHOT_HIZ_AMBIGUATE; + break; + case ISL_AUX_OP_FAST_CLEAR: + params.snapshot_type = INTEL_SNAPSHOT_HIZ_CLEAR; + break; + case ISL_AUX_OP_PARTIAL_RESOLVE: + case ISL_AUX_OP_NONE: + unreachable("Invalid HiZ op"); + } for (uint32_t a = 0; a < num_layers; a++) { const uint32_t layer = start_layer + a; diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index bf829eb5de3..6d0a6df84ae 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -2330,6 +2330,7 @@ blorp_blit(struct blorp_batch *batch, { struct blorp_params params; blorp_params_init(¶ms); + params.snapshot_type = INTEL_SNAPSHOT_BLIT; /* We cannot handle combined depth and stencil. */ if (src_surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) @@ -2638,6 +2639,7 @@ blorp_copy(struct blorp_batch *batch, return; blorp_params_init(¶ms); + params.snapshot_type = INTEL_SNAPSHOT_COPY; brw_blorp_surface_info_init(batch->blorp, ¶ms.src, src_surf, src_level, src_layer, ISL_FORMAT_UNSUPPORTED, false); brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, dst_surf, dst_level, diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index 69d1a3ffc1e..beaeda1e51d 100644 --- a/src/intel/blorp/blorp_clear.c +++ b/src/intel/blorp/blorp_clear.c @@ -363,6 +363,12 @@ blorp_fast_clear(struct blorp_batch *batch, start_layer, format, true); params.num_samples = params.dst.surf.samples; + assert(params.num_samples != 0); + if (params.num_samples == 1) + params.snapshot_type = INTEL_SNAPSHOT_CCS_COLOR_CLEAR; + else + params.snapshot_type = INTEL_SNAPSHOT_MCS_COLOR_CLEAR; + /* If a swizzle was provided, we need to swizzle the clear color so that * the hardware color format conversion will work properly. */ @@ -383,6 +389,7 @@ blorp_clear(struct blorp_batch *batch, { struct blorp_params params; blorp_params_init(¶ms); + params.snapshot_type = INTEL_SNAPSHOT_SLOW_COLOR_CLEAR; /* Manually apply the clear destination swizzle. This way swizzled clears * will work for swizzles which we can't normally use for rendering and it @@ -597,6 +604,7 @@ blorp_clear_stencil_as_rgba(struct blorp_batch *batch, struct blorp_params params; blorp_params_init(¶ms); + params.snapshot_type = INTEL_SNAPSHOT_SLOW_DEPTH_CLEAR; if (!blorp_params_get_clear_kernel(batch, ¶ms, true, false)) return false; @@ -675,6 +683,7 @@ blorp_clear_depth_stencil(struct blorp_batch *batch, struct blorp_params params; blorp_params_init(¶ms); + params.snapshot_type = INTEL_SNAPSHOT_SLOW_DEPTH_CLEAR; params.x0 = x0; params.y0 = y0; @@ -884,6 +893,7 @@ blorp_hiz_clear_depth_stencil(struct blorp_batch *batch, { struct blorp_params params; blorp_params_init(¶ms); + params.snapshot_type = INTEL_SNAPSHOT_HIZ_CLEAR; /* This requires WM_HZ_OP which only exists on gen8+ */ assert(ISL_DEV_GEN(batch->blorp->isl_dev) >= 8); @@ -949,6 +959,7 @@ blorp_gen8_hiz_clear_attachments(struct blorp_batch *batch, struct blorp_params params; blorp_params_init(¶ms); + params.snapshot_type = INTEL_SNAPSHOT_HIZ_CLEAR; params.num_layers = 1; params.hiz_op = ISL_AUX_OP_FAST_CLEAR; params.x0 = x0; @@ -1002,6 +1013,7 @@ blorp_clear_attachments(struct blorp_batch *batch, if (clear_color) { params.dst.enabled = true; + params.snapshot_type = INTEL_SNAPSHOT_SLOW_COLOR_CLEAR; memcpy(¶ms.wm_inputs.clear_color, color_value.f32, sizeof(float) * 4); @@ -1015,6 +1027,7 @@ blorp_clear_attachments(struct blorp_batch *batch, if (clear_depth) { params.depth.enabled = true; + params.snapshot_type = INTEL_SNAPSHOT_SLOW_DEPTH_CLEAR; params.z = depth_value; params.depth_format = isl_format_get_depth_format(depth_format, false); @@ -1022,6 +1035,7 @@ blorp_clear_attachments(struct blorp_batch *batch, if (stencil_mask) { params.stencil.enabled = true; + params.snapshot_type = INTEL_SNAPSHOT_SLOW_DEPTH_CLEAR; params.stencil_mask = stencil_mask; params.stencil_ref = stencil_value; @@ -1045,6 +1059,19 @@ blorp_ccs_resolve(struct blorp_batch *batch, struct blorp_params params; blorp_params_init(¶ms); + switch(resolve_op) { + case ISL_AUX_OP_AMBIGUATE: + params.snapshot_type = INTEL_SNAPSHOT_CCS_AMBIGUATE; + break; + case ISL_AUX_OP_FULL_RESOLVE: + params.snapshot_type = INTEL_SNAPSHOT_CCS_RESOLVE; + break; + case ISL_AUX_OP_PARTIAL_RESOLVE: + params.snapshot_type = INTEL_SNAPSHOT_CCS_PARTIAL_RESOLVE; + break; + default: + assert(false); + } brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, level, start_layer, format, true); @@ -1207,6 +1234,7 @@ blorp_mcs_partial_resolve(struct blorp_batch *batch, { struct blorp_params params; blorp_params_init(¶ms); + params.snapshot_type = INTEL_SNAPSHOT_MCS_PARTIAL_RESOLVE; assert(batch->blorp->isl_dev->info->gen >= 7); @@ -1252,6 +1280,7 @@ blorp_ccs_ambiguate(struct blorp_batch *batch, struct blorp_params params; blorp_params_init(¶ms); + params.snapshot_type = INTEL_SNAPSHOT_CCS_AMBIGUATE; assert(ISL_DEV_GEN(batch->blorp->isl_dev) >= 7); diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index f0872eb0be8..0f52b48d27b 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -52,6 +52,10 @@ static uint64_t blorp_emit_reloc(struct blorp_batch *batch, void *location, struct blorp_address address, uint32_t delta); +static void +blorp_measure_start(struct blorp_batch *batch, + const struct blorp_params *params); + static void * blorp_alloc_dynamic_state(struct blorp_batch *batch, uint32_t size, @@ -1766,6 +1770,8 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch, blorp_emit_depth_stencil_config(batch, params); } + blorp_measure_start(batch, params); + blorp_emit(batch, GENX(3DSTATE_WM_HZ_OP), hzp) { switch (params->hiz_op) { case ISL_AUX_OP_FAST_CLEAR: @@ -1970,6 +1976,8 @@ blorp_exec(struct blorp_batch *batch, const struct blorp_params *params) if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL)) blorp_emit_depth_stencil_config(batch, params); + blorp_measure_start(batch, params); + blorp_emit(batch, GENX(3DPRIMITIVE), prim) { prim.VertexAccessType = SEQUENTIAL; prim.PrimitiveTopologyType = _3DPRIM_RECTLIST; diff --git a/src/intel/blorp/blorp_priv.h b/src/intel/blorp/blorp_priv.h index 5bb498402bb..3d1d984a2fd 100644 --- a/src/intel/blorp/blorp_priv.h +++ b/src/intel/blorp/blorp_priv.h @@ -26,6 +26,7 @@ #include <stdint.h> +#include "common/intel_measure.h" #include "compiler/nir/nir.h" #include "compiler/brw_compiler.h" @@ -218,6 +219,7 @@ struct blorp_params bool use_pre_baked_binding_table; uint32_t pre_baked_binding_table_offset; + enum intel_measure_snapshot_type snapshot_type; }; void blorp_params_init(struct blorp_params *params); diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index 10b98543c85..66dc0485eff 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -33,6 +33,9 @@ #include "common/gen_l3_config.h" #include "blorp/blorp_genX_exec.h" +static void blorp_measure_start(struct blorp_batch *_batch, + const struct blorp_params *params) { } + static void * blorp_emit_dwords(struct blorp_batch *batch, unsigned n) { |