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authorSagar Ghuge <sagar.ghuge@intel.com>2023-05-16 11:25:33 -0700
committerSagar Ghuge <sagar.ghuge@intel.com>2023-05-17 10:05:34 -0700
commit688ee02864d52101a31886f9d762e6d8d13bc3c2 (patch)
treef0772fb8b6b2322a5691c8f4cf2ed7c482deb1fe /src/intel/vulkan/anv_blorp.c
parent241741a77a8ffb8b5b8e65a717922b22bb423325 (diff)
anv: Set CS stall bit during HIZ_CCS_WT surface fast clear
It make sense to enable CS stall so that it guarantees that the fast clear will start after tile cache flush has completed. cc: mesa-stable closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9030 Fixes: e488773b ("anv: Fast clear depth/stencil surface in vkCmdClearAttachments" Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23063>
Diffstat (limited to 'src/intel/vulkan/anv_blorp.c')
-rw-r--r--src/intel/vulkan/anv_blorp.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index c59672925f4..caeb8a4212b 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1520,9 +1520,13 @@ anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
*
* There may have been a write to this depth buffer. Flush it from the
* tile cache just in case.
+ *
+ * Set CS stall bit to guarantee that the fast clear starts the execution
+ * after the tile cache flush completed.
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
+ ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT,
"before clear hiz_ccs_wt");
}