diff options
| author | Sagar Ghuge <sagar.ghuge@intel.com> | 2023-07-06 09:29:31 -0700 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2023-07-10 18:03:39 +0000 |
| commit | 66a6f48747266f9adb4c36ea3e846dae3e0647b7 (patch) | |
| tree | 68d39f0b311756c905eeaefb4398dfd17d84a34c /src/intel/vulkan/anv_blorp.c | |
| parent | bcae3128193047e82c3e2b110f424cf2a77eef56 (diff) | |
anv: Drop depth cache flush requirement after depth clear/resolve
From Bspec 46959, a programming note applicable to Gfx12+:
"Since HZ_OP has to be sent twice (first time set the clear/resolve
state and 2nd time to clear the state), and HW internally flushes the
depth cache on HZ_OP, there is no need to explicitly send a Depth
Cache flush after Clear or Resolve."
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24027>
Diffstat (limited to 'src/intel/vulkan/anv_blorp.c')
| -rw-r--r-- | src/intel/vulkan/anv_blorp.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index e079617375e..952daea937e 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1562,11 +1562,20 @@ anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer, * Even though the PRM provides a bunch of conditions under which this is * supposedly unnecessary, we choose to perform the flush unconditionally * just to be safe. + * + * From Bspec 46959, a programming note applicable to Gfx12+: + * + * "Since HZ_OP has to be sent twice (first time set the clear/resolve state + * and 2nd time to clear the state), and HW internally flushes the depth + * cache on HZ_OP, there is no need to explicitly send a Depth Cache flush + * after Clear or Resolve." */ - anv_add_pending_pipe_bits(cmd_buffer, - ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | - ANV_PIPE_DEPTH_STALL_BIT, - "after clear hiz"); + if (cmd_buffer->device->info->verx10 < 120) { + anv_add_pending_pipe_bits(cmd_buffer, + ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | + ANV_PIPE_DEPTH_STALL_BIT, + "after clear hiz"); + } } static bool |