diff options
| author | Francisco Jerez <currojerez@riseup.net> | 2020-05-29 17:22:55 -0700 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2021-09-02 03:14:37 +0000 |
| commit | cb9f02f86342d1cf1b6a62c23b706d1fc5c9a85f (patch) | |
| tree | 29b6ea0bf98733c02f590fc4b6a87551257a9d4a /src/gallium | |
| parent | c677e76483952fc7ccb96141afe271374f85f040 (diff) | |
iris: Add read-write domain for data cache.
This will allow us to remove the history flushes performed for SSBOs
and instead take advantage of the same mechanism used for tracking
other memory accesses.
v2: Use C99 designated initializers (Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12691>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/iris/iris_bufmgr.h | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/iris/iris_pipe_control.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 6 |
3 files changed, 10 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_bufmgr.h b/src/gallium/drivers/iris/iris_bufmgr.h index 66da1078614..d95f5f8a058 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.h +++ b/src/gallium/drivers/iris/iris_bufmgr.h @@ -105,6 +105,8 @@ enum iris_domain { IRIS_DOMAIN_RENDER_WRITE = 0, /** (Hi)Z/stencil cache. */ IRIS_DOMAIN_DEPTH_WRITE, + /** Data port (HDC) cache. */ + IRIS_DOMAIN_DATA_WRITE, /** Any other read-write cache. */ IRIS_DOMAIN_OTHER_WRITE, /** Vertex cache. */ diff --git a/src/gallium/drivers/iris/iris_pipe_control.c b/src/gallium/drivers/iris/iris_pipe_control.c index 069e52609f7..33c904740da 100644 --- a/src/gallium/drivers/iris/iris_pipe_control.c +++ b/src/gallium/drivers/iris/iris_pipe_control.c @@ -190,6 +190,7 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch, const uint32_t flush_bits[NUM_IRIS_DOMAINS] = { [IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH, [IRIS_DOMAIN_DEPTH_WRITE] = PIPE_CONTROL_DEPTH_CACHE_FLUSH, + [IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_DATA_CACHE_FLUSH, [IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE, [IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD, [IRIS_DOMAIN_OTHER_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD, @@ -197,6 +198,7 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch, const uint32_t invalidate_bits[NUM_IRIS_DOMAINS] = { [IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH, [IRIS_DOMAIN_DEPTH_WRITE] = PIPE_CONTROL_DEPTH_CACHE_FLUSH, + [IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_DATA_CACHE_FLUSH, [IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE, [IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_VF_CACHE_INVALIDATE, [IRIS_DOMAIN_OTHER_READ] = (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index a6d56684c6e..4a3452414dc 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -7380,6 +7380,9 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags) if ((flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_DEPTH_WRITE); + if ((flags & PIPE_CONTROL_DATA_CACHE_FLUSH)) + iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_DATA_WRITE); + if ((flags & PIPE_CONTROL_FLUSH_ENABLE)) iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_OTHER_WRITE); @@ -7396,6 +7399,9 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags) if ((flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_DEPTH_WRITE); + if ((flags & PIPE_CONTROL_DATA_CACHE_FLUSH)) + iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_DATA_WRITE); + if ((flags & PIPE_CONTROL_FLUSH_ENABLE)) iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_OTHER_WRITE); |