diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2020-05-17 02:38:02 -0400 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2020-05-23 03:44:44 -0400 |
| commit | 21504eab78eb465e27520baa7389fa732bfefa36 (patch) | |
| tree | a164720bf5cb35f2507d88083fb25c31cbb6404a /src/gallium/winsys/radeon | |
| parent | 5f365affc906ed9b07857a6fafbb5d51f3f1a607 (diff) | |
ac/gpu_info: compute the best safe IB alignment
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
Diffstat (limited to 'src/gallium/winsys/radeon')
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index a8f3cb3e3bd..002ebe07b55 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -569,7 +569,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 3); ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */ - ws->info.ib_start_alignment = 4096; + ws->info.ib_alignment = 4096; ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40; /* HTILE is broken with 1D tiling on old kernels and GFX7. */ ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != GFX7 || |