amd: rename RING_* enums to AMD_IP_*

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>

2 files changed, 17 insertions, 17 deletions

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 0e1a6e7e64e..44e3758955d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -274,7 +274,7 @@ static unsigned radeon_lookup_or_add_real_buffer(struct radeon_drm_cs *cs,
        * This doesn't have to be done if virtual memory is enabled,
        * because there is no offset patching with virtual memory.
        */
-      if (cs->ip_type != RING_DMA || cs->ws->info.r600_has_virtual_memory) {
+      if (cs->ip_type != AMD_IP_SDMA || cs->ws->info.r600_has_virtual_memory) {
          return i;
       }
    }
@@ -579,7 +579,7 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs,
    struct radeon_cs_context *tmp;
 
    switch (cs->ip_type) {
-   case RING_DMA:
+   case AMD_IP_SDMA:
       /* pad DMA ring to 8 DWs */
       if (cs->ws->info.chip_class <= GFX6) {
          while (rcs->current.cdw & 7)
@@ -589,7 +589,7 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs,
             radeon_emit(rcs, 0x00000000); /* NOP packet */
       }
       break;
-   case RING_GFX:
+   case AMD_IP_GFX:
       /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements
        * r6xx, requires at least 4 dw alignment to avoid a hw bug.
        */
@@ -601,7 +601,7 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs,
             radeon_emit(rcs, 0xffff1000); /* type3 nop packet */
       }
       break;
-   case RING_UVD:
+   case AMD_IP_UVD:
       while (rcs->current.cdw & 15)
          radeon_emit(rcs, 0x80000000); /* type2 nop packet */
       break;
@@ -663,7 +663,7 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs,
       }
 
       switch (cs->ip_type) {
-      case RING_DMA:
+      case AMD_IP_SDMA:
          cs->cst->flags[0] = 0;
          cs->cst->flags[1] = RADEON_CS_RING_DMA;
          cs->cst->cs.num_chunks = 3;
@@ -672,21 +672,21 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs,
          }
          break;
 
-      case RING_UVD:
+      case AMD_IP_UVD:
          cs->cst->flags[0] = 0;
          cs->cst->flags[1] = RADEON_CS_RING_UVD;
          cs->cst->cs.num_chunks = 3;
          break;
 
-      case RING_VCE:
+      case AMD_IP_VCE:
          cs->cst->flags[0] = 0;
          cs->cst->flags[1] = RADEON_CS_RING_VCE;
          cs->cst->cs.num_chunks = 3;
          break;
 
       default:
-      case RING_GFX:
-      case RING_COMPUTE:
+      case AMD_IP_GFX:
+      case AMD_IP_COMPUTE:
          cs->cst->flags[0] = RADEON_CS_KEEP_TILING_FLAGS;
          cs->cst->flags[1] = RADEON_CS_RING_GFX;
          cs->cst->cs.num_chunks = 3;
@@ -699,7 +699,7 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs,
             cs->cst->flags[0] |= RADEON_CS_END_OF_FRAME;
             cs->cst->cs.num_chunks = 3;
          }
-         if (cs->ip_type == RING_COMPUTE) {
+         if (cs->ip_type == AMD_IP_COMPUTE) {
             cs->cst->flags[1] = RADEON_CS_RING_COMPUTE;
             cs->cst->cs.num_chunks = 3;
          }
@@ -724,9 +724,9 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs,
    rcs->used_vram_kb = 0;
    rcs->used_gart_kb = 0;
 
-   if (cs->ip_type == RING_GFX)
+   if (cs->ip_type == AMD_IP_GFX)
       cs->ws->num_gfx_IBs++;
-   else if (cs->ip_type == RING_DMA)
+   else if (cs->ip_type == AMD_IP_SDMA)
       cs->ws->num_sdma_IBs++;
    return 0;
 }
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 31e8cb6e01f..0df473e5df9 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -304,12 +304,12 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
       ws->info.has_dedicated_vram = true;
    }
 
-   ws->info.num_rings[RING_GFX] = 1;
+   ws->info.num_rings[AMD_IP_GFX] = 1;
    /* Check for dma */
-   ws->info.num_rings[RING_DMA] = 0;
+   ws->info.num_rings[AMD_IP_SDMA] = 0;
    /* DMA is disabled on R700. There is IB corruption and hangs. */
    if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
-      ws->info.num_rings[RING_DMA] = 1;
+      ws->info.num_rings[AMD_IP_SDMA] = 1;
    }
 
    /* Check for UVD and VCE */
@@ -321,7 +321,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
       if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
                                "UVD Ring working", &value)) {
          ws->info.has_video_hw.uvd_decode = value;
-         ws->info.num_rings[RING_UVD] = 1;
+         ws->info.num_rings[AMD_IP_UVD] = 1;
       }
 
       value = RADEON_CS_RING_VCE;
@@ -331,7 +331,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
          if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
                                   "VCE FW version", &value)) {
             ws->info.vce_fw_version = value;
-            ws->info.num_rings[RING_VCE] = 1;
+            ws->info.num_rings[AMD_IP_VCE] = 1;
             ws->info.has_video_hw.vce_encode = true;
          }
       }