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authorMarek Olšák <marek.olsak@amd.com>2013-10-08 21:26:34 +0200
committerMarek Olšák <marek.olsak@amd.com>2013-10-25 11:55:55 +0200
commit6067a30838535c838262a9229b400afe4d92c184 (patch)
treec32d65547f27684ff0f8360a71fa1c2cb5b0833c /src/gallium/winsys/radeon/drm/radeon_winsys.h
parent48784f3591a4608509ccad8c73618999765711b3 (diff)
winsys/radeon: add the implementation of fences from r300g
Diffstat (limited to 'src/gallium/winsys/radeon/drm/radeon_winsys.h')
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_winsys.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 581cd841cd8..c0003711bee 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -485,6 +485,29 @@ struct radeon_winsys {
void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
/**
+ * Return a fence associated with the CS. The fence will be signalled
+ * once the CS is flushed and all commands in the CS are completed
+ * by the GPU.
+ */
+ struct pipe_fence_handle *(*cs_create_fence)(struct radeon_winsys_cs *cs);
+
+ /**
+ * Wait for the fence and return true if the fence has been signalled.
+ * The timeout of 0 will only return the status.
+ * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
+ * is signalled.
+ */
+ bool (*fence_wait)(struct radeon_winsys *ws,
+ struct pipe_fence_handle *fence,
+ uint64_t timeout);
+
+ /**
+ * Reference counting for fences.
+ */
+ void (*fence_reference)(struct pipe_fence_handle **dst,
+ struct pipe_fence_handle *src);
+
+ /**
* Initialize surface
*
* \param ws The winsys this function is called from.