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authorGert Wollny <gert.wollny@collabora.com>2023-02-22 17:58:58 +0100
committerMarge Bot <emma+marge@anholt.net>2023-03-16 09:30:00 +0000
commit831e7818aad562be029a00492bd86640bbe7bc59 (patch)
tree30a958be1244b2c6e55157f2ef0dfb6325bbb6f5 /src/gallium/drivers/virgl/virgl_screen.c
parentd53aba56dbc382a8ff93614ca685d7d6ea14314b (diff)
virgl: Enable AMD_vertex_shader_(layer|viewport_index) when host supports it
This increase the number of cases when the texture upload from buffer can use the PBO upload code path. v2: Fix logic combination (Corentin) Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
Diffstat (limited to 'src/gallium/drivers/virgl/virgl_screen.c')
-rw-r--r--src/gallium/drivers/virgl/virgl_screen.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c
index a63b7cb690a..2db9aef280c 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -229,7 +229,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
return 1;
case PIPE_CAP_VS_LAYER_VIEWPORT:
- return 0;
+ return (vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_VS_VERTEX_LAYER) &&
+ (vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_VS_VIEWPORT_INDEX);
case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
return vscreen->caps.caps.v2.max_geom_output_vertices;
case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: