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authorBrian Paul <brianp@vmware.com>2013-03-14 07:45:59 -0600
committerBrian Paul <brianp@vmware.com>2013-03-14 18:17:18 -0600
commitf4a2c29d932b91fe0a311a656b4ce1fa061a4f6b (patch)
treef011559414f88e0ce532d7905c8874e9df24a6d1 /src/gallium/drivers/softpipe/sp_tile_cache.c
parent2f6970ae970860acaaaa21b2354f6e447faf15bd (diff)
softpipe: fix up NUM_ENTRIES confusion
There were two different NUM_ENTRIES #defines for the framebuffer tile cache and the texture tile cache. Rename the later to fix the warnings: In file included from sp_flush.c:40:0: sp_tex_tile_cache.h:76:0: warning: "NUM_ENTRIES" redefined sp_tile_cache.h:78:0: note: this is the location of the previous definition In file included from sp_context.c:50:0: sp_tex_tile_cache.h:76:0: warning: "NUM_ENTRIES" redefined sp_tile_cache.h:78:0: note: this is the location of the previous definition Also, replace occurances of NUM_ENTRIES with Element() macro to be safer. Reviewed-by: José Fonseca <jfonseca@vmware.com>
Diffstat (limited to 'src/gallium/drivers/softpipe/sp_tile_cache.c')
-rw-r--r--src/gallium/drivers/softpipe/sp_tile_cache.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/gallium/drivers/softpipe/sp_tile_cache.c b/src/gallium/drivers/softpipe/sp_tile_cache.c
index b6dd6af48af..1f9c3dd7d5d 100644
--- a/src/gallium/drivers/softpipe/sp_tile_cache.c
+++ b/src/gallium/drivers/softpipe/sp_tile_cache.c
@@ -99,7 +99,7 @@ sp_create_tile_cache( struct pipe_context *pipe )
tc = CALLOC_STRUCT( softpipe_tile_cache );
if (tc) {
tc->pipe = pipe;
- for (pos = 0; pos < NUM_ENTRIES; pos++) {
+ for (pos = 0; pos < Elements(tc->tile_addrs); pos++) {
tc->tile_addrs[pos].bits.invalid = 1;
}
tc->last_tile_addr.bits.invalid = 1;
@@ -134,7 +134,7 @@ sp_destroy_tile_cache(struct softpipe_tile_cache *tc)
if (tc) {
uint pos;
- for (pos = 0; pos < NUM_ENTRIES; pos++) {
+ for (pos = 0; pos < Elements(tc->entries); pos++) {
/*assert(tc->entries[pos].x < 0);*/
FREE( tc->entries[pos] );
}
@@ -419,7 +419,7 @@ sp_flush_tile_cache(struct softpipe_tile_cache *tc)
if (pt) {
/* caching a drawing transfer */
- for (pos = 0; pos < NUM_ENTRIES; pos++) {
+ for (pos = 0; pos < Elements(tc->entries); pos++) {
struct softpipe_cached_tile *tile = tc->entries[pos];
if (!tile)
{
@@ -452,7 +452,7 @@ sp_alloc_tile(struct softpipe_tile_cache *tc)
if (!tc->tile)
{
unsigned pos;
- for (pos = 0; pos < NUM_ENTRIES; ++pos) {
+ for (pos = 0; pos < Elements(tc->entries); ++pos) {
if (!tc->entries[pos])
continue;
@@ -608,7 +608,7 @@ sp_tile_cache_clear(struct softpipe_tile_cache *tc,
/* set flags to indicate all the tiles are cleared */
memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
- for (pos = 0; pos < NUM_ENTRIES; pos++) {
+ for (pos = 0; pos < Elements(tc->tile_addrs); pos++) {
tc->tile_addrs[pos].bits.invalid = 1;
}
tc->last_tile_addr.bits.invalid = 1;