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authorRoland Scheidegger <sroland@vmware.com>2013-03-13 21:19:20 +0100
committerRoland Scheidegger <sroland@vmware.com>2013-03-14 00:21:56 +0100
commit81e728982da61f66c39a44b18460307425c22c1b (patch)
tree8e9b1bcc48bbca50b93712f860afb7161c4b30f3 /src/gallium/drivers/softpipe/sp_tile_cache.c
parent48893156192ff2ffbfaf910dbf51f5f7a904c568 (diff)
softpipe: don't assert when creating surfaces with multiple layers
We can't handle them yet, however we can safely just warn (we will just render to first layer, which is fine since we can't handle rendertarget system value neither). Also make behavior more predictable with buffer surfaces (it would sometimes hit bogus asserts because of the union in the surface, instead create the surface but assert when trying to set a buffer in the framebuffer). Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Diffstat (limited to 'src/gallium/drivers/softpipe/sp_tile_cache.c')
-rw-r--r--src/gallium/drivers/softpipe/sp_tile_cache.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/src/gallium/drivers/softpipe/sp_tile_cache.c b/src/gallium/drivers/softpipe/sp_tile_cache.c
index dded0e17342..b6dd6af48af 100644
--- a/src/gallium/drivers/softpipe/sp_tile_cache.c
+++ b/src/gallium/drivers/softpipe/sp_tile_cache.c
@@ -170,12 +170,18 @@ sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
tc->surface = ps;
if (ps) {
- tc->transfer_map = pipe_transfer_map(pipe, ps->texture,
- ps->u.tex.level, ps->u.tex.first_layer,
- PIPE_TRANSFER_READ_WRITE |
- PIPE_TRANSFER_UNSYNCHRONIZED,
- 0, 0, ps->width, ps->height,
- &tc->transfer);
+ if (ps->texture->target != PIPE_BUFFER) {
+ tc->transfer_map = pipe_transfer_map(pipe, ps->texture,
+ ps->u.tex.level, ps->u.tex.first_layer,
+ PIPE_TRANSFER_READ_WRITE |
+ PIPE_TRANSFER_UNSYNCHRONIZED,
+ 0, 0, ps->width, ps->height,
+ &tc->transfer);
+ }
+ else {
+ /* can't render to buffers */
+ assert(0);
+ }
tc->depth_stencil = util_format_is_depth_or_stencil(ps->format);
}