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authorMarek Olšák <marek.olsak@amd.com>2018-10-06 22:44:36 -0400
committerMarek Olšák <marek.olsak@amd.com>2018-10-16 17:23:25 -0400
commitfcc70e4855c3bde3cadce9d0d1abf8da7106f643 (patch)
tree6c0ccaa5d5dcb71e083930cf5376d2ff57fda8c9 /src/gallium/drivers/radeonsi/si_state_viewport.c
parent25ddb15cfe36ff0d1f47e7b34161b545e6f329a8 (diff)
radeonsi: track context rolls better for the Vega scissor bug workaround
We should get fewer context rolls with the SET_CONTEXT_REG optimization, but it would have been for nothing if the scissor state rolled the context anyway. Don't emit the scissor state if there is no context roll.
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state_viewport.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_state_viewport.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c
index 819c773ba8e..587422e50ca 100644
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -258,6 +258,7 @@ static void si_emit_guardband(struct si_context *ctx)
* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
*/
+ unsigned initial_cdw = ctx->gfx_cs->current.cdw;
radeon_opt_set_context_reg4(ctx, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ,
SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ,
fui(guardband_y), fui(discard_y),
@@ -271,6 +272,8 @@ static void si_emit_guardband(struct si_context *ctx)
S_028BE4_PIX_CENTER(rs->half_pixel_center) |
S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH +
vp_as_scissor.quant_mode));
+ if (initial_cdw != ctx->gfx_cs->current.cdw)
+ ctx->context_roll_counter++;
}
static void si_emit_scissors(struct si_context *ctx)