radeonsi: remove si_vid_join_surfaces and use combined planar allocations

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

2 files changed, 0 insertions, 92 deletions

diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c
index 31b28f76d3a..0b45a5a0f36 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -125,89 +125,3 @@ void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffe
 	si_sdma_clear_buffer(sctx, &buffer->res->b.b, 0, buffer->res->b.b.width0, 0);
 	context->flush(context, NULL, 0);
 }
-
-/**
- * join surfaces into the same buffer with identical tiling params
- * sumup their sizes and replace the backend buffers with a single bo
- */
-void si_vid_join_surfaces(struct si_context *sctx,
-			  struct pb_buffer** buffers[VL_NUM_COMPONENTS],
-			  struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
-{
-	struct radeon_winsys *ws = sctx->ws;;
-	unsigned best_tiling, best_wh, off;
-	unsigned size, alignment;
-	struct pb_buffer *pb;
-	unsigned i, j;
-
-	for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
-		unsigned wh;
-
-		if (!surfaces[i])
-			continue;
-
-		if (sctx->chip_class < GFX9) {
-			/* choose the smallest bank w/h for now */
-			wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
-			if (wh < best_wh) {
-				best_wh = wh;
-				best_tiling = i;
-			}
-		}
-	}
-
-	for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
-		if (!surfaces[i])
-			continue;
-
-		/* adjust the texture layer offsets */
-		off = align(off, surfaces[i]->surf_alignment);
-
-		if (sctx->chip_class < GFX9) {
-			/* copy the tiling parameters */
-			surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
-			surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
-			surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
-			surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
-
-			for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
-				surfaces[i]->u.legacy.level[j].offset += off;
-		} else {
-			surfaces[i]->u.gfx9.surf_offset += off;
-			for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j)
-				surfaces[i]->u.gfx9.offset[j] += off;
-		}
-
-		surfaces[i]->flags |= RADEON_SURF_IMPORTED;
-		off += surfaces[i]->surf_size;
-	}
-
-	for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
-		if (!buffers[i] || !*buffers[i])
-			continue;
-
-		size = align(size, (*buffers[i])->alignment);
-		size += (*buffers[i])->size;
-		alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
-	}
-
-	if (!size)
-		return;
-
-	/* TODO: 2D tiling workaround */
-	alignment *= 2;
-
-	pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM,
-			       RADEON_FLAG_GTT_WC);
-	if (!pb)
-		return;
-
-	for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
-		if (!buffers[i] || !*buffers[i])
-			continue;
-
-		pb_reference(buffers[i], pb);
-	}
-
-	pb_reference(&pb, NULL);
-}
diff --git a/src/gallium/drivers/radeon/radeon_video.h b/src/gallium/drivers/radeon/radeon_video.h
index b7797c05d16..232b7736f7b 100644
--- a/src/gallium/drivers/radeon/radeon_video.h
+++ b/src/gallium/drivers/radeon/radeon_video.h
@@ -60,10 +60,4 @@ bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs,
 /* clear the buffer with zeros */
 void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer);
 
-/* join surfaces into the same buffer with identical tiling params
-   sumup their sizes and replace the backend buffers with a single bo */
-void si_vid_join_surfaces(struct si_context *sctx,
-			  struct pb_buffer** buffers[VL_NUM_COMPONENTS],
-			  struct radeon_surf *surfaces[VL_NUM_COMPONENTS]);
-
 #endif // RADEON_VIDEO_H