diff options
| author | Roland Scheidegger <sroland@vmware.com> | 2010-05-29 01:29:31 +0200 |
|---|---|---|
| committer | Roland Scheidegger <sroland@vmware.com> | 2010-05-29 01:29:31 +0200 |
| commit | 837d32062ee7400e7582c842bb8a69d5beb2a759 (patch) | |
| tree | e38e43d3bd688f80c3ea579e7d8071c984c48e6e /src/gallium/drivers/i965/brw_screen.c | |
| parent | 4bc7b14224bfb9c5efe37e1505345fb90ba69d9e (diff) | |
i965g: adapt to clear interface changes
just like i915g, should in theory support separate depth/stencil clears
(untested), with the same 2d blitter hacks.
Diffstat (limited to 'src/gallium/drivers/i965/brw_screen.c')
| -rw-r--r-- | src/gallium/drivers/i965/brw_screen.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/drivers/i965/brw_screen.c b/src/gallium/drivers/i965/brw_screen.c index 7a7b9c1a5a9..36b0eb6954e 100644 --- a/src/gallium/drivers/i965/brw_screen.c +++ b/src/gallium/drivers/i965/brw_screen.c @@ -188,6 +188,9 @@ brw_get_param(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: return 0; + case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: + /* disable for now */ + return 0; default: return 0; } |