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| author | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-11-18 20:49:54 +0100 |
|---|---|---|
| committer | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-11-30 09:09:50 +0100 |
| commit | 611166b8ed08ce39f835385b8e08e37754edcf7b (patch) | |
| tree | 2e25a22d6fa87c50ac39711980ad05d0186e1c82 /src/gallium/docs | |
| parent | abc887faa108b52f1e622ac8c1a3e30c4f317475 (diff) | |
gallium: add PIPE_CAP_TGSI_CAN_READ_OUTPUTS
Drivers that support this benefit by saving one lowering pass in the
GLSL-to-TGSI conversion.
radeonsi already supports this because all outputs are stored in temporary
variables before the export (except for TCS outputs, which have always
been readable in TGSI anyway due to their special semantics).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium/docs')
| -rw-r--r-- | src/gallium/docs/source/screen.rst | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index 33f233a4cb5..7ac39ffc44f 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -364,6 +364,8 @@ The integer capabilities: * ``PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS``: Whether interleaved stream output mode is able to interleave across buffers. This is required for ARB_transform_feedback3. +* ``PIPE_CAP_TGSI_CAN_READ_OUTPUTS``: Whether every TGSI shader stage can read + from the output file. .. _pipe_capf: |