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| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2018-12-03 22:45:03 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2018-12-05 09:26:31 +0100 |
| commit | 824cfc1ee5e0aba15b676b9363ff32046d96eb42 (patch) | |
| tree | 70a59a4cf0c3f29a6db55c597aa2d8dc90b135bf /src/amd/vulkan/radv_image.c | |
| parent | 2669dbf8810c534025ca0dd10942eb416a94fe4d (diff) | |
radv: rework the TC-compat HTILE hardware bug with COND_EXEC
After investigating on this, it appears that COND_WRITE doesn't
work correctly in some situations. I don't know exactly why does
it fail to update DB_Z_INFO.ZRANGE_PRECISION, but as AMDVLK
also uses COND_EXEC I think there is a reason.
Now the driver stores a new metadata value in order to reflect
the last fast depth clear state. If a TC-compat HTILE is fast cleared
with 0.0f, we have to update ZRANGE_PRECISION to 0 in order to
work around that hardware bug.
This fixes rendering issues with The Forest and DXVK and doesn't
seem to introduce any regressions.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108914
Fixes: 68dead112e7 ("radv: update the ZRANGE_PRECISION value for the TC-compat bug")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Diffstat (limited to 'src/amd/vulkan/radv_image.c')
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 4032906f3c6..090ca70a327 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -870,6 +870,14 @@ radv_image_alloc_htile(struct radv_image *image) /* + 8 for storing the clear values */ image->clear_value_offset = image->htile_offset + image->surface.htile_size; image->size = image->clear_value_offset + 8; + if (radv_image_is_tc_compat_htile(image)) { + /* Metadata for the TC-compatible HTILE hardware bug which + * have to be fixed by updating ZRANGE_PRECISION when doing + * fast depth clears to 0.0f. + */ + image->tc_compat_zrange_offset = image->clear_value_offset + 8; + image->size = image->clear_value_offset + 16; + } image->alignment = align64(image->alignment, image->surface.htile_alignment); } @@ -1014,8 +1022,8 @@ radv_image_create(VkDevice _device, /* Otherwise, try to enable HTILE for depth surfaces. */ if (radv_image_can_enable_htile(image) && !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) { - radv_image_alloc_htile(image); image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE; + radv_image_alloc_htile(image); } else { image->surface.htile_size = 0; } |