diff options
| author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2017-12-29 10:59:27 +0100 |
|---|---|---|
| committer | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2017-12-29 11:21:43 +0100 |
| commit | 516a80b579163ef0894bb2fe2922912ef8599205 (patch) | |
| tree | 7dbc810e52bfd9cb72dda28a41bbbaca841315fa /src/amd/vulkan/radv_image.c | |
| parent | 23f37e98a1a5e8c11dfd55200328701ffb47ebce (diff) | |
Revert "radv/gfx9: fix block compression texture views."
This reverts commit 59515780433837ad3975f8ed20b93cf2fe6870e5.
The mentioned commit causes a hang in DoW3 on Vega.
Fixes: 59515780433 "radv/gfx9: fix block compression texture views."
Acked-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'src/amd/vulkan/radv_image.c')
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index a579a1ef5dc..a1b660a74cd 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1067,41 +1067,6 @@ radv_image_view_init(struct radv_image_view *iview, vk_format_get_blockwidth(image->vk_format)); iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format), vk_format_get_blockheight(image->vk_format)); - /* Comment ported from amdvlk - - * If we have the following image: - * Uncompressed pixels Compressed block sizes (4x4) - * mip0: 22 x 22 6 x 6 - * mip1: 11 x 11 3 x 3 - * mip2: 5 x 5 2 x 2 - * mip3: 2 x 2 1 x 1 - * mip4: 1 x 1 1 x 1 - * - * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is - * calculating the degradation of the block sizes down the mip-chain as follows (straight-up - * divide-by-two integer math): - * mip0: 6x6 - * mip1: 3x3 - * mip2: 1x1 - * mip3: 1x1 - * - * This means that mip2 will be missing texels. - * - * Fix this by calculating the base mip's width and height, then convert that, and round it - * back up to get the level 0 size. Take the max of the converted size and the scaled up size. - */ - if (device->physical_device->rad_info.chip_class >= GFX9 && - vk_format_is_compressed(image->vk_format)) { - unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel); - unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel); - - lvl_width = round_up_u32(lvl_width * vk_format_get_blockwidth(iview->vk_format), - vk_format_get_blockwidth(image->vk_format)); - lvl_height = round_up_u32(lvl_height * vk_format_get_blockheight(iview->vk_format), - vk_format_get_blockheight(image->vk_format)); - - iview->extent.width = MAX2(iview->extent.width, lvl_width << range->baseMipLevel); - iview->extent.height = MAX2(iview->extent.height, lvl_height << range->baseMipLevel); - } } iview->base_layer = range->baseArrayLayer; |