diff options
| author | Rhys Perry <pendingchaos02@gmail.com> | 2021-06-02 16:30:35 +0100 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2021-06-03 03:49:07 +0000 |
| commit | 903f814b78f3bdb6f330889277ada147070bfd7b (patch) | |
| tree | ad217077c8f69861a804d6ad5420b1322157adb9 /src/amd/compiler | |
| parent | bb52484df54ec9824229e99ed64e03e2f3a4cd72 (diff) | |
aco: don't create 4 and 5 dword NSA instructions on GFX10
"stability issues", apparently: https://reviews.llvm.org/D103348
fossil-db (Navi10):
Totals from 4512 (3.01% of 149839) affected shaders:
VGPRs: 221516 -> 223308 (+0.81%); split: -0.07%, +0.88%
CodeSize: 23000080 -> 23070672 (+0.31%); split: -0.08%, +0.39%
MaxWaves: 107718 -> 107496 (-0.21%); split: +0.11%, -0.32%
Instrs: 4321890 -> 4362822 (+0.95%); split: -0.00%, +0.95%
Latency: 71495710 -> 71581476 (+0.12%); split: -0.07%, +0.19%
InvThroughput: 11858568 -> 11938960 (+0.68%); split: -0.00%, +0.68%
VClause: 76575 -> 76585 (+0.01%); split: -0.05%, +0.07%
SClause: 168771 -> 168709 (-0.04%); split: -0.06%, +0.02%
Copies: 182305 -> 221948 (+21.75%); split: -0.00%, +21.75%
PreVGPRs: 194657 -> 195635 (+0.50%); split: -0.00%, +0.50%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: c353895c922 ("aco: use non-sequential addressing")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10898>
Diffstat (limited to 'src/amd/compiler')
| -rw-r--r-- | src/amd/compiler/README-ISA.md | 5 | ||||
| -rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 6 |
2 files changed, 10 insertions, 1 deletions
diff --git a/src/amd/compiler/README-ISA.md b/src/amd/compiler/README-ISA.md index a790522ba4f..cb9d8da0298 100644 --- a/src/amd/compiler/README-ISA.md +++ b/src/amd/compiler/README-ISA.md @@ -250,3 +250,8 @@ Only `s_waitcnt_vscnt null, 0`. Needed even if the first instruction is a load. ### NSAClauseBug "MIMG-NSA in a hard clause has unpredictable results on GFX10.1" + +### NSAMaxSize5 + +NSA MIMG instructions should be limited to 3 dwords before GFX10.3 to avoid +stability issues: https://reviews.llvm.org/D103348 diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 4c0c8871446..3428bd1518f 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -5544,7 +5544,11 @@ static MIMG_instruction *emit_mimg(Builder& bld, aco_opcode op, unsigned wqm_mask=0, Operand vdata=Operand(v1)) { - if (bld.program->chip_class < GFX10) { + /* Limit NSA instructions to 3 dwords on GFX10 to avoid stability issues. */ + unsigned max_nsa_size = bld.program->chip_class >= GFX10_3 ? 13 : 5; + bool use_nsa = bld.program->chip_class >= GFX10 && coords.size() <= max_nsa_size; + + if (!use_nsa) { Temp coord = coords[0]; if (coords.size() > 1) { coord = bld.tmp(RegType::vgpr, coords.size()); |