diff options
| author | Carlos Xiong <clever.xiong@amd.com> | 2014-12-14 22:50:15 -0500 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2017-03-30 14:44:33 +0200 |
| commit | 3bd1380ab2aea14d6187110982b8ba576eefb073 (patch) | |
| tree | 5d0794d76459174ad6cde9416558a1405f520743 /src/amd/addrlib | |
| parent | 8b110f03191624b4a41c729297ecc58adeca2e31 (diff) | |
amdgpu/addrlib: force all zero tile info for linear general.
Diffstat (limited to 'src/amd/addrlib')
| -rw-r--r-- | src/amd/addrlib/r800/ciaddrlib.cpp | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp index f72f5a26935..d4f8c641b37 100644 --- a/src/amd/addrlib/r800/ciaddrlib.cpp +++ b/src/amd/addrlib/r800/ciaddrlib.cpp @@ -555,7 +555,16 @@ ADDR_E_RETURNCODE CiAddrLib::HwlSetupTileCfg( // Global flag to control usage of tileIndex if (UseTileIndex(index)) { - if (static_cast<UINT_32>(index) >= m_noOfEntries) + if (index == TileIndexLinearGeneral) + { + pInfo->banks = 2; + pInfo->bankWidth = 1; + pInfo->bankHeight = 1; + pInfo->macroAspectRatio = 1; + pInfo->tileSplitBytes = 64; + pInfo->pipeConfig = ADDR_PIPECFG_P2; + } + else if (static_cast<UINT_32>(index) >= m_noOfEntries) { returnCode = ADDR_INVALIDPARAMS; } |