summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>2021-04-06 08:50:34 +0200
committerMarge Bot <eric+marge@anholt.net>2021-04-07 17:13:51 +0000
commitd4db68b338a9c6b009fa9d9fa05e13ce0215861b (patch)
tree86f2cd52a5370cfb8d6c8afbf07ee03904b696a7
parent1286e73c2c0c5aac1bbc5a979230e9fd2c4a0600 (diff)
radv: enable DCC stores with MSAA 4x/8x on GFX10+
Should work now. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10052>
-rw-r--r--src/amd/vulkan/radv_image.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 44963dd308b..b8d0590a80f 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -291,14 +291,11 @@ bool radv_image_use_dcc_image_stores(const struct radv_device *device,
* TODO: Enable on more HW. DIMGREY and VANGOGH need a workaround and
* we need more perf analysis.
* https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6796#note_643853
- *
- * DCC with MSAA > 2 samples results in CTS failures (some of dEQP-VK.pipeline.multisample.storage_image.*).
*/
- return (device->physical_device->rad_info.chip_class == GFX10 ||
+ return device->physical_device->rad_info.chip_class == GFX10 ||
(device->physical_device->rad_info.chip_class == GFX10_3 &&
(device->instance->perftest_flags & RADV_PERFTEST_DCC_STORES) &&
- !device->physical_device->use_llvm)) &&
- image->info.samples <= 2;
+ !device->physical_device->use_llvm);
}
/*