diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2017-06-05 19:51:38 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2017-06-07 19:38:39 +0200 |
| commit | d2ee423b69660a219c031abad101decd0ecae327 (patch) | |
| tree | 3414d58d95f398ed714fb1f75ed5c93fba4830dd | |
| parent | e003e3c4c058e69e3dcaee3d31493b27ffc0052c (diff) | |
radeonsi: enable TC-compatible stencil compression on VI
Most things are in place. Ideally we won't see decompress blits for stencil
anymore.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_blit.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 8 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 3 |
3 files changed, 8 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index f5d9048d8c9..500c5bfcf7c 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -332,6 +332,8 @@ si_flush_depth_texture(struct si_context *sctx, } assert(!tex->tc_compatible_htile || levels_z == 0); + assert(!tex->tc_compatible_htile || levels_s == 0 || + !r600_can_sample_zs(tex, true)); /* We may have to allocate the flushed texture here when called from * si_decompress_subresource. diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 61eb2f10be2..7a2b71df6b5 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -339,8 +339,7 @@ static void si_sampler_view_add_buffer(struct si_context *sctx, } if (rtex->htile_buffer && - rtex->tc_compatible_htile && - !is_stencil_sampler) { + rtex->tc_compatible_htile) { radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, rtex->htile_buffer, usage, RADEON_PRIO_HTILE, check_mem); @@ -424,7 +423,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, if (sscreen->b.chip_class <= VI) meta_va += base_level_info->dcc_offset; - } else if (tex->tc_compatible_htile && !is_stencil) { + } else if (tex->tc_compatible_htile) { meta_va = tex->htile_buffer->gpu_address; } @@ -571,7 +570,8 @@ static bool depth_needs_decompression(struct r600_texture *rtex, struct si_sampler_view *sview) { return rtex->db_compatible && - (!rtex->tc_compatible_htile || sview->is_stencil_sampler); + (!rtex->tc_compatible_htile || + !r600_can_sample_zs(rtex, sview->is_stencil_sampler)); } static void si_update_compressed_tex_shader_mask(struct si_context *sctx, diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 77df64397f9..cd069e31a64 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1398,7 +1398,8 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) if (!rtex->tc_compatible_htile) rtex->dirty_level_mask |= 1 << surf->u.tex.level; - if (rtex->surface.flags & RADEON_SURF_SBUFFER) + if (rtex->surface.flags & RADEON_SURF_SBUFFER && + (!rtex->tc_compatible_htile || !rtex->can_sample_s)) rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level; } if (sctx->framebuffer.compressed_cb_mask) { |