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authorIago Toral Quiroga <itoral@igalia.com>2022-06-22 09:43:30 +0200
committerMarge Bot <emma+marge@anholt.net>2022-06-28 05:49:51 +0000
commitcfccd93efc95277a739a202a036cbea36fde85f4 (patch)
treed1345c6accec96c50c5ea428dead68333c2d5a31
parent98420408d0bd0d339c723d6de544a668b2b8f9b6 (diff)
broadcom/compiler: don't predicate postponed spills
The postponed spill is predicated using the condition from the last write, but this is only correct if the register was only written once in the TMU sequence, or if it is always written with the same predication. While we could try to track whether this is the case or not, it would make the postponed spill path even more complex than it already is, so let's just avoid predicating these. We are already discouraging TMU spilling of registers in the middle of TMU sequences, so this should not be a very common case. Cc: mesa-stable Reviewed-by: Alejandro PiƱeiro <apinheiro@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17201>
-rw-r--r--src/broadcom/compiler/vir_register_allocate.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/broadcom/compiler/vir_register_allocate.c b/src/broadcom/compiler/vir_register_allocate.c
index 09107523fb1..ca1428bdfb6 100644
--- a/src/broadcom/compiler/vir_register_allocate.c
+++ b/src/broadcom/compiler/vir_register_allocate.c
@@ -499,6 +499,8 @@ v3d_emit_tmu_spill(struct v3d_compile *c,
c->cursor = vir_after_inst(position);
+ enum v3d_qpu_cond cond = vir_get_cond(inst);
+
/* If inst and position don't match, this is a postponed spill,
* in which case we have already allocated the temp for the spill
* and we should use that, otherwise create a new temp with the
@@ -511,9 +513,15 @@ v3d_emit_tmu_spill(struct v3d_compile *c,
add_node(c, inst->dst.index, class_bits);
} else {
inst->dst = spill_temp;
+
+ /* If this is a postponed spill the register being spilled may
+ * have been written more than once including conditional
+ * writes, so ignore predication on the spill instruction and
+ * always spill the full register.
+ */
+ cond = V3D_QPU_COND_NONE;
}
- enum v3d_qpu_cond cond = vir_get_cond(inst);
struct qinst *tmp =
vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
inst->dst);