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| author | Francisco Jerez <currojerez@riseup.net> | 2021-07-21 14:30:28 -0700 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2022-01-10 18:27:41 -0800 |
| commit | ae5fa3f51834926632377647d8559fabc078c9ec (patch) | |
| tree | 386872b558e13417c9bbb8b82b9f55d8e604b9fe | |
| parent | a748b264e8a52eca5bbfd5b9fdb0d281bcc9f0f5 (diff) | |
intel/genxml: Fix SLICE_HASH_TABLE struct on XeHP.
It's now an array with 7 tables, each table is intended to specify the
pixel pipe hashing behavior for every possible slice count between 2
and 8, however that doesn't actually work, among other reasons due to
hardware bugs that will cause the GPU to erroneously access the table
at the wrong index in some cases, so in practice all 7 tables need to
be initialized to the same value.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569>
| -rw-r--r-- | src/intel/genxml/gen125.xml | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml index 91dfc29c332..bc716687d2c 100644 --- a/src/intel/genxml/gen125.xml +++ b/src/intel/genxml/gen125.xml @@ -1201,10 +1201,12 @@ <field name="Component Override W" start="15" end="15" type="bool"/> </struct> - <struct name="SLICE_HASH_TABLE" length="32"> - <group count="16" start="0" size="64"> - <group count="16" start="0" size="4"> - <field name="Entry" start="0" end="3" type="uint"/> + <struct name="SLICE_HASH_TABLE" length="224"> + <group count="7" start="0" size="1024"> + <group count="16" start="0" size="64"> + <group count="16" start="0" size="4"> + <field name="Entry" start="0" end="3" type="uint"/> + </group> </group> </group> </struct> |