diff options
| author | Dave Airlie <airlied@redhat.com> | 2018-01-24 12:53:26 +1000 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2018-02-09 03:50:10 +0000 |
| commit | a78ff020c6f8ee8e4efaa49d99e9a76299381ca4 (patch) | |
| tree | d8d1bbe2fa301a52bcac60b5fced86e06125a5fd | |
| parent | 5ef3cadf157ce9b868511cb5c13114eb22ba0b51 (diff) | |
radv: move spi_baryc_cntl to pipeline
We need to enable the pos float location 2 mode anytime we have
persample not just when forced by the frag shader.
This fixes:
dEQP-VK.pipeline.multisample.min_sample_shading*
Fixes: 58c97a079 (radv: enable location at sample when persample is forced.)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 298554541da220ebdcd9aa9b9055ede2481d5817)
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 6 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 3 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 1 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index dbae1d79ed9..0a9780b64d5 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -919,7 +919,6 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer, { struct radv_shader_variant *ps; uint64_t va; - unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); struct radv_blend_state *blend = &pipeline->graphics.blend; assert (pipeline->shaders[MESA_SHADER_FRAGMENT]); @@ -941,13 +940,10 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer, radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR, ps->config.spi_ps_input_addr); - if (ps->info.info.ps.force_persample) - spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); - radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL, S_0286D8_NUM_INTERP(ps->info.fs.num_interp)); - radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl); + radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl); radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT, pipeline->graphics.shader_z_format); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index d5adb4c8c99..384804125e0 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -879,6 +879,8 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) | S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */ ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); + if (ps_iter_samples > 1) + pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); } const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order = @@ -1995,6 +1997,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline, radv_create_shaders(pipeline, device, cache, keys, pStages); + pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra); radv_pipeline_init_raster_state(pipeline, pCreateInfo); radv_pipeline_init_multisample_state(pipeline, pCreateInfo); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 1d62b202ff7..ae799e2c829 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1132,6 +1132,7 @@ struct radv_pipeline { struct radv_gs_state gs; uint32_t db_shader_control; uint32_t shader_z_format; + uint32_t spi_baryc_cntl; unsigned prim; unsigned gs_out; uint32_t vgt_gs_mode; |