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authorElie Tournier <tournier.elie@gmail.com>2020-07-16 13:41:15 +0100
committerMarge Bot <eric+marge@anholt.net>2020-07-17 06:19:16 +0000
commit575ab303a80d02fb7eda451f636e013e2d95fa60 (patch)
tree4321307f8931de22a365cb10c581454f7337c268
parenta0f42b89a15eda8b4f05572e7d0ed75ccce8a75a (diff)
virgl: set PIPE_CAP_BLEND_EQUATION_ADVANCED
Signed-off-by: Elie Tournier <elie.tournier@collabora.com> Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5516>
-rw-r--r--src/gallium/drivers/virgl/virgl_screen.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c
index 3591762c9e3..348575d7b9f 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -262,6 +262,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_FBFETCH:
return (vscreen->caps.caps.v2.capability_bits &
VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
+ case PIPE_CAP_BLEND_EQUATION_ADVANCED:
+ return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_BLEND_EQUATION;
case PIPE_CAP_TGSI_CLOCK:
return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
case PIPE_CAP_TGSI_ARRAY_COMPONENTS: