diff options
author | Rhys Perry <pendingchaos02@gmail.com> | 2021-12-07 11:57:34 +0000 |
---|---|---|
committer | Marge Bot <emma+marge@anholt.net> | 2021-12-08 11:07:40 +0000 |
commit | 420170fabc1152339ca81b8c962c1884b3d9f856 (patch) | |
tree | e363ba7d5d2f3f9875257f1d687c8d6fe754e03e | |
parent | 85161fb8ac1b926b2222b4a860168d73c33a5801 (diff) |
radv: initialize workgroup_size in radv_meta_init_shader
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14087>
-rw-r--r-- | src/amd/vulkan/radv_acceleration_structure.c | 6 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta.c | 3 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_buffer.c | 4 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_bufimage.c | 7 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 3 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_copy_vrs_htile.c | 1 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_dcc_retile.c | 1 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_decompress.c | 1 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_fast_clear.c | 1 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_fmask_copy.c | 1 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_fmask_expand.c | 1 | ||||
-rw-r--r-- | src/amd/vulkan/radv_meta_resolve_cs.c | 2 | ||||
-rw-r--r-- | src/amd/vulkan/radv_query.c | 8 |
13 files changed, 3 insertions, 36 deletions
diff --git a/src/amd/vulkan/radv_acceleration_structure.c b/src/amd/vulkan/radv_acceleration_structure.c index eb9d207ade9..edc3156acde 100644 --- a/src/amd/vulkan/radv_acceleration_structure.c +++ b/src/amd/vulkan/radv_acceleration_structure.c @@ -919,8 +919,6 @@ build_leaf_shader(struct radv_device *dev) nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_build_leaf_shader"); b.shader->info.workgroup_size[0] = 64; - b.shader->info.workgroup_size[1] = 1; - b.shader->info.workgroup_size[2] = 1; nir_ssa_def *pconst0 = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .base = 0, .range = 16); @@ -1264,8 +1262,6 @@ build_internal_shader(struct radv_device *dev) nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_build_internal_shader"); b.shader->info.workgroup_size[0] = 64; - b.shader->info.workgroup_size[1] = 1; - b.shader->info.workgroup_size[2] = 1; /* * push constants: @@ -1375,8 +1371,6 @@ build_copy_shader(struct radv_device *dev) { nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_copy"); b.shader->info.workgroup_size[0] = 64; - b.shader->info.workgroup_size[1] = 1; - b.shader->info.workgroup_size[2] = 1; nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b); nir_ssa_def *wg_id = nir_load_workgroup_id(&b, 32); diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c index af4652b30f4..8ee6ef4c60b 100644 --- a/src/amd/vulkan/radv_meta.c +++ b/src/amd/vulkan/radv_meta.c @@ -565,6 +565,9 @@ nir_builder PRINTFLIKE(2, 3) radv_meta_init_shader(gl_shader_stage stage, const } b.shader->info.internal = true; + b.shader->info.workgroup_size[0] = 1; + b.shader->info.workgroup_size[1] = 1; + b.shader->info.workgroup_size[2] = 1; return b; } diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c index 721acca4224..8fc28e656c3 100644 --- a/src/amd/vulkan/radv_meta_buffer.c +++ b/src/amd/vulkan/radv_meta_buffer.c @@ -9,8 +9,6 @@ build_buffer_fill_shader(struct radv_device *dev) { nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_buffer_fill"); b.shader->info.workgroup_size[0] = 64; - b.shader->info.workgroup_size[1] = 1; - b.shader->info.workgroup_size[2] = 1; nir_ssa_def *global_id = get_global_ids(&b, 1); @@ -33,8 +31,6 @@ build_buffer_copy_shader(struct radv_device *dev) { nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_buffer_copy"); b.shader->info.workgroup_size[0] = 64; - b.shader->info.workgroup_size[1] = 1; - b.shader->info.workgroup_size[2] = 1; nir_ssa_def *global_id = get_global_ids(&b, 1); diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index 1448ca2cf51..22bdd478ac5 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -42,7 +42,6 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d) radv_meta_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs"); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex"); input_img->data.descriptor_set = 0; input_img->data.binding = 0; @@ -224,7 +223,6 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d) radv_meta_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs"); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, buf_type, "s_tex"); input_img->data.descriptor_set = 0; input_img->data.binding = 0; @@ -403,7 +401,6 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev) nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_btoi_r32g32b32_cs"); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, buf_type, "s_tex"); input_img->data.descriptor_set = 0; input_img->data.binding = 0; @@ -557,7 +554,6 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d, int samples) is_3d ? "meta_itoi_cs_3d-%d" : "meta_itoi_cs-%d", samples); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, buf_type, "s_tex"); input_img->data.descriptor_set = 0; input_img->data.binding = 0; @@ -756,7 +752,6 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev) nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_itoi_r32g32b32_cs"); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, type, "input_img"); input_img->data.descriptor_set = 0; input_img->data.binding = 0; @@ -916,7 +911,6 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples MESA_SHADER_COMPUTE, is_3d ? "meta_cleari_cs_3d-%d" : "meta_cleari_cs-%d", samples); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *output_img = nir_variable_create(b.shader, nir_var_image, img_type, "out_img"); output_img->data.descriptor_set = 0; @@ -1073,7 +1067,6 @@ build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev) nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_cleari_r32g32b32_cs"); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *output_img = nir_variable_create(b.shader, nir_var_image, img_type, "out_img"); output_img->data.descriptor_set = 0; diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index a0aa2a1fe49..0ed9db3d183 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1060,8 +1060,6 @@ build_clear_htile_mask_shader() { nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_clear_htile_mask"); b.shader->info.workgroup_size[0] = 64; - b.shader->info.workgroup_size[1] = 1; - b.shader->info.workgroup_size[2] = 1; nir_ssa_def *global_id = get_global_ids(&b, 1); @@ -1165,7 +1163,6 @@ build_clear_dcc_comp_to_single_shader(bool is_msaa) is_msaa ? "multisampled" : "singlesampled"); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_ssa_def *global_id = get_global_ids(&b, 3); diff --git a/src/amd/vulkan/radv_meta_copy_vrs_htile.c b/src/amd/vulkan/radv_meta_copy_vrs_htile.c index d223c8570f6..a5f3dd7be4b 100644 --- a/src/amd/vulkan/radv_meta_copy_vrs_htile.c +++ b/src/amd/vulkan/radv_meta_copy_vrs_htile.c @@ -47,7 +47,6 @@ build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_copy_vrs_htile"); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; /* Get coordinates. */ nir_ssa_def *global_id = get_global_ids(&b, 2); diff --git a/src/amd/vulkan/radv_meta_dcc_retile.c b/src/amd/vulkan/radv_meta_dcc_retile.c index df6377f968f..06a2e9c89c3 100644 --- a/src/amd/vulkan/radv_meta_dcc_retile.c +++ b/src/amd/vulkan/radv_meta_dcc_retile.c @@ -36,7 +36,6 @@ build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *sur b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_ssa_def *src_dcc_size = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8); nir_ssa_def *src_dcc_pitch = nir_channels(&b, src_dcc_size, 1); diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c index 19b66d64d23..9824657b64e 100644 --- a/src/amd/vulkan/radv_meta_decompress.c +++ b/src/amd/vulkan/radv_meta_decompress.c @@ -43,7 +43,6 @@ build_expand_depth_stencil_compute_shader(struct radv_device *dev) /* We need at least 8/8/1 to cover an entire HTILE block in a single workgroup. */ b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *input_img = nir_variable_create(b.shader, nir_var_image, img_type, "in_img"); input_img->data.descriptor_set = 0; input_img->data.binding = 0; diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index c85b8b13fd5..8757872965d 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -44,7 +44,6 @@ build_dcc_decompress_compute_shader(struct radv_device *dev) /* We need at least 16/16/1 to cover an entire DCC block in a single workgroup. */ b.shader->info.workgroup_size[0] = 16; b.shader->info.workgroup_size[1] = 16; - b.shader->info.workgroup_size[2] = 1; nir_variable *input_img = nir_variable_create(b.shader, nir_var_image, img_type, "in_img"); input_img->data.descriptor_set = 0; input_img->data.binding = 0; diff --git a/src/amd/vulkan/radv_meta_fmask_copy.c b/src/amd/vulkan/radv_meta_fmask_copy.c index 91de7942e64..b52eedb3c5f 100644 --- a/src/amd/vulkan/radv_meta_fmask_copy.c +++ b/src/amd/vulkan/radv_meta_fmask_copy.c @@ -33,7 +33,6 @@ build_fmask_copy_compute_shader(struct radv_device *dev, int samples) b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex"); input_img->data.descriptor_set = 0; diff --git a/src/amd/vulkan/radv_meta_fmask_expand.c b/src/amd/vulkan/radv_meta_fmask_expand.c index 866b2909076..329985a83e0 100644 --- a/src/amd/vulkan/radv_meta_fmask_expand.c +++ b/src/amd/vulkan/radv_meta_fmask_expand.c @@ -36,7 +36,6 @@ build_fmask_expand_compute_shader(struct radv_device *device, int samples) nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_fmask_expand_cs-%d", samples); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, type, "s_tex"); input_img->data.descriptor_set = 0; diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c index 8ab75ab9752..a3da78a3355 100644 --- a/src/amd/vulkan/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/radv_meta_resolve_cs.c @@ -68,7 +68,6 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s is_integer ? "int" : (is_srgb ? "srgb" : "float")); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex"); input_img->data.descriptor_set = 0; @@ -140,7 +139,6 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples, get_resolve_mode_str(resolve_mode), samples); b.shader->info.workgroup_size[0] = 8; b.shader->info.workgroup_size[1] = 8; - b.shader->info.workgroup_size[2] = 1; nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex"); input_img->data.descriptor_set = 0; diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index f73ab58999f..6e92eb4dd92 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -119,8 +119,6 @@ build_occlusion_query_shader(struct radv_device *device) */ nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "occlusion_query"); b.shader->info.workgroup_size[0] = 64; - b.shader->info.workgroup_size[1] = 1; - b.shader->info.workgroup_size[2] = 1; nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result"); nir_variable *outer_counter = @@ -257,8 +255,6 @@ build_pipeline_statistics_query_shader(struct radv_device *device) */ nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "pipeline_statistics_query"); b.shader->info.workgroup_size[0] = 64; - b.shader->info.workgroup_size[1] = 1; - b.shader->info.workgroup_size[2] = 1; nir_variable *output_offset = nir_local_variable_create(b.impl, glsl_int_type(), "output_offset"); @@ -397,8 +393,6 @@ build_tfb_query_shader(struct radv_device *device) */ nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "tfb_query"); b.shader->info.workgroup_size[0] = 64; - b.shader->info.workgroup_size[1] = 1; - b.shader->info.workgroup_size[2] = 1; /* Create and initialize local variables. */ nir_variable *result = @@ -522,8 +516,6 @@ build_timestamp_query_shader(struct radv_device *device) */ nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "timestamp_query"); b.shader->info.workgroup_size[0] = 64; - b.shader->info.workgroup_size[1] = 1; - b.shader->info.workgroup_size[2] = 1; /* Create and initialize local variables. */ nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result"); |