diff options
| author | Jason Ekstrand <jason@jlekstrand.net> | 2020-01-22 22:54:20 -0600 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2020-01-24 19:18:27 +0000 |
| commit | 3b2eafbea959183c5ef27b11620edacaf8e92c8b (patch) | |
| tree | 2964b235d92a2df3fe218e9cd29411f006a31995 | |
| parent | c70a786c77370bbc47f71a9f529d50116fd511da (diff) | |
intel/fs: Don't unnecessarily fall back to indirect sends on Gen12
The instruction encoding for SENDS changed on Gen12 and it now supports
embedding the entire extended message descriptor in the instruction if
it's an immediate. Stop falling back to doing an indirect SEND just
because we had something in [15:12] of ex_desc.ud.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
| -rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 427b01e789b..1938dd65f4d 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -2677,7 +2677,7 @@ brw_send_indirect_split_message(struct brw_codegen *p, } if (ex_desc.file == BRW_IMMEDIATE_VALUE && - (ex_desc.ud & INTEL_MASK(15, 12)) == 0) { + (devinfo->gen >= 12 || (ex_desc.ud & INTEL_MASK(15, 12)) == 0)) { ex_desc.ud |= ex_desc_imm; } else { const struct tgl_swsb swsb = brw_get_default_swsb(p); @@ -2703,8 +2703,9 @@ brw_send_indirect_split_message(struct brw_codegen *p, unsigned imm_part = ex_desc_imm | sfid | eot << 5; if (ex_desc.file == BRW_IMMEDIATE_VALUE) { - /* ex_desc bits 15:12 don't exist in the instruction encoding, so - * we may have fallen back to an indirect extended descriptor. + /* ex_desc bits 15:12 don't exist in the instruction encoding prior + * to Gen12, so we may have fallen back to an indirect extended + * descriptor. */ brw_MOV(p, addr, brw_imm_ud(ex_desc.ud | imm_part)); } else { |