diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2022-05-12 02:50:17 -0400 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2022-05-13 14:56:22 -0400 |
| commit | 39800f0fa3104c56736d5beb70a7920a33be48de (patch) | |
| tree | 8c658b5a75bc52b5fe0a66c09d4f326438cf4508 | |
| parent | 6dcf7f651f421c0f46ebf9c4c5904f452ea14eb1 (diff) | |
amd: change chip_class naming to "enum amd_gfx_level gfx_level"
This aligns the naming with PAL.
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>
198 files changed, 2775 insertions, 2776 deletions
diff --git a/src/amd/common/ac_binary.c b/src/amd/common/ac_binary.c index 080ffbb6321..3fa0cc88334 100644 --- a/src/amd/common/ac_binary.c +++ b/src/amd/common/ac_binary.c @@ -92,7 +92,7 @@ void ac_parse_shader_binary_config(const char *data, size_t nbytes, unsigned wav break; case R_0286E8_SPI_TMPRING_SIZE: case R_00B860_COMPUTE_TMPRING_SIZE: - if (info->chip_class >= GFX11) + if (info->gfx_level >= GFX11) conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(value) * 256; else conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(value) * 1024; @@ -126,7 +126,7 @@ void ac_parse_shader_binary_config(const char *data, size_t nbytes, unsigned wav * * For shader-db stats, set num_vgprs that the hw actually uses. */ - if (info->chip_class == GFX10_3) { + if (info->gfx_level == GFX10_3) { conf->num_vgprs = align(conf->num_vgprs, wave_size == 32 ? 16 : 8); } diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c index 9e6f4603f96..a9b45cf66c4 100644 --- a/src/amd/common/ac_debug.c +++ b/src/amd/common/ac_debug.c @@ -67,7 +67,7 @@ struct ac_ib_parser { unsigned num_dw; const int *trace_ids; unsigned trace_id_count; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; ac_debug_addr_callback addr_callback; void *addr_callback_data; @@ -109,12 +109,12 @@ static void print_named_value(FILE *file, const char *name, uint32_t value, int print_value(file, value, bits); } -static const struct si_reg *find_register(enum chip_class chip_class, unsigned offset) +static const struct si_reg *find_register(enum amd_gfx_level gfx_level, unsigned offset) { const struct si_reg *table; unsigned table_size; - switch (chip_class) { + switch (gfx_level) { case GFX11: table = gfx11_reg_table; table_size = ARRAY_SIZE(gfx11_reg_table); @@ -154,17 +154,17 @@ static const struct si_reg *find_register(enum chip_class chip_class, unsigned o return NULL; } -const char *ac_get_register_name(enum chip_class chip_class, unsigned offset) +const char *ac_get_register_name(enum amd_gfx_level gfx_level, unsigned offset) { - const struct si_reg *reg = find_register(chip_class, offset); + const struct si_reg *reg = find_register(gfx_level, offset); return reg ? sid_strings + reg->name_offset : "(no name)"; } -void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset, uint32_t value, +void ac_dump_reg(FILE *file, enum amd_gfx_level gfx_level, unsigned offset, uint32_t value, uint32_t field_mask) { - const struct si_reg *reg = find_register(chip_class, offset); + const struct si_reg *reg = find_register(gfx_level, offset); if (reg) { const char *reg_name = sid_strings + reg->name_offset; @@ -252,7 +252,7 @@ static void ac_parse_set_reg_packet(FILE *f, unsigned count, unsigned reg_offset } for (i = 0; i < count; i++) - ac_dump_reg(f, ib->chip_class, reg + i * 4, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, reg + i * 4, ac_ib_get(ib), ~0); } static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib, @@ -297,30 +297,30 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib, ac_parse_set_reg_packet(f, count, SI_SH_REG_OFFSET, ib); break; case PKT3_ACQUIRE_MEM: - ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_030230_CP_COHER_SIZE_HI, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_0301E4_CP_COHER_BASE_HI, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_030230_CP_COHER_SIZE_HI, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0301E4_CP_COHER_BASE_HI, ac_ib_get(ib), ~0); print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16); - if (ib->chip_class >= GFX10) - ac_dump_reg(f, ib->chip_class, R_586_GCR_CNTL, ac_ib_get(ib), ~0); + if (ib->gfx_level >= GFX10) + ac_dump_reg(f, ib->gfx_level, R_586_GCR_CNTL, ac_ib_get(ib), ~0); break; case PKT3_SURFACE_SYNC: - if (ib->chip_class >= GFX7) { - ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0); + if (ib->gfx_level >= GFX7) { + ac_dump_reg(f, ib->gfx_level, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0); } else { - ac_dump_reg(f, ib->chip_class, R_0085F0_CP_COHER_CNTL, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_0085F4_CP_COHER_SIZE, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_0085F8_CP_COHER_BASE, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0085F0_CP_COHER_CNTL, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0085F4_CP_COHER_SIZE, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0085F8_CP_COHER_BASE, ac_ib_get(ib), ~0); } print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16); break; case PKT3_EVENT_WRITE: { uint32_t event_dw = ac_ib_get(ib); - ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw, + ac_dump_reg(f, ib->gfx_level, R_028A90_VGT_EVENT_INITIATOR, event_dw, S_028A90_EVENT_TYPE(~0)); print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4); print_named_value(f, "INV_L2", (event_dw >> 20) & 0x1, 1); @@ -332,7 +332,7 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib, } case PKT3_EVENT_WRITE_EOP: { uint32_t event_dw = ac_ib_get(ib); - ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw, + ac_dump_reg(f, ib->gfx_level, R_028A90_VGT_EVENT_INITIATOR, event_dw, S_028A90_EVENT_TYPE(~0)); print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4); print_named_value(f, "TCL1_VOL_ACTION_ENA", (event_dw >> 12) & 0x1, 1); @@ -352,10 +352,10 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib, } case PKT3_RELEASE_MEM: { uint32_t event_dw = ac_ib_get(ib); - if (ib->chip_class >= GFX10) { - ac_dump_reg(f, ib->chip_class, R_490_RELEASE_MEM_OP, event_dw, ~0u); + if (ib->gfx_level >= GFX10) { + ac_dump_reg(f, ib->gfx_level, R_490_RELEASE_MEM_OP, event_dw, ~0u); } else { - ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw, + ac_dump_reg(f, ib->gfx_level, R_028A90_VGT_EVENT_INITIATOR, event_dw, S_028A90_EVENT_TYPE(~0)); print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4); print_named_value(f, "TCL1_VOL_ACTION_ENA", (event_dw >> 12) & 0x1, 1); @@ -387,52 +387,52 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib, print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16); break; case PKT3_DRAW_INDEX_AUTO: - ac_dump_reg(f, ib->chip_class, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0); break; case PKT3_DRAW_INDEX_2: - ac_dump_reg(f, ib->chip_class, R_028A78_VGT_DMA_MAX_SIZE, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_0287E8_VGT_DMA_BASE, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_0287E4_VGT_DMA_BASE_HI, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_028A78_VGT_DMA_MAX_SIZE, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0287E8_VGT_DMA_BASE, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0287E4_VGT_DMA_BASE_HI, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0); break; case PKT3_INDEX_TYPE: - ac_dump_reg(f, ib->chip_class, R_028A7C_VGT_DMA_INDEX_TYPE, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_028A7C_VGT_DMA_INDEX_TYPE, ac_ib_get(ib), ~0); break; case PKT3_NUM_INSTANCES: - ac_dump_reg(f, ib->chip_class, R_030934_VGT_NUM_INSTANCES, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_030934_VGT_NUM_INSTANCES, ac_ib_get(ib), ~0); break; case PKT3_WRITE_DATA: - ac_dump_reg(f, ib->chip_class, R_370_CONTROL, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_371_DST_ADDR_LO, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_372_DST_ADDR_HI, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_370_CONTROL, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_371_DST_ADDR_LO, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_372_DST_ADDR_HI, ac_ib_get(ib), ~0); /* The payload is written automatically */ break; case PKT3_CP_DMA: - ac_dump_reg(f, ib->chip_class, R_410_CP_DMA_WORD0, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_411_CP_DMA_WORD1, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_412_CP_DMA_WORD2, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_413_CP_DMA_WORD3, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_415_COMMAND, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_410_CP_DMA_WORD0, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_411_CP_DMA_WORD1, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_412_CP_DMA_WORD2, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_413_CP_DMA_WORD3, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_415_COMMAND, ac_ib_get(ib), ~0); break; case PKT3_DMA_DATA: - ac_dump_reg(f, ib->chip_class, R_500_DMA_DATA_WORD0, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_501_SRC_ADDR_LO, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_502_SRC_ADDR_HI, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_503_DST_ADDR_LO, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_504_DST_ADDR_HI, ac_ib_get(ib), ~0); - ac_dump_reg(f, ib->chip_class, R_415_COMMAND, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_500_DMA_DATA_WORD0, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_501_SRC_ADDR_LO, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_502_SRC_ADDR_HI, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_503_DST_ADDR_LO, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_504_DST_ADDR_HI, ac_ib_get(ib), ~0); + ac_dump_reg(f, ib->gfx_level, R_415_COMMAND, ac_ib_get(ib), ~0); break; case PKT3_INDIRECT_BUFFER_SI: case PKT3_INDIRECT_BUFFER_CONST: case PKT3_INDIRECT_BUFFER_CIK: { uint32_t base_lo_dw = ac_ib_get(ib); - ac_dump_reg(f, ib->chip_class, R_3F0_IB_BASE_LO, base_lo_dw, ~0); + ac_dump_reg(f, ib->gfx_level, R_3F0_IB_BASE_LO, base_lo_dw, ~0); uint32_t base_hi_dw = ac_ib_get(ib); - ac_dump_reg(f, ib->chip_class, R_3F1_IB_BASE_HI, base_hi_dw, ~0); + ac_dump_reg(f, ib->gfx_level, R_3F1_IB_BASE_HI, base_hi_dw, ~0); uint32_t control_dw = ac_ib_get(ib); - ac_dump_reg(f, ib->chip_class, R_3F2_IB_CONTROL, control_dw, ~0); + ac_dump_reg(f, ib->gfx_level, R_3F2_IB_CONTROL, control_dw, ~0); if (!ib->addr_callback) break; @@ -590,7 +590,7 @@ static void format_ib_output(FILE *f, char *out) * \param f file * \param ib_ptr IB * \param num_dw size of the IB - * \param chip_class chip class + * \param gfx_level gfx level * \param trace_ids the last trace IDs that are known to have been reached * and executed by the CP, typically read from a buffer * \param trace_id_count The number of entries in the trace_ids array. @@ -599,7 +599,7 @@ static void format_ib_output(FILE *f, char *out) * \param addr_callback_data user data for addr_callback */ void ac_parse_ib_chunk(FILE *f, uint32_t *ib_ptr, int num_dw, const int *trace_ids, - unsigned trace_id_count, enum chip_class chip_class, + unsigned trace_id_count, enum amd_gfx_level gfx_level, ac_debug_addr_callback addr_callback, void *addr_callback_data) { struct ac_ib_parser ib = {0}; @@ -607,7 +607,7 @@ void ac_parse_ib_chunk(FILE *f, uint32_t *ib_ptr, int num_dw, const int *trace_i ib.num_dw = num_dw; ib.trace_ids = trace_ids; ib.trace_id_count = trace_id_count; - ib.chip_class = chip_class; + ib.gfx_level = gfx_level; ib.addr_callback = addr_callback; ib.addr_callback_data = addr_callback_data; @@ -637,7 +637,7 @@ void ac_parse_ib_chunk(FILE *f, uint32_t *ib_ptr, int num_dw, const int *trace_i * \param f file * \param ib IB * \param num_dw size of the IB - * \param chip_class chip class + * \param gfx_level gfx level * \param trace_ids the last trace IDs that are known to have been reached * and executed by the CP, typically read from a buffer * \param trace_id_count The number of entries in the trace_ids array. @@ -646,12 +646,12 @@ void ac_parse_ib_chunk(FILE *f, uint32_t *ib_ptr, int num_dw, const int *trace_i * \param addr_callback_data user data for addr_callback */ void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids, unsigned trace_id_count, - const char *name, enum chip_class chip_class, ac_debug_addr_callback addr_callback, + const char *name, enum amd_gfx_level gfx_level, ac_debug_addr_callback addr_callback, void *addr_callback_data) { fprintf(f, "------------------ %s begin ------------------\n", name); - ac_parse_ib_chunk(f, ib, num_dw, trace_ids, trace_id_count, chip_class, addr_callback, + ac_parse_ib_chunk(f, ib, num_dw, trace_ids, trace_id_count, gfx_level, addr_callback, addr_callback_data); fprintf(f, "------------------- %s end -------------------\n\n", name); @@ -660,11 +660,11 @@ void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids, unsign /** * Parse dmesg and return TRUE if a VM fault has been detected. * - * \param chip_class chip class + * \param gfx_level gfx level * \param old_dmesg_timestamp previous dmesg timestamp parsed at init time * \param out_addr detected VM fault addr */ -bool ac_vm_fault_occured(enum chip_class chip_class, uint64_t *old_dmesg_timestamp, +bool ac_vm_fault_occured(enum amd_gfx_level gfx_level, uint64_t *old_dmesg_timestamp, uint64_t *out_addr) { #ifdef _WIN32 @@ -722,7 +722,7 @@ bool ac_vm_fault_occured(enum chip_class chip_class, uint64_t *old_dmesg_timesta const char *header_line, *addr_line_prefix, *addr_line_format; - if (chip_class >= GFX9) { + if (gfx_level >= GFX9) { /* Match this: * ..: [gfxhub] VMC page fault (src_id:0 ring:158 vm_id:2 pas_id:0) * ..: at page 0x0000000219f8f000 from 27 @@ -802,7 +802,7 @@ static int compare_wave(const void *p1, const void *p2) } /* Return wave information. "waves" should be a large enough array. */ -unsigned ac_get_wave_info(enum chip_class chip_class, +unsigned ac_get_wave_info(enum amd_gfx_level gfx_level, struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP]) { #ifdef _WIN32 @@ -811,7 +811,7 @@ unsigned ac_get_wave_info(enum chip_class chip_class, char line[2000], cmd[128]; unsigned num_waves = 0; - sprintf(cmd, "umr -O halt_waves -wa %s", chip_class >= GFX10 ? "gfx_0.0.0" : "gfx"); + sprintf(cmd, "umr -O halt_waves -wa %s", gfx_level >= GFX10 ? "gfx_0.0.0" : "gfx"); FILE *p = popen(cmd, "r"); if (!p) diff --git a/src/amd/common/ac_debug.h b/src/amd/common/ac_debug.h index 72441f7d6cc..9ced4de06ae 100644 --- a/src/amd/common/ac_debug.h +++ b/src/amd/common/ac_debug.h @@ -56,20 +56,20 @@ struct ac_wave_info { typedef void *(*ac_debug_addr_callback)(void *data, uint64_t addr); -const char *ac_get_register_name(enum chip_class chip_class, unsigned offset); -void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset, uint32_t value, +const char *ac_get_register_name(enum amd_gfx_level gfx_level, unsigned offset); +void ac_dump_reg(FILE *file, enum amd_gfx_level gfx_level, unsigned offset, uint32_t value, uint32_t field_mask); void ac_parse_ib_chunk(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids, - unsigned trace_id_count, enum chip_class chip_class, + unsigned trace_id_count, enum amd_gfx_level gfx_level, ac_debug_addr_callback addr_callback, void *addr_callback_data); void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids, unsigned trace_id_count, - const char *name, enum chip_class chip_class, ac_debug_addr_callback addr_callback, + const char *name, enum amd_gfx_level gfx_level, ac_debug_addr_callback addr_callback, void *addr_callback_data); -bool ac_vm_fault_occured(enum chip_class chip_class, uint64_t *old_dmesg_timestamp, +bool ac_vm_fault_occured(enum amd_gfx_level gfx_level, uint64_t *old_dmesg_timestamp, uint64_t *out_addr); -unsigned ac_get_wave_info(enum chip_class chip_class, +unsigned ac_get_wave_info(enum amd_gfx_level gfx_level, struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP]); #ifdef __cplusplus diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 75a582514fe..16e9ec82a62 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -318,7 +318,7 @@ has_tmz_support(amdgpu_device_handle dev, return false; /* Find out ourselves if TMZ is enabled */ - if (info->chip_class < GFX9) + if (info->gfx_level < GFX9) return false; if (info->drm_minor < 36) @@ -758,32 +758,32 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->lowercase_name[i] = tolower(info->name[i]); if (info->family >= CHIP_GFX1100) - info->chip_class = GFX11; + info->gfx_level = GFX11; else if (info->family >= CHIP_SIENNA_CICHLID) - info->chip_class = GFX10_3; + info->gfx_level = GFX10_3; else if (info->family >= CHIP_NAVI10) - info->chip_class = GFX10; + info->gfx_level = GFX10; else if (info->family >= CHIP_VEGA10) - info->chip_class = GFX9; + info->gfx_level = GFX9; else if (info->family >= CHIP_TONGA) - info->chip_class = GFX8; + info->gfx_level = GFX8; else if (info->family >= CHIP_BONAIRE) - info->chip_class = GFX7; + info->gfx_level = GFX7; else if (info->family >= CHIP_TAHITI) - info->chip_class = GFX6; + info->gfx_level = GFX6; else { fprintf(stderr, "amdgpu: Unknown family.\n"); return false; } /* Fix incorrect IP versions reported by the kernel. */ - if (info->chip_class == GFX10_3) + if (info->gfx_level == GFX10_3) info->ip[AMD_IP_GFX].ver_minor = info->ip[AMD_IP_COMPUTE].ver_minor = 3; - else if (info->chip_class == GFX10) + else if (info->gfx_level == GFX10) info->ip[AMD_IP_GFX].ver_minor = info->ip[AMD_IP_COMPUTE].ver_minor = 1; info->smart_access_memory = info->all_vram_visible && - info->chip_class >= GFX10_3 && + info->gfx_level >= GFX10_3 && util_get_cpu_caps()->family >= CPU_AMD_ZEN3 && util_get_cpu_caps()->family < CPU_AMD_LAST; @@ -809,7 +809,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->vram_bit_width = amdinfo->vram_bit_width; /* Set which chips have uncached device memory. */ - info->has_l2_uncached = info->chip_class >= GFX9; + info->has_l2_uncached = info->gfx_level >= GFX9; /* Set hardware information. */ /* convert the shader/memory clocks from KHz to MHz */ @@ -836,17 +836,17 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->si_TA_CS_BC_BASE_ADDR_allowed = true; info->has_bo_metadata = true; info->has_gpu_reset_status_query = true; - info->has_eqaa_surface_allocator = info->chip_class < GFX11; + info->has_eqaa_surface_allocator = info->gfx_level < GFX11; info->has_format_bc1_through_bc7 = true; /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */ - info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 || info->drm_minor >= 2; + info->kernel_flushes_tc_l2_after_ib = info->gfx_level != GFX8 || info->drm_minor >= 2; info->has_indirect_compute_dispatch = true; /* GFX6 doesn't support unaligned loads. */ - info->has_unaligned_shader_loads = info->chip_class != GFX6; + info->has_unaligned_shader_loads = info->gfx_level != GFX6; /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once * these faults are mitigated in software. */ - info->has_sparse_vm_mappings = info->chip_class >= GFX7 && info->drm_minor >= 13; + info->has_sparse_vm_mappings = info->gfx_level >= GFX7 && info->drm_minor >= 13; info->has_2d_tiling = true; info->has_read_registers_query = true; info->has_scheduled_fence_dependency = info->drm_minor >= 28; @@ -866,7 +866,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n"); info->clock_crystal_freq = 1; } - if (info->chip_class >= GFX10) { + if (info->gfx_level >= GFX10) { info->tcc_cache_line_size = 128; if (info->drm_minor >= 35) { @@ -922,7 +922,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->mc_arb_ramcfg = amdinfo->mc_arb_ramcfg; info->gb_addr_config = amdinfo->gb_addr_cfg; - if (info->chip_class >= GFX9) { + if (info->gfx_level >= GFX9) { info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg); info->pipe_interleave_bytes = 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg); } else { @@ -936,12 +936,12 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, * * LDS is 128KB in WGP mode and 64KB in CU mode. Assume the WGP mode is used. */ - info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024; + info->lds_size_per_workgroup = info->gfx_level >= GFX10 ? 128 * 1024 : 64 * 1024; /* lds_encode_granularity is the block size used for encoding registers. * lds_alloc_granularity is what the hardware will align the LDS size to. */ - info->lds_encode_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4; - info->lds_alloc_granularity = info->chip_class >= GFX10_3 ? 256 * 4 : info->lds_encode_granularity; + info->lds_encode_granularity = info->gfx_level >= GFX7 ? 128 * 4 : 64 * 4; + info->lds_alloc_granularity = info->gfx_level >= GFX10_3 ? 256 * 4 : info->lds_encode_granularity; /* This is "align_mask" copied from the kernel, maximums of all IP versions. */ info->ib_pad_dw_mask[AMD_IP_GFX] = 0xff; @@ -958,15 +958,15 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc. * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */ - info->has_clear_state = info->chip_class >= GFX7; + info->has_clear_state = info->gfx_level >= GFX7; info->has_distributed_tess = - info->chip_class >= GFX10 || (info->chip_class >= GFX8 && info->max_se >= 2); + info->gfx_level >= GFX10 || (info->gfx_level >= GFX8 && info->max_se >= 2); info->has_dcc_constant_encode = - info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->chip_class >= GFX10; + info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->gfx_level >= GFX10; - info->has_rbplus = info->family == CHIP_STONEY || info->chip_class >= GFX9; + info->has_rbplus = info->family == CHIP_STONEY || info->gfx_level >= GFX9; /* Some chips have RB+ registers, but don't support RB+. Those must * always disable it. @@ -974,13 +974,13 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->rbplus_allowed = info->has_rbplus && (info->family == CHIP_STONEY || info->family == CHIP_VEGA12 || info->family == CHIP_RAVEN || - info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->chip_class >= GFX10_3); + info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->gfx_level >= GFX10_3); info->has_out_of_order_rast = - info->chip_class >= GFX8 && info->chip_class <= GFX9 && info->max_se >= 2; + info->gfx_level >= GFX8 && info->gfx_level <= GFX9 && info->max_se >= 2; /* Whether chips support double rate packed math instructions. */ - info->has_packed_math_16bit = info->chip_class >= GFX9; + info->has_packed_math_16bit = info->gfx_level >= GFX9; /* Whether chips support dot product instructions. A subset of these support a smaller * instruction encoding which accumulates with the destination. @@ -991,13 +991,13 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */ info->has_load_ctx_reg_pkt = - info->chip_class >= GFX9 || (info->chip_class >= GFX8 && info->me_fw_feature >= 41); + info->gfx_level >= GFX9 || (info->gfx_level >= GFX8 && info->me_fw_feature >= 41); - info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8; + info->cpdma_prefetch_writes_memory = info->gfx_level <= GFX8; info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN; - info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 && info->chip_class <= GFX9; + info->has_tc_compat_zrange_bug = info->gfx_level >= GFX8 && info->gfx_level <= GFX9; info->has_msaa_sample_loc_bug = (info->family >= CHIP_POLARIS10 && info->family <= CHIP_POLARIS12) || @@ -1006,7 +1006,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN; /* Drawing from 0-sized index buffers causes hangs on gfx10. */ - info->has_zero_index_buffer_bug = info->chip_class == GFX10; + info->has_zero_index_buffer_bug = info->gfx_level == GFX10; /* Whether chips are affected by the image load/sample/gather hw bug when * DCC is enabled (ie. WRITE_COMPRESS_ENABLE should be 0). @@ -1018,10 +1018,10 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, /* DB has a bug when ITERATE_256 is set to 1 that can cause a hang. The * workaround is to set DECOMPRESS_ON_Z_PLANES to 2 for 4X MSAA D/S images. */ - info->has_two_planes_iterate256_bug = info->chip_class == GFX10; + info->has_two_planes_iterate256_bug = info->gfx_level == GFX10; /* GFX10+Sienna: NGG->legacy transitions require VGT_FLUSH. */ - info->has_vgt_flush_ngg_legacy_bug = info->chip_class == GFX10 || + info->has_vgt_flush_ngg_legacy_bug = info->gfx_level == GFX10 || info->family == CHIP_SIENNA_CICHLID; /* HW bug workaround when CS threadgroups > 256 threads and async compute @@ -1032,23 +1032,23 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, * * FIXME: RADV doesn't limit the number of threads for async compute. */ - info->has_cs_regalloc_hang_bug = info->chip_class == GFX6 || + info->has_cs_regalloc_hang_bug = info->gfx_level == GFX6 || info->family == CHIP_BONAIRE || info->family == CHIP_KABINI; /* Support for GFX10.3 was added with F32_ME_FEATURE_VERSION_31 but the * feature version wasn't bumped. */ - info->has_32bit_predication = (info->chip_class >= GFX10 && + info->has_32bit_predication = (info->gfx_level >= GFX10 && info->me_fw_feature >= 32) || - (info->chip_class == GFX9 && + (info->gfx_level == GFX9 && info->me_fw_feature >= 52); /* Get the number of good compute units. */ info->num_good_compute_units = 0; for (i = 0; i < info->max_se; i++) { for (j = 0; j < info->max_sa_per_se; j++) { - if (info->chip_class >= GFX11) { + if (info->gfx_level >= GFX11) { assert(info->max_sa_per_se <= 2); info->cu_mask[i][j] = amdinfo->cu_bitmap[i % 4][(i / 4) * 2 + j]; } else if (info->family == CHIP_ARCTURUS) { @@ -1073,7 +1073,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, } /* Derive the number of enabled SEs from the CU mask. */ - if (info->chip_class >= GFX10_3 && info->max_se > 1) { + if (info->gfx_level >= GFX10_3 && info->max_se > 1) { info->num_se = 0; for (unsigned se = 0; se < info->max_se; se++) { @@ -1092,7 +1092,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, /* On GFX10, only whole WGPs (in units of 2 CUs) can be disabled, * and max - min <= 2. */ - unsigned cu_group = info->chip_class >= GFX10 ? 2 : 1; + unsigned cu_group = info->gfx_level >= GFX10 ? 2 : 1; info->max_good_cu_per_sa = DIV_ROUND_UP(info->num_good_compute_units, (info->num_se * info->max_sa_per_se * cu_group)) * cu_group; @@ -1108,16 +1108,16 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->pte_fragment_size = alignment_info.size_local; info->gart_page_size = alignment_info.size_remote; - if (info->chip_class == GFX6) + if (info->gfx_level == GFX6) info->gfx_ib_pad_with_type2 = true; /* GFX10 and maybe GFX9 need this alignment for cache coherency. */ - if (info->chip_class >= GFX9) + if (info->gfx_level >= GFX9) info->ib_alignment = MAX2(info->ib_alignment, info->tcc_cache_line_size); if ((info->drm_minor >= 31 && (info->family == CHIP_RAVEN || info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR)) || - info->chip_class >= GFX10_3) { + info->gfx_level >= GFX10_3) { if (info->max_render_backends == 1) info->use_display_dcc_unaligned = true; else @@ -1126,10 +1126,10 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->has_stable_pstate = info->drm_minor >= 45; - if (info->chip_class >= GFX11) { + if (info->gfx_level >= GFX11) { info->pc_lines = 1024; info->pbb_max_alloc_count = 255; /* minimum is 2, maximum is 256 */ - } else if (info->chip_class >= GFX9 && info->has_graphics) { + } else if (info->gfx_level >= GFX9 && info->has_graphics) { unsigned pc_lines = 0; switch (info->family) { @@ -1163,27 +1163,27 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->pc_lines = pc_lines; - if (info->chip_class >= GFX10) { + if (info->gfx_level >= GFX10) { info->pbb_max_alloc_count = pc_lines / 3; } else { info->pbb_max_alloc_count = MIN2(128, pc_lines / (4 * info->max_se)); } } - if (info->chip_class >= GFX10_3) + if (info->gfx_level >= GFX10_3) info->max_wave64_per_simd = 16; - else if (info->chip_class == GFX10) + else if (info->gfx_level == GFX10) info->max_wave64_per_simd = 20; else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM) info->max_wave64_per_simd = 8; else info->max_wave64_per_simd = 10; - if (info->chip_class >= GFX10) { + if (info->gfx_level >= GFX10) { info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd; info->min_sgpr_alloc = 128; info->sgpr_alloc_granularity = 128; - } else if (info->chip_class >= GFX8) { + } else if (info->gfx_level >= GFX8) { info->num_physical_sgprs_per_simd = 800; info->min_sgpr_alloc = 16; info->sgpr_alloc_granularity = 16; @@ -1194,9 +1194,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, } info->has_3d_cube_border_color_mipmap = info->has_graphics || info->family == CHIP_ARCTURUS; - info->never_stop_sq_perf_counters = info->chip_class == GFX10 || - info->chip_class == GFX10_3; - info->never_send_perfcounter_stop = info->chip_class == GFX11; + info->never_stop_sq_perf_counters = info->gfx_level == GFX10 || + info->gfx_level == GFX10_3; + info->never_send_perfcounter_stop = info->gfx_level == GFX11; info->has_sqtt_rb_harvest_bug = (info->family == CHIP_DIMGREY_CAVEFISH || info->family == CHIP_BEIGE_GOBY || info->family == CHIP_YELLOW_CARP || @@ -1205,7 +1205,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->max_render_backends; /* On GFX10.3, the polarity of AUTO_FLUSH_MODE is inverted. */ - info->has_sqtt_auto_flush_mode_bug = info->chip_class == GFX10_3; + info->has_sqtt_auto_flush_mode_bug = info->gfx_level == GFX10_3; info->max_sgpr_alloc = info->family == CHIP_TONGA || info->family == CHIP_ICELAND ? 96 : 104; @@ -1219,8 +1219,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->wave64_vgpr_alloc_granularity = 4; } - info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256; - info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4; + info->num_physical_wave64_vgprs_per_simd = info->gfx_level >= GFX10 ? 512 : 256; + info->num_simd_per_compute_unit = info->gfx_level >= GFX10 ? 2 : 4; /* The maximum number of scratch waves. The number is only a function of the number of CUs. * It should be large enough to hold at least 1 threadgroup. Use the minimum per-SA CU count. @@ -1249,7 +1249,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, exit(1); } - ac_parse_ib(stdout, ib, size / 4, NULL, 0, "IB", info->chip_class, NULL, NULL); + ac_parse_ib(stdout, ib, size / 4, NULL, 0, "IB", info->gfx_level, NULL, NULL); free(ib); exit(0); } @@ -1298,7 +1298,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f) fprintf(f, " pci_id = 0x%x\n", info->pci_id); fprintf(f, " pci_rev_id = 0x%x\n", info->pci_rev_id); fprintf(f, " family = %i\n", info->family); - fprintf(f, " chip_class = %i\n", info->chip_class); + fprintf(f, " gfx_level = %i\n", info->gfx_level); fprintf(f, " family_id = %i\n", info->family_id); fprintf(f, " chip_external_rev = %i\n", info->chip_external_rev); fprintf(f, " clock_crystal_freq = %i KHz\n", info->clock_crystal_freq); @@ -1459,15 +1459,15 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f) fprintf(f, " pbb_max_alloc_count = %u\n", info->pbb_max_alloc_count); fprintf(f, "GB_ADDR_CONFIG: 0x%08x\n", info->gb_addr_config); - if (info->chip_class >= GFX10) { + if (info->gfx_level >= GFX10) { fprintf(f, " num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config)); fprintf(f, " pipe_interleave_size = %u\n", 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config)); fprintf(f, " max_compressed_frags = %u\n", 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config)); - if (info->chip_class >= GFX10_3) + if (info->gfx_level >= GFX10_3) fprintf(f, " num_pkrs = %u\n", 1 << G_0098F8_NUM_PKRS(info->gb_addr_config)); - } else if (info->chip_class == GFX9) { + } else if (info->gfx_level == GFX9) { fprintf(f, " num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config)); fprintf(f, " pipe_interleave_size = %u\n", 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config)); @@ -1505,9 +1505,9 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f) } } -int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family) +int ac_get_gs_table_depth(enum amd_gfx_level gfx_level, enum radeon_family family) { - if (chip_class >= GFX9) + if (gfx_level >= GFX9) return -1; switch (family) { @@ -1646,7 +1646,7 @@ void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config, assert(sh_per_se == 1 || sh_per_se == 2); assert(rb_per_pkr == 1 || rb_per_pkr == 2); - if (info->chip_class >= GFX7) { + if (info->gfx_level >= GFX7) { unsigned raster_config_1 = *cik_raster_config_1_p; if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || (!se_mask[2] && !se_mask[3]))) { raster_config_1 &= C_028354_SE_PAIR_MAP; @@ -1728,11 +1728,11 @@ unsigned ac_get_compute_resource_limits(struct radeon_info *info, unsigned waves { unsigned compute_resource_limits = S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0); - if (info->chip_class >= GFX7) { + if (info->gfx_level >= GFX7) { unsigned num_cu_per_se = info->num_good_compute_units / info->num_se; /* Gfx9 should set the limit to max instead of 0 to fix high priority compute. */ - if (info->chip_class == GFX9 && !max_waves_per_sh) { + if (info->gfx_level == GFX9 && !max_waves_per_sh) { max_waves_per_sh = info->max_good_cu_per_sa * info->num_simd_per_compute_unit * info->max_wave64_per_simd; } @@ -1760,7 +1760,7 @@ unsigned ac_get_compute_resource_limits(struct radeon_info *info, unsigned waves void ac_get_hs_info(struct radeon_info *info, struct ac_hs_info *hs) { - bool double_offchip_buffers = info->chip_class >= GFX7 && + bool double_offchip_buffers = info->gfx_level >= GFX7 && info->family != CHIP_CARRIZO && info->family != CHIP_STONEY; unsigned max_offchip_buffers_per_se; @@ -1783,9 +1783,9 @@ void ac_get_hs_info(struct radeon_info *info, * * Follow AMDVLK here. */ - if (info->chip_class >= GFX11) { + if (info->gfx_level >= GFX11) { max_offchip_buffers_per_se = 256; /* TODO: we could decrease this to reduce memory/cache usage */ - } else if (info->chip_class >= GFX10) { + } else if (info->gfx_level >= GFX10) { max_offchip_buffers_per_se = 128; } else if (info->family == CHIP_VEGA12 || info->family == CHIP_VEGA20) { /* Only certain chips can use the maximum value. */ @@ -1807,7 +1807,7 @@ void ac_get_hs_info(struct radeon_info *info, offchip_granularity = V_03093C_X_8K_DWORDS; } - switch (info->chip_class) { + switch (info->gfx_level) { case GFX6: max_offchip_buffers = MIN2(max_offchip_buffers, 126); break; @@ -1824,15 +1824,15 @@ void ac_get_hs_info(struct radeon_info *info, hs->max_offchip_buffers = max_offchip_buffers; - if (info->chip_class >= GFX11) { + if (info->gfx_level >= GFX11) { /* OFFCHIP_BUFFERING is per SE. */ hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers_per_se - 1) | S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity); - } else if (info->chip_class >= GFX10_3) { + } else if (info->gfx_level >= GFX10_3) { hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) | S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity); - } else if (info->chip_class >= GFX7) { - if (info->chip_class >= GFX8) + } else if (info->gfx_level >= GFX7) { + if (info->gfx_level >= GFX8) --max_offchip_buffers; hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX7(max_offchip_buffers) | S_03093C_OFFCHIP_GRANULARITY_GFX7(offchip_granularity); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 814e259bed1..1bd245b1acf 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -63,7 +63,7 @@ struct radeon_info { uint32_t pci_id; uint32_t pci_rev_id; enum radeon_family family; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; uint32_t family_id; uint32_t chip_external_rev; uint32_t clock_crystal_freq; @@ -253,7 +253,7 @@ void ac_compute_driver_uuid(char *uuid, size_t size); void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size); void ac_print_gpu_info(struct radeon_info *info, FILE *f); -int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family); +int ac_get_gs_table_depth(enum amd_gfx_level gfx_level, enum radeon_family family); void ac_get_raster_config(struct radeon_info *info, uint32_t *raster_config_p, uint32_t *raster_config_1_p, uint32_t *se_tile_repeat_p); void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config, diff --git a/src/amd/common/ac_nir.c b/src/amd/common/ac_nir.c index 9fd21d080c1..c2f2d66ba54 100644 --- a/src/amd/common/ac_nir.c +++ b/src/amd/common/ac_nir.c @@ -37,7 +37,7 @@ ac_nir_load_arg(nir_builder *b, const struct ac_shader_args *ac_args, struct ac_ bool ac_nir_lower_indirect_derefs(nir_shader *shader, - enum chip_class chip_class) + enum amd_gfx_level gfx_level) { bool progress = false; @@ -49,7 +49,7 @@ ac_nir_lower_indirect_derefs(nir_shader *shader, glsl_get_natural_size_align_bytes); /* LLVM doesn't support VGPR indexing on GFX9. */ - bool llvm_has_working_vgpr_indexing = chip_class != GFX9; + bool llvm_has_working_vgpr_indexing = gfx_level != GFX9; /* TODO: Indirect indexing of GS inputs is unimplemented. * diff --git a/src/amd/common/ac_nir.h b/src/amd/common/ac_nir.h index 91679d9501f..3ef13c79687 100644 --- a/src/amd/common/ac_nir.h +++ b/src/amd/common/ac_nir.h @@ -72,7 +72,7 @@ ac_nir_lower_hs_inputs_to_mem(nir_shader *shader, void ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, - enum chip_class chip_class, + enum amd_gfx_level gfx_level, bool tes_reads_tessfactors, uint64_t tes_inputs_read, uint64_t tes_patch_inputs_read, @@ -88,17 +88,17 @@ ac_nir_lower_tes_inputs_to_mem(nir_shader *shader, void ac_nir_lower_es_outputs_to_mem(nir_shader *shader, - enum chip_class chip_class, + enum amd_gfx_level gfx_level, unsigned num_reserved_es_outputs); void ac_nir_lower_gs_inputs_to_mem(nir_shader *shader, - enum chip_class chip_class, + enum amd_gfx_level gfx_level, unsigned num_reserved_es_outputs); bool ac_nir_lower_indirect_derefs(nir_shader *shader, - enum chip_class chip_class); + enum amd_gfx_level gfx_level); void ac_nir_lower_ngg_nogs(nir_shader *shader, diff --git a/src/amd/common/ac_nir_lower_esgs_io_to_mem.c b/src/amd/common/ac_nir_lower_esgs_io_to_mem.c index 5fff4dedd2b..1d5f9e9032b 100644 --- a/src/amd/common/ac_nir_lower_esgs_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_esgs_io_to_mem.c @@ -42,7 +42,7 @@ typedef struct { /* Which hardware generation we're dealing with */ - enum chip_class chip_class; + enum amd_gfx_level gfx_level; /* Number of ES outputs for which memory should be reserved. * When compacted, this should be the number of linked ES outputs. @@ -127,7 +127,7 @@ lower_es_output_store(nir_builder *b, b->cursor = nir_before_instr(instr); nir_ssa_def *io_off = nir_build_calc_io_offset(b, intrin, nir_imm_int(b, 16u), 4u); - if (st->chip_class <= GFX8) { + if (st->gfx_level <= GFX8) { /* GFX6-8: ES is a separate HW stage, data is passed from ES to GS in VRAM. */ nir_ssa_def *ring = nir_build_load_ring_esgs_amd(b); nir_ssa_def *es2gs_off = nir_build_load_ring_es2gs_offset_amd(b); @@ -193,11 +193,11 @@ gs_per_vertex_input_offset(nir_builder *b, nir_intrinsic_instr *instr) { nir_src *vertex_src = nir_get_io_arrayed_index_src(instr); - nir_ssa_def *vertex_offset = st->chip_class >= GFX9 + nir_ssa_def *vertex_offset = st->gfx_level >= GFX9 ? gs_per_vertex_input_vertex_offset_gfx9(b, vertex_src) : gs_per_vertex_input_vertex_offset_gfx6(b, vertex_src); - unsigned base_stride = st->chip_class >= GFX9 ? 1 : 64 /* Wave size on GFX6-8 */; + unsigned base_stride = st->gfx_level >= GFX9 ? 1 : 64 /* Wave size on GFX6-8 */; nir_ssa_def *io_off = nir_build_calc_io_offset(b, instr, nir_imm_int(b, base_stride * 4u), base_stride); nir_ssa_def *off = nir_iadd(b, io_off, vertex_offset); return nir_imul_imm(b, off, 4u); @@ -212,7 +212,7 @@ lower_gs_per_vertex_input_load(nir_builder *b, nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); nir_ssa_def *off = gs_per_vertex_input_offset(b, st, intrin); - if (st->chip_class >= GFX9) + if (st->gfx_level >= GFX9) return nir_build_load_shared(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size, off, .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); @@ -230,11 +230,11 @@ filter_load_per_vertex_input(const nir_instr *instr, UNUSED const void *state) void ac_nir_lower_es_outputs_to_mem(nir_shader *shader, - enum chip_class chip_class, + enum amd_gfx_level gfx_level, unsigned num_reserved_es_outputs) { lower_esgs_io_state state = { - .chip_class = chip_class, + .gfx_level = gfx_level, .num_reserved_es_outputs = num_reserved_es_outputs, }; @@ -246,11 +246,11 @@ ac_nir_lower_es_outputs_to_mem(nir_shader *shader, void ac_nir_lower_gs_inputs_to_mem(nir_shader *shader, - enum chip_class chip_class, + enum amd_gfx_level gfx_level, unsigned num_reserved_es_outputs) { lower_esgs_io_state state = { - .chip_class = chip_class, + .gfx_level = gfx_level, .num_reserved_es_outputs = num_reserved_es_outputs, }; diff --git a/src/amd/common/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/ac_nir_lower_tess_io_to_mem.c index e56e529bb10..2fe6b2cd957 100644 --- a/src/amd/common/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_tess_io_to_mem.c @@ -121,7 +121,7 @@ typedef struct { /* Which hardware generation we're dealing with */ - enum chip_class chip_class; + enum amd_gfx_level gfx_level; /* True if merged VS+TCS (on GFX9+) has the same number * of input and output patch size. @@ -545,7 +545,7 @@ hs_emit_write_tess_factors(nir_shader *shader, nir_ssa_def *tess_factors_offset = nir_imul_imm(b, rel_patch_id, (inner_comps + outer_comps) * 4u); unsigned tess_factors_const_offset = 0; - if (st->chip_class <= GFX8) { + if (st->gfx_level <= GFX8) { /* Store the dynamic HS control word. */ nir_if *rel_patch_id_zero = nir_push_if(b, nir_ieq_imm(b, rel_patch_id, 0)); nir_ssa_def *ctrlw = nir_imm_int(b, 0x80000000u); @@ -671,7 +671,7 @@ ac_nir_lower_hs_inputs_to_mem(nir_shader *shader, void ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, - enum chip_class chip_class, + enum amd_gfx_level gfx_level, bool tes_reads_tessfactors, uint64_t tes_inputs_read, uint64_t tes_patch_inputs_read, @@ -683,7 +683,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, assert(shader->info.stage == MESA_SHADER_TESS_CTRL); lower_tess_io_state state = { - .chip_class = chip_class, + .gfx_level = gfx_level, .tes_reads_tessfactors = tes_reads_tessfactors, .tes_inputs_read = tes_inputs_read, .tes_patch_inputs_read = tes_patch_inputs_read, diff --git a/src/amd/common/ac_perfcounter.c b/src/amd/common/ac_perfcounter.c index 139db14a4a8..bbb3b91cfec 100644 --- a/src/amd/common/ac_perfcounter.c +++ b/src/amd/common/ac_perfcounter.c @@ -1156,7 +1156,7 @@ bool ac_init_perfcounters(const struct radeon_info *info, const struct ac_pc_block_gfxdescr *blocks; unsigned num_blocks; - switch (info->chip_class) { + switch (info->gfx_level) { case GFX7: blocks = groups_CIK; num_blocks = ARRAY_SIZE(groups_CIK); diff --git a/src/amd/common/ac_rgp.c b/src/amd/common/ac_rgp.c index c6bfc85b879..1004ae48fc2 100644 --- a/src/amd/common/ac_rgp.c +++ b/src/amd/common/ac_rgp.c @@ -362,9 +362,9 @@ struct sqtt_file_chunk_asic_info { static_assert(sizeof(struct sqtt_file_chunk_asic_info) == 720, "sqtt_file_chunk_asic_info doesn't match RGP spec"); -static enum sqtt_gfxip_level ac_chip_class_to_sqtt_gfxip_level(enum chip_class chip_class) +static enum sqtt_gfxip_level ac_gfx_level_to_sqtt_gfxip_level(enum amd_gfx_level gfx_level) { - switch (chip_class) { + switch (gfx_level) { case GFX8: return SQTT_GFXIP_LEVEL_GFXIP_8; case GFX9: @@ -374,7 +374,7 @@ static enum sqtt_gfxip_level ac_chip_class_to_sqtt_gfxip_level(enum chip_class c case GFX10_3: return SQTT_GFXIP_LEVEL_GFXIP_10_3; default: - unreachable("Invalid chip class"); + unreachable("Invalid gfx level"); } } @@ -431,7 +431,7 @@ static uint32_t ac_memory_ops_per_clock(uint32_t vram_type) static void ac_sqtt_fill_asic_info(struct radeon_info *rad_info, struct sqtt_file_chunk_asic_info *chunk) { - bool has_wave32 = rad_info->chip_class >= GFX10; + bool has_wave32 = rad_info->gfx_level >= GFX10; chunk->header.chunk_id.type = SQTT_FILE_CHUNK_TYPE_ASIC_INFO; chunk->header.chunk_id.index = 0; @@ -444,11 +444,11 @@ static void ac_sqtt_fill_asic_info(struct radeon_info *rad_info, /* All chips older than GFX9 are affected by the "SPI not * differentiating pkr_id for newwave commands" bug. */ - if (rad_info->chip_class < GFX9) + if (rad_info->gfx_level < GFX9) chunk->flags |= SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING; /* Only GFX9+ support PS1 events. */ - if (rad_info->chip_class >= GFX9) + if (rad_info->gfx_level >= GFX9) chunk->flags |= SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED; chunk->trace_shader_core_clock = rad_info->max_shader_clock * 1000000; @@ -478,7 +478,7 @@ static void ac_sqtt_fill_asic_info(struct radeon_info *rad_info, chunk->hardware_contexts = 8; chunk->gpu_type = rad_info->has_dedicated_vram ? SQTT_GPU_TYPE_DISCRETE : SQTT_GPU_TYPE_INTEGRATED; - chunk->gfxip_level = ac_chip_class_to_sqtt_gfxip_level(rad_info->chip_class); + chunk->gfxip_level = ac_gfx_level_to_sqtt_gfxip_level(rad_info->gfx_level); chunk->gpu_index = 0; chunk->max_number_of_dedicated_cus = 0; @@ -491,7 +491,7 @@ static void ac_sqtt_fill_asic_info(struct radeon_info *rad_info, chunk->l2_cache_size = rad_info->l2_cache_size; chunk->l1_cache_size = rad_info->l1_cache_size; chunk->lds_size = rad_info->lds_size_per_workgroup; - if (rad_info->chip_class >= GFX10) { + if (rad_info->gfx_level >= GFX10) { /* RGP expects the LDS size in CU mode. */ chunk->lds_size /= 2; } @@ -501,7 +501,7 @@ static void ac_sqtt_fill_asic_info(struct radeon_info *rad_info, chunk->alu_per_clock = 0.0; chunk->texture_per_clock = 0.0; chunk->prims_per_clock = rad_info->max_se; - if (rad_info->chip_class == GFX10) + if (rad_info->gfx_level == GFX10) chunk->prims_per_clock *= 2; chunk->pixels_per_clock = 0.0; @@ -722,9 +722,9 @@ struct sqtt_file_chunk_sqtt_desc { static_assert(sizeof(struct sqtt_file_chunk_sqtt_desc) == 32, "sqtt_file_chunk_sqtt_desc doesn't match RGP spec"); -static enum sqtt_version ac_chip_class_to_sqtt_version(enum chip_class chip_class) +static enum sqtt_version ac_gfx_level_to_sqtt_version(enum amd_gfx_level gfx_level) { - switch (chip_class) { + switch (gfx_level) { case GFX8: return SQTT_VERSION_2_2; case GFX9: @@ -734,7 +734,7 @@ static enum sqtt_version ac_chip_class_to_sqtt_version(enum chip_class chip_clas case GFX10_3: return SQTT_VERSION_2_4; default: - unreachable("Invalid chip class"); + unreachable("Invalid gfx level"); } } @@ -749,7 +749,7 @@ static void ac_sqtt_fill_sqtt_desc(struct radeon_info *info, chunk->header.size_in_bytes = sizeof(*chunk); chunk->sqtt_version = - ac_chip_class_to_sqtt_version(info->chip_class); + ac_gfx_level_to_sqtt_version(info->gfx_level); chunk->shader_engine_index = shader_engine_index; chunk->v1.instrumentation_spec_version = 1; chunk->v1.instrumentation_api_version = 0; @@ -877,9 +877,9 @@ enum elf_gfxip_level EF_AMDGPU_MACH_AMDGCN_GFX1030 = 0x036, }; -static enum elf_gfxip_level ac_chip_class_to_elf_gfxip_level(enum chip_class chip_class) +static enum elf_gfxip_level ac_gfx_level_to_elf_gfxip_level(enum amd_gfx_level gfx_level) { - switch (chip_class) { + switch (gfx_level) { case GFX8: return EF_AMDGPU_MACH_AMDGCN_GFX801; case GFX9: @@ -889,7 +889,7 @@ static enum elf_gfxip_level ac_chip_class_to_elf_gfxip_level(enum chip_class chi case GFX10_3: return EF_AMDGPU_MACH_AMDGCN_GFX1030; default: - unreachable("Invalid chip class"); + unreachable("Invalid gfx level"); } } @@ -1049,7 +1049,7 @@ static void ac_sqtt_dump_data(struct radeon_info *rad_info, struct sqtt_file_chunk_code_object_database code_object; struct sqtt_code_object_database_record code_object_record; uint32_t elf_size_calc = 0; - uint32_t flags = ac_chip_class_to_elf_gfxip_level(rad_info->chip_class); + uint32_t flags = ac_gfx_level_to_elf_gfxip_level(rad_info->gfx_level); fseek(output, sizeof(struct sqtt_file_chunk_code_object_database), SEEK_CUR); file_offset += sizeof(struct sqtt_file_chunk_code_object_database); diff --git a/src/amd/common/ac_rtld.c b/src/amd/common/ac_rtld.c index 282df71dc0d..c4ae62dc710 100644 --- a/src/amd/common/ac_rtld.c +++ b/src/amd/common/ac_rtld.c @@ -257,7 +257,7 @@ bool ac_rtld_open(struct ac_rtld_binary *binary, struct ac_rtld_open_info i) memset(binary, 0, sizeof(*binary)); memcpy(&binary->options, &i.options, sizeof(binary->options)); binary->wave_size = i.wave_size; - binary->chip_class = i.info->chip_class; + binary->gfx_level = i.info->gfx_level; binary->num_parts = i.num_parts; binary->parts = calloc(sizeof(*binary->parts), i.num_parts); if (!binary->parts) @@ -297,7 +297,7 @@ bool ac_rtld_open(struct ac_rtld_binary *binary, struct ac_rtld_open_info i) unsigned max_lds_size = 64 * 1024; - if (i.info->chip_class == GFX6 || + if (i.info->gfx_level == GFX6 || (i.shader_type != MESA_SHADER_COMPUTE && i.shader_type != MESA_SHADER_FRAGMENT)) max_lds_size = 32 * 1024; @@ -456,11 +456,11 @@ bool ac_rtld_open(struct ac_rtld_binary *binary, struct ac_rtld_open_info i) if (!i.info->has_graphics && i.info->family >= CHIP_ALDEBARAN) prefetch_distance = 16; - else if (i.info->chip_class >= GFX10) + else if (i.info->gfx_level >= GFX10) prefetch_distance = 3; if (prefetch_distance) { - if (i.info->chip_class >= GFX11) + if (i.info->gfx_level >= GFX11) binary->rx_size = align(binary->rx_size + prefetch_distance * 64, 128); else binary->rx_size = align(binary->rx_size + prefetch_distance * 64, 64); @@ -577,7 +577,7 @@ static bool resolve_symbol(const struct ac_rtld_upload_info *u, unsigned part_id /* TODO: resolve from other parts */ - if (u->get_external_symbol(u->binary->chip_class, u->cb_data, name, value)) + if (u->get_external_symbol(u->binary->gfx_level, u->cb_data, name, value)) return true; report_errorf("symbol %s: unknown", name); diff --git a/src/amd/common/ac_rtld.h b/src/amd/common/ac_rtld.h index c6e5bf254e7..70ef1f452ce 100644 --- a/src/amd/common/ac_rtld.h +++ b/src/amd/common/ac_rtld.h @@ -57,7 +57,7 @@ struct ac_rtld_options { /* Lightweight wrapper around underlying ELF objects. */ struct ac_rtld_binary { struct ac_rtld_options options; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; unsigned wave_size; /* Required buffer sizes, currently read/executable only. */ @@ -84,7 +84,7 @@ struct ac_rtld_binary { * \param value to be filled in by the callback * \return whether the symbol was found successfully */ -typedef bool (*ac_rtld_get_external_symbol_cb)(enum chip_class chip_class, void *cb_data, +typedef bool (*ac_rtld_get_external_symbol_cb)(enum amd_gfx_level gfx_level, void *cb_data, const char *symbol, uint64_t *value); /** diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c index 89a745f8e18..2cb2bedb03a 100644 --- a/src/amd/common/ac_shader_util.c +++ b/src/amd/common/ac_shader_util.c @@ -85,11 +85,11 @@ unsigned ac_get_cb_shader_mask(unsigned spi_shader_col_format) * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a * geometry shader. */ -uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class) +uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum amd_gfx_level gfx_level) { unsigned cut_mode; - assert (chip_class < GFX11); + assert (gfx_level < GFX11); if (gs_max_vert_out <= 128) { cut_mode = V_028A40_GS_CUT_128; @@ -103,20 +103,20 @@ uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class) } return S_028A40_MODE(V_028A40_GS_SCENARIO_G) | S_028A40_CUT_MODE(cut_mode) | - S_028A40_ES_WRITE_OPTIMIZE(chip_class <= GFX8) | S_028A40_GS_WRITE_OPTIMIZE(1) | - S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0); + S_028A40_ES_WRITE_OPTIMIZE(gfx_level <= GFX8) | S_028A40_GS_WRITE_OPTIMIZE(1) | + S_028A40_ONCHIP(gfx_level >= GFX9 ? 1 : 0); } /// Translate a (dfmt, nfmt) pair into a chip-appropriate combined format /// value for LLVM8+ tbuffer intrinsics. -unsigned ac_get_tbuffer_format(enum chip_class chip_class, unsigned dfmt, unsigned nfmt) +unsigned ac_get_tbuffer_format(enum amd_gfx_level gfx_level, unsigned dfmt, unsigned nfmt) { // Some games try to access vertex buffers without a valid format. // This is a game bug, but we should still handle it gracefully. if (dfmt == V_008F0C_GFX10_FORMAT_INVALID) return V_008F0C_GFX10_FORMAT_INVALID; - if (chip_class >= GFX11) { + if (gfx_level >= GFX11) { switch (dfmt) { default: unreachable("bad dfmt"); @@ -311,7 +311,7 @@ unsigned ac_get_tbuffer_format(enum chip_class chip_class, unsigned dfmt, unsign return V_008F0C_GFX11_FORMAT_10_11_11_FLOAT; } } - } else if (chip_class >= GFX10) { + } else if (gfx_level >= GFX10) { unsigned format; switch (dfmt) { default: @@ -417,12 +417,12 @@ const struct ac_data_format_info *ac_get_data_format_info(unsigned dfmt) return &data_format_table[dfmt]; } -enum ac_image_dim ac_get_sampler_dim(enum chip_class chip_class, enum glsl_sampler_dim dim, +enum ac_image_dim ac_get_sampler_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim dim, bool is_array) { switch (dim) { case GLSL_SAMPLER_DIM_1D: - if (chip_class == GFX9) + if (gfx_level == GFX9) return is_array ? ac_image_2darray : ac_image_2d; return is_array ? ac_image_1darray : ac_image_1d; case GLSL_SAMPLER_DIM_2D: @@ -444,15 +444,15 @@ enum ac_image_dim ac_get_sampler_dim(enum chip_class chip_class, enum glsl_sampl } } -enum ac_image_dim ac_get_image_dim(enum chip_class chip_class, enum glsl_sampler_dim sdim, +enum ac_image_dim ac_get_image_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim sdim, bool is_array) { - enum ac_image_dim dim = ac_get_sampler_dim(chip_class, sdim, is_array); + enum ac_image_dim dim = ac_get_sampler_dim(gfx_level, sdim, is_array); /* Match the resource type set in the descriptor. */ - if (dim == ac_image_cube || (chip_class <= GFX8 && dim == ac_image_3d)) + if (dim == ac_image_cube || (gfx_level <= GFX8 && dim == ac_image_3d)) dim = ac_image_2darray; - else if (sdim == GLSL_SAMPLER_DIM_2D && !is_array && chip_class == GFX9) { + else if (sdim == GLSL_SAMPLER_DIM_2D && !is_array && gfx_level == GFX9) { /* When a single layer of a 3D texture is bound, the shader * will refer to a 2D target, but the descriptor has a 3D type. * Since the HW ignores BASE_ARRAY in this case, we need to @@ -670,7 +670,7 @@ void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_cu if (ngg && info->family == CHIP_NAVI14) return; - if (info->chip_class >= GFX10) { + if (info->gfx_level >= GFX10) { /* For Wave32, the hw will launch twice the number of late alloc waves, so 1 == 2x wave32. * These limits are estimated because they are all safe but they vary in performance. */ @@ -680,7 +680,7 @@ void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_cu *late_alloc_wave64 = info->min_good_cu_per_sa * 4; /* Limit LATE_ALLOC_GS to prevent a hang (hw bug) on gfx10. */ - if (info->chip_class == GFX10 && ngg) + if (info->gfx_level == GFX10 && ngg) *late_alloc_wave64 = MIN2(*late_alloc_wave64, 64); /* Gfx10: CU2 & CU3 must be disabled to prevent a hw deadlock. @@ -688,7 +688,7 @@ void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_cu * * The deadlock is caused by late alloc, which usually increases performance. */ - *cu_mask &= info->chip_class == GFX10 ? ~BITFIELD_RANGE(2, 2) : + *cu_mask &= info->gfx_level == GFX10 ? ~BITFIELD_RANGE(2, 2) : ~BITFIELD_RANGE(1, 1); } else { if (info->min_good_cu_per_sa <= 4) { @@ -724,7 +724,7 @@ unsigned ac_compute_cs_workgroup_size(uint16_t sizes[3], bool variable, unsigned return sizes[0] * sizes[1] * sizes[2]; } -unsigned ac_compute_lshs_workgroup_size(enum chip_class chip_class, gl_shader_stage stage, +unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage, unsigned tess_num_patches, unsigned tess_patch_in_vtx, unsigned tess_patch_out_vtx) @@ -733,7 +733,7 @@ unsigned ac_compute_lshs_workgroup_size(enum chip_class chip_class, gl_shader_st * These two HW stages are merged on GFX9+. */ - bool merged_shaders = chip_class >= GFX9; + bool merged_shaders = gfx_level >= GFX9; unsigned ls_workgroup_size = tess_num_patches * tess_patch_in_vtx; unsigned hs_workgroup_size = tess_num_patches * tess_patch_out_vtx; @@ -747,7 +747,7 @@ unsigned ac_compute_lshs_workgroup_size(enum chip_class chip_class, gl_shader_st unreachable("invalid LSHS shader stage"); } -unsigned ac_compute_esgs_workgroup_size(enum chip_class chip_class, unsigned wave_size, +unsigned ac_compute_esgs_workgroup_size(enum amd_gfx_level gfx_level, unsigned wave_size, unsigned es_verts, unsigned gs_inst_prims) { /* ESGS may operate in workgroups if on-chip GS (LDS rings) are enabled. @@ -757,7 +757,7 @@ unsigned ac_compute_esgs_workgroup_size(enum chip_class chip_class, unsigned wav * GFX9+ (merged): implemented in Mesa. */ - if (chip_class <= GFX8) + if (gfx_level <= GFX8) return wave_size; unsigned workgroup_size = MAX2(es_verts, gs_inst_prims); @@ -821,7 +821,7 @@ void ac_get_scratch_tmpring_size(const struct radeon_info *info, bool compute, * * Shaders with SCRATCH_EN=0 don't allocate scratch space. */ - const unsigned size_shift = info->chip_class >= GFX11 ? 8 : 10; + const unsigned size_shift = info->gfx_level >= GFX11 ? 8 : 10; const unsigned min_size_per_wave = BITFIELD_BIT(size_shift); /* The LLVM shader backend should be reporting aligned scratch_sizes. */ @@ -837,7 +837,7 @@ void ac_get_scratch_tmpring_size(const struct radeon_info *info, bool compute, *max_seen_bytes_per_wave = MAX2(*max_seen_bytes_per_wave, bytes_per_wave); unsigned max_scratch_waves = info->max_scratch_waves; - if (info->chip_class >= GFX11 && !compute) + if (info->gfx_level >= GFX11 && !compute) max_scratch_waves /= info->num_se; /* WAVES is per SE for SPI_TMPRING_SIZE. */ /* TODO: We could decrease WAVES to make the whole buffer fit into the infinity cache. */ diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h index f1d8f3ca958..37252fe1f8e 100644 --- a/src/amd/common/ac_shader_util.h +++ b/src/amd/common/ac_shader_util.h @@ -94,16 +94,16 @@ unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool wri unsigned ac_get_cb_shader_mask(unsigned spi_shader_col_format); -uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class); +uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum amd_gfx_level gfx_level); -unsigned ac_get_tbuffer_format(enum chip_class chip_class, unsigned dfmt, unsigned nfmt); +unsigned ac_get_tbuffer_format(enum amd_gfx_level gfx_level, unsigned dfmt, unsigned nfmt); const struct ac_data_format_info *ac_get_data_format_info(unsigned dfmt); -enum ac_image_dim ac_get_sampler_dim(enum chip_class chip_class, enum glsl_sampler_dim dim, +enum ac_image_dim ac_get_sampler_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim dim, bool is_array); -enum ac_image_dim ac_get_image_dim(enum chip_class chip_class, enum glsl_sampler_dim sdim, +enum ac_image_dim ac_get_image_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim sdim, bool is_array); unsigned ac_get_fs_input_vgpr_cnt(const struct ac_shader_config *config, @@ -119,12 +119,12 @@ void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_cu unsigned ac_compute_cs_workgroup_size(uint16_t sizes[3], bool variable, unsigned max); -unsigned ac_compute_lshs_workgroup_size(enum chip_class chip_class, gl_shader_stage stage, +unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage, unsigned tess_num_patches, unsigned tess_patch_in_vtx, unsigned tess_patch_out_vtx); -unsigned ac_compute_esgs_workgroup_size(enum chip_class chip_class, unsigned wave_size, +unsigned ac_compute_esgs_workgroup_size(enum amd_gfx_level gfx_level, unsigned wave_size, unsigned es_verts, unsigned gs_inst_prims); unsigned ac_compute_ngg_workgroup_size(unsigned es_verts, unsigned gs_inst_prims, diff --git a/src/amd/common/ac_shadowed_regs.c b/src/amd/common/ac_shadowed_regs.c index 240daff5676..65a49bd9cc2 100644 --- a/src/amd/common/ac_shadowed_regs.c +++ b/src/amd/common/ac_shadowed_regs.c @@ -1240,7 +1240,7 @@ static const struct ac_reg_range Gfx11NonShadowedRanges[] = }, }; -void ac_get_reg_ranges(enum chip_class chip_class, enum radeon_family family, +void ac_get_reg_ranges(enum amd_gfx_level gfx_level, enum radeon_family family, enum ac_reg_range_type type, unsigned *num_ranges, const struct ac_reg_range **ranges) { @@ -1255,51 +1255,51 @@ void ac_get_reg_ranges(enum chip_class chip_class, enum radeon_family family, switch (type) { case SI_REG_RANGE_UCONFIG: - if (chip_class == GFX11) + if (gfx_level == GFX11) RETURN(Gfx11UserConfigShadowRange); - else if (chip_class == GFX10_3) + else if (gfx_level == GFX10_3) RETURN(Gfx103UserConfigShadowRange); - else if (chip_class == GFX10) + else if (gfx_level == GFX10) RETURN(Nv10UserConfigShadowRange); - else if (chip_class == GFX9) + else if (gfx_level == GFX9) RETURN(Gfx9UserConfigShadowRange); break; case SI_REG_RANGE_CONTEXT: - if (chip_class == GFX11) + if (gfx_level == GFX11) RETURN(Gfx11ContextShadowRange); - else if (chip_class == GFX10_3) + else if (gfx_level == GFX10_3) RETURN(Gfx103ContextShadowRange); - else if (chip_class == GFX10) + else if (gfx_level == GFX10) RETURN(Nv10ContextShadowRange); - else if (chip_class == GFX9) + else if (gfx_level == GFX9) RETURN(Gfx9ContextShadowRange); break; case SI_REG_RANGE_SH: - if (chip_class == GFX11) + if (gfx_level == GFX11) RETURN(Gfx11ShShadowRange); - else if (chip_class == GFX10_3 || chip_class == GFX10) + else if (gfx_level == GFX10_3 || gfx_level == GFX10) RETURN(Gfx10ShShadowRange); else if (family == CHIP_RAVEN2 || family == CHIP_RENOIR) RETURN(Gfx9ShShadowRangeRaven2); - else if (chip_class == GFX9) + else if (gfx_level == GFX9) RETURN(Gfx9ShShadowRange); break; case SI_REG_RANGE_CS_SH: - if (chip_class == GFX11) + if (gfx_level == GFX11) RETURN(Gfx11CsShShadowRange); - else if (chip_class == GFX10_3 || chip_class == GFX10) + else if (gfx_level == GFX10_3 || gfx_level == GFX10) RETURN(Gfx10CsShShadowRange); else if (family == CHIP_RAVEN2 || family == CHIP_RENOIR) RETURN(Gfx9CsShShadowRangeRaven2); - else if (chip_class == GFX9) + else if (gfx_level == GFX9) RETURN(Gfx9CsShShadowRange); break; case SI_REG_RANGE_NON_SHADOWED: - if (chip_class == GFX11) + if (gfx_level == GFX11) RETURN(Gfx11NonShadowedRanges); - else if (chip_class == GFX10_3) + else if (gfx_level == GFX10_3) RETURN(Gfx103NonShadowedRanges); - else if (chip_class == GFX10) + else if (gfx_level == GFX10) RETURN(Navi10NonShadowedRanges); else assert(0); @@ -4031,13 +4031,13 @@ void ac_emulate_clear_state(const struct radeon_info *info, struct radeon_cmdbuf unsigned reg_offset = R_02835C_PA_SC_TILE_STEERING_OVERRIDE; uint32_t reg_value = info->pa_sc_tile_steering_override; - if (info->chip_class >= GFX11) { + if (info->gfx_level >= GFX11) { gfx11_emulate_clear_state(cs, 1, ®_offset, ®_value, set_context_reg_seq_array); - } else if (info->chip_class == GFX10_3) { + } else if (info->gfx_level == GFX10_3) { gfx103_emulate_clear_state(cs, 1, ®_offset, ®_value, set_context_reg_seq_array); - } else if (info->chip_class == GFX10) { + } else if (info->gfx_level == GFX10) { gfx10_emulate_clear_state(cs, 1, ®_offset, ®_value, set_context_reg_seq_array); - } else if (info->chip_class == GFX9) { + } else if (info->gfx_level == GFX9) { gfx9_emulate_clear_state(cs, set_context_reg_seq_array); } else { unreachable("unimplemented"); @@ -4047,7 +4047,7 @@ void ac_emulate_clear_state(const struct radeon_info *info, struct radeon_cmdbuf /* Debug helper to find if any registers are missing in the tables above. * Call this in the driver whenever you set a register. */ -void ac_check_shadowed_regs(enum chip_class chip_class, enum radeon_family family, +void ac_check_shadowed_regs(enum amd_gfx_level gfx_level, enum radeon_family family, unsigned reg_offset, unsigned count) { bool found = false; @@ -4057,7 +4057,7 @@ void ac_check_shadowed_regs(enum chip_class chip_class, enum radeon_family famil const struct ac_reg_range *ranges; unsigned num_ranges; - ac_get_reg_ranges(chip_class, family, type, &num_ranges, &ranges); + ac_get_reg_ranges(gfx_level, family, type, &num_ranges, &ranges); for (unsigned i = 0; i < num_ranges; i++) { unsigned end_reg_offset = reg_offset + count * 4; @@ -4080,10 +4080,10 @@ void ac_check_shadowed_regs(enum chip_class chip_class, enum radeon_family famil if (!found || !shadowed) { printf("register %s: ", !found ? "not found" : "not shadowed"); if (count > 1) { - printf("%s .. %s\n", ac_get_register_name(chip_class, reg_offset), - ac_get_register_name(chip_class, reg_offset + (count - 1) * 4)); + printf("%s .. %s\n", ac_get_register_name(gfx_level, reg_offset), + ac_get_register_name(gfx_level, reg_offset + (count - 1) * 4)); } else { - printf("%s\n", ac_get_register_name(chip_class, reg_offset)); + printf("%s\n", ac_get_register_name(gfx_level, reg_offset)); } } } @@ -4102,13 +4102,13 @@ void ac_print_shadowed_regs(const struct radeon_info *info) const struct ac_reg_range *ranges; unsigned num_ranges; - ac_get_reg_ranges(info->chip_class, info->family, type, &num_ranges, &ranges); + ac_get_reg_ranges(info->gfx_level, info->family, type, &num_ranges, &ranges); for (unsigned i = 0; i < num_ranges; i++) { for (unsigned j = 0; j < ranges[i].size / 4; j++) { unsigned offset = ranges[i].offset + j * 4; - const char *name = ac_get_register_name(info->chip_class, offset); + const char *name = ac_get_register_name(info->gfx_level, offset); unsigned value = -1; #ifndef _WIN32 diff --git a/src/amd/common/ac_shadowed_regs.h b/src/amd/common/ac_shadowed_regs.h index 8a183927177..8d2114452af 100644 --- a/src/amd/common/ac_shadowed_regs.h +++ b/src/amd/common/ac_shadowed_regs.h @@ -54,12 +54,12 @@ extern "C" { typedef void (*set_context_reg_seq_array_fn)(struct radeon_cmdbuf *cs, unsigned reg, unsigned num, const uint32_t *values); -void ac_get_reg_ranges(enum chip_class chip_class, enum radeon_family family, +void ac_get_reg_ranges(enum amd_gfx_level gfx_level, enum radeon_family family, enum ac_reg_range_type type, unsigned *num_ranges, const struct ac_reg_range **ranges); void ac_emulate_clear_state(const struct radeon_info *info, struct radeon_cmdbuf *cs, set_context_reg_seq_array_fn set_context_reg_seq_array); -void ac_check_shadowed_regs(enum chip_class chip_class, enum radeon_family family, +void ac_check_shadowed_regs(enum amd_gfx_level gfx_level, enum radeon_family family, unsigned reg_offset, unsigned count); void ac_print_shadowed_regs(const struct radeon_info *info); diff --git a/src/amd/common/ac_sqtt.c b/src/amd/common/ac_sqtt.c index c52b32b3e24..d3f31888834 100644 --- a/src/amd/common/ac_sqtt.c +++ b/src/amd/common/ac_sqtt.c @@ -67,7 +67,7 @@ ac_is_thread_trace_complete(struct radeon_info *rad_info, const struct ac_thread_trace_data *data, const struct ac_thread_trace_info *info) { - if (rad_info->chip_class >= GFX10) { + if (rad_info->gfx_level >= GFX10) { /* GFX10 doesn't have THREAD_TRACE_CNTR but it reports the number of * dropped bytes per SE via THREAD_TRACE_DROPPED_CNTR. Though, this * doesn't seem reliable because it might still report non-zero even if @@ -90,7 +90,7 @@ uint32_t ac_get_expected_buffer_size(struct radeon_info *rad_info, const struct ac_thread_trace_info *info) { - if (rad_info->chip_class >= GFX10) { + if (rad_info->gfx_level >= GFX10) { uint32_t dropped_cntr_per_se = info->gfx10_dropped_cntr / rad_info->max_se; return ((info->cur_offset * 32) + dropped_cntr_per_se) / 1024; } diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 8e8ca14a794..f88bb16f832 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -122,11 +122,11 @@ bool ac_modifier_supports_dcc_image_stores(uint64_t modifier) } -bool ac_surface_supports_dcc_image_stores(enum chip_class chip_class, +bool ac_surface_supports_dcc_image_stores(enum amd_gfx_level gfx_level, const struct radeon_surf *surf) { /* DCC image stores is only available for GFX10+. */ - if (chip_class < GFX10) + if (gfx_level < GFX10) return false; /* DCC image stores support the following settings: @@ -151,7 +151,7 @@ bool ac_surface_supports_dcc_image_stores(enum chip_class chip_class, return (!surf->u.gfx9.color.dcc.independent_64B_blocks && surf->u.gfx9.color.dcc.independent_128B_blocks && surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B) || - (chip_class >= GFX10_3 && /* gfx10.3 */ + (gfx_level >= GFX10_3 && /* gfx10.3 */ surf->u.gfx9.color.dcc.independent_64B_blocks && surf->u.gfx9.color.dcc.independent_128B_blocks && surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B); @@ -199,18 +199,18 @@ bool ac_is_modifier_supported(const struct radeon_info *info, util_format_get_blocksizebits(format) > 64) return false; - if (info->chip_class < GFX9) + if (info->gfx_level < GFX9) return false; if(modifier == DRM_FORMAT_MOD_LINEAR) return true; /* GFX8 may need a different modifier for each plane */ - if (info->chip_class < GFX9 && util_format_get_num_planes(format) > 1) + if (info->gfx_level < GFX9 && util_format_get_num_planes(format) > 1) return false; uint32_t allowed_swizzles = 0xFFFFFFFF; - switch(info->chip_class) { + switch(info->gfx_level) { case GFX9: allowed_swizzles = ac_modifier_has_dcc(modifier) ? 0x06000000 : 0x06660660; break; @@ -264,7 +264,7 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, /* The modifiers have to be added in descending order of estimated * performance. The drivers will prefer modifiers that come earlier * in the list. */ - switch (info->chip_class) { + switch (info->gfx_level) { case GFX9: { unsigned pipe_xor_bits = MIN2(G_0098F8_NUM_PIPES(info->gb_addr_config) + G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config), 8); @@ -340,7 +340,7 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, } case GFX10: case GFX10_3: { - bool rbplus = info->chip_class >= GFX10_3; + bool rbplus = info->gfx_level >= GFX10_3; unsigned pipe_xor_bits = G_0098F8_NUM_PIPES(info->gb_addr_config); unsigned pkrs = rbplus ? G_0098F8_NUM_PKRS(info->gb_addr_config) : 0; @@ -357,7 +357,7 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)) - if (info->chip_class >= GFX10_3) { + if (info->gfx_level >= GFX10_3) { if (info->max_render_backends == 1) { ADD_MOD(AMD_FMT_MOD | common_dcc | AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | @@ -370,8 +370,8 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)) } - if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14 || info->chip_class >= GFX10_3) { - bool independent_128b = info->chip_class >= GFX10_3; + if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14 || info->gfx_level >= GFX10_3) { + bool independent_128b = info->gfx_level >= GFX10_3; if (info->max_render_backends == 1) { ADD_MOD(AMD_FMT_MOD | common_dcc | @@ -855,7 +855,7 @@ static void gfx6_set_micro_tile_mode(struct radeon_surf *surf, const struct rade { uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]]; - if (info->chip_class >= GFX7) + if (info->gfx_level >= GFX7) surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode); else surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode); @@ -934,7 +934,7 @@ static int gfx6_surface_settings(ADDR_HANDLE addrlib, const struct radeon_info * /* Compute tile swizzle. */ /* TODO: fix tile swizzle with mipmapping for GFX6 */ - if ((info->chip_class >= GFX7 || config->info.levels == 1) && config->info.surf_index && + if ((info->gfx_level >= GFX7 || config->info.levels == 1) && config->info.surf_index && surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D && !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) && !get_display_flag(config, surf)) { @@ -972,7 +972,7 @@ static void ac_compute_cmask(const struct radeon_info *info, const struct ac_sur (config->info.samples >= 2 && !surf->fmask_size)) return; - assert(info->chip_class <= GFX8); + assert(info->gfx_level <= GFX8); switch (num_pipes) { case 2: @@ -1138,7 +1138,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i * driver team). */ AddrSurfInfoIn.flags.dccCompatible = - info->chip_class >= GFX8 && info->has_graphics && /* disable DCC on compute-only chips */ + info->gfx_level >= GFX8 && info->has_graphics && /* disable DCC on compute-only chips */ !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed && ((config->info.array_size == 1 && config->info.depth == 1) || config->info.levels == 1); @@ -1203,7 +1203,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1); - if (info->chip_class == GFX6) { + if (info->gfx_level == GFX6) { if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) { if (surf->bpe == 2) AddrSurfInfoIn.tileIndex = 11; /* 16bpp */ @@ -1443,7 +1443,7 @@ static int gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, const struct rad /* TODO: We could allow some of these: */ sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */ - if (info->chip_class >= GFX11) { + if (info->gfx_level >= GFX11) { if ((1 << G_0098F8_NUM_PIPES(info->gb_addr_config)) <= 16) { sin.forbiddenBlock.gfx11.thin256KB = 1; sin.forbiddenBlock.gfx11.thick256KB = 1; @@ -1472,7 +1472,7 @@ static int gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, const struct rad if (sin.flags.prt) { sin.forbiddenBlock.macroThin4KB = 1; sin.forbiddenBlock.macroThick4KB = 1; - if (info->chip_class >= GFX11) { + if (info->gfx_level >= GFX11) { sin.forbiddenBlock.gfx11.thin256KB = 1; sin.forbiddenBlock.gfx11.thick256KB = 1; } @@ -1492,7 +1492,7 @@ static int gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, const struct rad sin.preferredSwSet.sw_R = 1; } - if (info->chip_class >= GFX10 && in->resourceType == ADDR_RSRC_TEX_3D && in->numSlices > 1) { + if (info->gfx_level >= GFX10 && in->resourceType == ADDR_RSRC_TEX_3D && in->numSlices > 1) { /* 3D textures should use S swizzle modes for the best performance. * THe only exception is 3D render targets, which prefer 64KB_D_X. * @@ -1519,11 +1519,11 @@ static int gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, const struct rad static bool is_dcc_supported_by_CB(const struct radeon_info *info, unsigned sw_mode) { - if (info->chip_class >= GFX11) + if (info->gfx_level >= GFX11) return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X || sw_mode == ADDR_SW_256KB_Z_X || sw_mode == ADDR_SW_256KB_R_X; - if (info->chip_class >= GFX10) + if (info->gfx_level >= GFX10) return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X; return sw_mode != ADDR_SW_LINEAR; @@ -1532,7 +1532,7 @@ static bool is_dcc_supported_by_CB(const struct radeon_info *info, unsigned sw_m ASSERTED static bool is_dcc_supported_by_L2(const struct radeon_info *info, const struct radeon_surf *surf) { - if (info->chip_class <= GFX9) { + if (info->gfx_level <= GFX9) { /* Only independent 64B blocks are supported. */ return surf->u.gfx9.color.dcc.independent_64B_blocks && !surf->u.gfx9.color.dcc.independent_128B_blocks && surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B; @@ -1567,7 +1567,7 @@ ASSERTED static bool is_dcc_supported_by_L2(const struct radeon_info *info, static bool gfx10_DCN_requires_independent_64B_blocks(const struct radeon_info *info, const struct ac_surf_config *config) { - assert(info->chip_class >= GFX10); + assert(info->gfx_level >= GFX10); /* Older kernels have buggy DAL. */ if (info->drm_minor <= 43) @@ -1589,7 +1589,7 @@ void ac_modifier_max_extent(const struct radeon_info *info, if (ac_modifier_has_dcc(modifier)) { bool independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); - if (info->chip_class >= GFX10 && !independent_64B_blocks) { + if (info->gfx_level >= GFX10 && !independent_64B_blocks) { /* For 4K, DCN requires INDEPENDENT_64B_BLOCKS = 1 and MAX_COMPRESSED_BLOCK_SIZE = 64B. */ *width = 2560; *height = 2560; @@ -1613,7 +1613,7 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info, if (info->use_display_dcc_unaligned && (rb_aligned || pipe_aligned)) return false; - switch (info->chip_class) { + switch (info->gfx_level) { case GFX6: case GFX7: case GFX8: @@ -1631,7 +1631,7 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info, case GFX10_3: case GFX11: /* DCN requires INDEPENDENT_128B_BLOCKS = 0 only on Navi1x. */ - if (info->chip_class == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks) + if (info->gfx_level == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks) return false; return (!gfx10_DCN_requires_independent_64B_blocks(info, config) || @@ -1651,7 +1651,7 @@ static void ac_copy_dcc_equation(const struct radeon_info *info, equation->meta_block_height = dcc->metaBlkHeight; equation->meta_block_depth = dcc->metaBlkDepth; - if (info->chip_class >= GFX10) { + if (info->gfx_level >= GFX10) { /* gfx9_meta_equation doesn't store the first 4 and the last 8 elements. They must be 0. */ for (unsigned i = 0; i < 4; i++) assert(dcc->equation.gfx10_bits[i] == 0); @@ -1683,7 +1683,7 @@ static void ac_copy_cmask_equation(const struct radeon_info *info, equation->meta_block_height = cmask->metaBlkHeight; equation->meta_block_depth = 1; - if (info->chip_class == GFX9) { + if (info->gfx_level == GFX9) { assert(cmask->equation.gfx9.num_bits <= ARRAY_SIZE(equation->u.gfx9.bit)); equation->u.gfx9.num_bits = cmask->equation.gfx9.num_bits; @@ -1740,7 +1740,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ for (unsigned i = 0; i < in->numMipLevels; i++) { surf->u.gfx9.prt_level_offset[i] = mip_info[i].macroBlockOffset + mip_info[i].mipTailOffset; - if (info->chip_class >= GFX10) + if (info->gfx_level >= GFX10) surf->u.gfx9.prt_level_pitch[i] = mip_info[i].pitch; else surf->u.gfx9.prt_level_pitch[i] = out.mipChainPitch; @@ -1857,7 +1857,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ if (!surf->num_meta_levels) surf->meta_size = 0; - if (info->chip_class >= GFX10) + if (info->gfx_level >= GFX10) ac_copy_htile_equation(info, &hout, &surf->u.gfx9.zs.htile_equation); return 0; } @@ -1919,10 +1919,10 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ din.dataSurfaceSize = out.surfSize; din.firstMipIdInTail = out.firstMipIdInTail; - if (info->chip_class == GFX9) + if (info->gfx_level == GFX9) simple_mtx_lock(&addrlib->lock); ret = Addr2ComputeDccInfo(addrlib->handle, &din, &dout); - if (info->chip_class == GFX9) + if (info->gfx_level == GFX9) simple_mtx_unlock(&addrlib->lock); if (ret != ADDR_OK) @@ -1973,7 +1973,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ * TODO: Try to do the same thing for gfx9 * if there are no regressions. */ - if (info->chip_class >= GFX10) + if (info->gfx_level >= GFX10) surf->num_meta_levels = i + 1; else surf->num_meta_levels = i; @@ -2005,10 +2005,10 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ assert(surf->tile_swizzle == 0); assert(surf->u.gfx9.color.dcc.pipe_aligned || surf->u.gfx9.color.dcc.rb_aligned); - if (info->chip_class == GFX9) + if (info->gfx_level == GFX9) simple_mtx_lock(&addrlib->lock); ret = Addr2ComputeDccInfo(addrlib->handle, &din, &dout); - if (info->chip_class == GFX9) + if (info->gfx_level == GFX9) simple_mtx_unlock(&addrlib->lock); if (ret != ADDR_OK) @@ -2026,7 +2026,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ } /* FMASK (it doesn't exist on GFX11) */ - if (info->chip_class <= GFX10_3 && info->has_graphics && + if (info->gfx_level <= GFX10_3 && info->has_graphics && in->numSamples > 1 && !(surf->flags & RADEON_SURF_NO_FMASK)) { ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0}; ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0}; @@ -2082,9 +2082,9 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ } /* CMASK -- on GFX10 only for FMASK (and it doesn't exist on GFX11) */ - if (info->chip_class <= GFX10_3 && info->has_graphics && + if (info->gfx_level <= GFX10_3 && info->has_graphics && in->swizzleMode != ADDR_SW_LINEAR && in->resourceType == ADDR_RSRC_TEX_2D && - ((info->chip_class <= GFX9 && in->numSamples == 1 && in->flags.metaPipeUnaligned == 0 && + ((info->gfx_level <= GFX9 && in->numSamples == 1 && in->flags.metaPipeUnaligned == 0 && in->flags.metaRbUnaligned == 0) || (surf->fmask_size && in->numSamples >= 2))) { ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0}; @@ -2112,10 +2112,10 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ else cin.swizzleMode = in->swizzleMode; - if (info->chip_class == GFX9) + if (info->gfx_level == GFX9) simple_mtx_lock(&addrlib->lock); ret = Addr2ComputeCmaskInfo(addrlib->handle, &cin, &cout); - if (info->chip_class == GFX9) + if (info->gfx_level == GFX9) simple_mtx_unlock(&addrlib->lock); if (ret != ADDR_OK) @@ -2214,7 +2214,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ * must sample 1D textures as 2D. */ if (config->is_3d) AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D; - else if (info->chip_class != GFX9 && config->is_1d) + else if (info->gfx_level != GFX9 && config->is_1d) AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D; else AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D; @@ -2239,11 +2239,11 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ /* Optimal values for the L2 cache. */ /* Don't change the DCC settings for imported buffers - they might differ. */ if (!(surf->flags & RADEON_SURF_IMPORTED)) { - if (info->chip_class == GFX9) { + if (info->gfx_level == GFX9) { surf->u.gfx9.color.dcc.independent_64B_blocks = 1; surf->u.gfx9.color.dcc.independent_128B_blocks = 0; surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; - } else if (info->chip_class >= GFX10) { + } else if (info->gfx_level >= GFX10) { surf->u.gfx9.color.dcc.independent_64B_blocks = 0; surf->u.gfx9.color.dcc.independent_128B_blocks = 1; surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B; @@ -2276,7 +2276,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; } - if ((info->chip_class >= GFX10_3 && info->family <= CHIP_YELLOW_CARP) || + if ((info->gfx_level >= GFX10_3 && info->family <= CHIP_YELLOW_CARP) || /* Newer chips will skip this when possible to get better performance. * This is also possible for other gfx10.3 chips, but is disabled for * interoperability between different Mesa versions. @@ -2302,7 +2302,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ case RADEON_SURF_MODE_1D: case RADEON_SURF_MODE_2D: if (surf->flags & RADEON_SURF_IMPORTED || - (info->chip_class >= GFX10 && surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE)) { + (info->gfx_level >= GFX10 && surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE)) { AddrSurfInfoIn.swizzleMode = surf->u.gfx9.swizzle_mode; break; } @@ -2465,7 +2465,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ * used at the same time. We currently do not use rotated * in gfx9. */ - assert(info->chip_class >= GFX10 || !"rotate micro tile mode is unsupported"); + assert(info->gfx_level >= GFX10 || !"rotate micro tile mode is unsupported"); surf->micro_tile_mode = RADEON_MICRO_MODE_RENDER; break; @@ -2530,11 +2530,11 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf if (surf->meta_size && /* dcc_size is computed on GFX9+ only if it's displayable. */ - (info->chip_class >= GFX9 || !get_display_flag(config, surf))) { + (info->gfx_level >= GFX9 || !get_display_flag(config, surf))) { /* It's better when displayable DCC is immediately after * the image due to hw-specific reasons. */ - if (info->chip_class >= GFX9 && + if (info->gfx_level >= GFX9 && !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->u.gfx9.color.dcc.display_equation_valid) { /* Add space for the displayable DCC buffer. */ @@ -2623,7 +2623,7 @@ void ac_surface_set_bo_metadata(const struct radeon_info *info, struct radeon_su { bool scanout; - if (info->chip_class >= GFX9) { + if (info->gfx_level >= GFX9) { surf->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); surf->u.gfx9.color.dcc.independent_64B_blocks = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B); @@ -2663,7 +2663,7 @@ void ac_surface_get_bo_metadata(const struct radeon_info *info, struct radeon_su { *tiling_flags = 0; - if (info->chip_class >= GFX9) { + if (info->gfx_level >= GFX9) { uint64_t dcc_offset = 0; if (surf->meta_offset) { @@ -2721,7 +2721,7 @@ bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_s if (surf->modifier != DRM_FORMAT_MOD_INVALID) return true; - if (info->chip_class >= GFX9) + if (info->gfx_level >= GFX9) offset = surf->u.gfx9.surf_offset; else offset = (uint64_t)surf->u.legacy.level[0].offset_256B * 256; @@ -2763,9 +2763,9 @@ bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_s } } - if (info->chip_class >= GFX8 && G_008F28_COMPRESSION_EN(desc[6])) { + if (info->gfx_level >= GFX8 && G_008F28_COMPRESSION_EN(desc[6])) { /* Read DCC information. */ - switch (info->chip_class) { + switch (info->gfx_level) { case GFX8: surf->meta_offset = (uint64_t)desc[7] << 8; break; @@ -2811,7 +2811,7 @@ void ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_s desc[0] = 0; desc[1] &= C_008F14_BASE_ADDRESS_HI; - switch (info->chip_class) { + switch (info->gfx_level) { case GFX6: case GFX7: break; @@ -2854,7 +2854,7 @@ void ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_s *size_metadata = 10 * 4; /* Dwords [10:..] contain the mipmap level offsets. */ - if (info->chip_class <= GFX8) { + if (info->gfx_level <= GFX8) { for (unsigned i = 0; i < num_mipmap_levels; i++) metadata[10 + i] = surf->u.legacy.level[i].offset_256B; @@ -2899,9 +2899,9 @@ bool ac_surface_override_offset_stride(const struct radeon_info *info, struct ra */ bool require_equal_pitch = surf->surf_size != surf->total_size || num_mipmap_levels != 1 || - info->chip_class >= GFX10; + info->gfx_level >= GFX10; - if (info->chip_class >= GFX9) { + if (info->gfx_level >= GFX9) { if (pitch) { if (surf->u.gfx9.surf_pitch != pitch && require_equal_pitch) return false; @@ -2964,13 +2964,13 @@ unsigned ac_surface_get_nplanes(const struct radeon_surf *surf) return 1; } -uint64_t ac_surface_get_plane_offset(enum chip_class chip_class, +uint64_t ac_surface_get_plane_offset(enum amd_gfx_level gfx_level, const struct radeon_surf *surf, unsigned plane, unsigned layer) { switch (plane) { case 0: - if (chip_class >= GFX9) { + if (gfx_level >= GFX9) { return surf->u.gfx9.surf_offset + layer * surf->u.gfx9.surf_slice_size; } else { @@ -2989,13 +2989,13 @@ uint64_t ac_surface_get_plane_offset(enum chip_class chip_class, } } -uint64_t ac_surface_get_plane_stride(enum chip_class chip_class, +uint64_t ac_surface_get_plane_stride(enum amd_gfx_level gfx_level, const struct radeon_surf *surf, unsigned plane, unsigned level) { switch (plane) { case 0: - if (chip_class >= GFX9) { + if (gfx_level >= GFX9) { return (surf->is_linear ? surf->u.gfx9.pitch[level] : surf->u.gfx9.surf_pitch) * surf->bpe; } else { return surf->u.legacy.level[level].nblk_x * surf->bpe; @@ -3029,7 +3029,7 @@ uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf, void ac_surface_print_info(FILE *out, const struct radeon_info *info, const struct radeon_surf *surf) { - if (info->chip_class >= GFX9) { + if (info->gfx_level >= GFX9) { fprintf(out, " Surf: size=%" PRIu64 ", slice_size=%" PRIu64 ", " "alignment=%u, swmode=%u, epitch=%u, pitch=%u, blk_w=%u, " @@ -3133,7 +3133,7 @@ static nir_ssa_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct nir_ssa_def *zero = nir_imm_int(b, 0); nir_ssa_def *one = nir_imm_int(b, 1); - assert(info->chip_class >= GFX10); + assert(info->gfx_level >= GFX10); unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width); unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height); @@ -3188,7 +3188,7 @@ static nir_ssa_def *gfx9_nir_meta_addr_from_coord(nir_builder *b, const struct r nir_ssa_def *zero = nir_imm_int(b, 0); nir_ssa_def *one = nir_imm_int(b, 1); - assert(info->chip_class >= GFX9); + assert(info->gfx_level >= GFX9); unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width); unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height); @@ -3253,7 +3253,7 @@ nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *sample, nir_ssa_def *pipe_xor) { - if (info->chip_class >= GFX10) { + if (info->gfx_level >= GFX10) { unsigned bpp_log2 = util_logbase2(bpe); return gfx10_nir_meta_addr_from_coord(b, info, equation, bpp_log2 - 8, 1, @@ -3276,7 +3276,7 @@ nir_ssa_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_in { nir_ssa_def *zero = nir_imm_int(b, 0); - if (info->chip_class >= GFX10) { + if (info->gfx_level >= GFX10) { return gfx10_nir_meta_addr_from_coord(b, info, equation, -7, 1, cmask_pitch, cmask_slice_size, x, y, z, pipe_xor, bit_position); diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 1f8114bb4b7..67c5914e073 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -460,10 +460,10 @@ void ac_modifier_max_extent(const struct radeon_info *info, uint64_t modifier, uint32_t *width, uint32_t *height); unsigned ac_surface_get_nplanes(const struct radeon_surf *surf); -uint64_t ac_surface_get_plane_offset(enum chip_class chip_class, +uint64_t ac_surface_get_plane_offset(enum amd_gfx_level gfx_level, const struct radeon_surf *surf, unsigned plane, unsigned layer); -uint64_t ac_surface_get_plane_stride(enum chip_class chip_class, +uint64_t ac_surface_get_plane_stride(enum amd_gfx_level gfx_level, const struct radeon_surf *surf, unsigned plane, unsigned level); /* Of the whole miplevel, not an individual layer */ @@ -473,7 +473,7 @@ uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf, void ac_surface_print_info(FILE *out, const struct radeon_info *info, const struct radeon_surf *surf); -bool ac_surface_supports_dcc_image_stores(enum chip_class chip_class, +bool ac_surface_supports_dcc_image_stores(enum amd_gfx_level gfx_level, const struct radeon_surf *surf); #ifdef AC_SURFACE_INCLUDE_NIR diff --git a/src/amd/common/ac_surface_meta_address_test.c b/src/amd/common/ac_surface_meta_address_test.c index b1a39182a4d..f16354ea62e 100644 --- a/src/amd/common/ac_surface_meta_address_test.c +++ b/src/amd/common/ac_surface_meta_address_test.c @@ -261,7 +261,7 @@ static bool one_dcc_address_test(const char *name, const char *test, ADDR_HANDLE /* Validate that the packed gfx9_meta_equation structure can fit all fields. */ const struct gfx9_meta_equation eq; - if (info->chip_class == GFX9) { + if (info->gfx_level == GFX9) { /* The bit array is smaller in gfx9_meta_equation than in addrlib. */ assert(dout.equation.gfx9.num_bits <= ARRAY_SIZE(eq.u.gfx9.bit)); } else { @@ -284,7 +284,7 @@ static bool one_dcc_address_test(const char *name, const char *test, ADDR_HANDLE } unsigned addr; - if (info->chip_class == GFX9) { + if (info->gfx_level == GFX9) { addr = gfx9_meta_addr_from_coord(info, &dout.equation.gfx9, dout.metaBlkWidth, dout.metaBlkHeight, dout.metaBlkDepth, dout.pitch, dout.height, in.x, in.y, in.slice, in.sample, in.pipeXor, NULL); @@ -321,7 +321,7 @@ static void run_dcc_address_test(const char *name, const struct radeon_info *inf unsigned last_size, max_samples, min_bpp, max_bpp; unsigned swizzle_modes[2], num_swizzle_modes = 0; - switch (info->chip_class) { + switch (info->gfx_level) { case GFX9: swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_S_X; break; @@ -334,7 +334,7 @@ static void run_dcc_address_test(const char *name, const struct radeon_info *inf swizzle_modes[num_swizzle_modes++] = ADDR_SW_256KB_R_X; break; default: - unreachable("unhandled gfx version"); + unreachable("unhandled gfx level"); } if (full) { @@ -366,7 +366,7 @@ static void run_dcc_address_test(const char *name, const struct radeon_info *inf for (unsigned swizzle_mode = 0; swizzle_mode < num_swizzle_modes; swizzle_mode++) { for (unsigned bpp = min_bpp; bpp <= max_bpp; bpp *= 2) { /* addrlib can do DccAddrFromCoord with MSAA images only on gfx9 */ - for (unsigned samples = 1; samples <= (info->chip_class == GFX9 ? max_samples : 1); samples *= 2) { + for (unsigned samples = 1; samples <= (info->gfx_level == GFX9 ? max_samples : 1); samples *= 2) { for (int rb_aligned = true; rb_aligned >= (samples > 1 ? true : false); rb_aligned--) { for (int pipe_aligned = true; pipe_aligned >= (samples > 1 ? true : false); pipe_aligned--) { for (unsigned mrt_index = 0; mrt_index < 2; mrt_index++) { @@ -501,7 +501,7 @@ static void run_htile_address_test(const char *name, const struct radeon_info *i unsigned first_size = 0, last_size = 6*6 - 1; unsigned swizzle_modes[2], num_swizzle_modes = 0; - switch (info->chip_class) { + switch (info->gfx_level) { case GFX9: case GFX10: case GFX10_3: @@ -512,7 +512,7 @@ static void run_htile_address_test(const char *name, const struct radeon_info *i swizzle_modes[num_swizzle_modes++] = ADDR_SW_256KB_Z_X; break; default: - unreachable("unhandled gfx version"); + unreachable("unhandled gfx level"); } /* The test coverage is reduced for Gitlab CI because it timeouts. */ @@ -638,7 +638,7 @@ static bool one_cmask_address_test(const char *name, const char *test, ADDR_HAND unsigned addr, bit_position; - if (info->chip_class == GFX9) { + if (info->gfx_level == GFX9) { addr = gfx9_meta_addr_from_coord(info, &cout.equation.gfx9, cout.metaBlkWidth, cout.metaBlkHeight, 1, cout.pitch, cout.height, @@ -672,11 +672,11 @@ static void run_cmask_address_test(const char *name, const struct radeon_info *i { unsigned total = 0; unsigned fails = 0; - unsigned swizzle_mode = info->chip_class == GFX9 ? ADDR_SW_64KB_S_X : ADDR_SW_64KB_Z_X; + unsigned swizzle_mode = info->gfx_level == GFX9 ? ADDR_SW_64KB_S_X : ADDR_SW_64KB_Z_X; unsigned first_size = 0, last_size = 6*6 - 1, max_bpp = 32; /* GFX11 doesn't have CMASK. */ - if (info->chip_class >= GFX11) + if (info->gfx_level >= GFX11) return; /* The test coverage is reduced for Gitlab CI because it timeouts. */ @@ -738,7 +738,7 @@ int main(int argc, char **argv) struct radeon_info info = get_radeon_info(&testcases[i]); /* Only GFX10+ is currently supported. */ - if (info.chip_class < GFX10) + if (info.gfx_level < GFX10) continue; run_htile_address_test(testcases[i].name, &info, full); diff --git a/src/amd/common/ac_surface_modifier_test.c b/src/amd/common/ac_surface_modifier_test.c index b57ccc4cf3b..49af6c5ab5e 100644 --- a/src/amd/common/ac_surface_modifier_test.c +++ b/src/amd/common/ac_surface_modifier_test.c @@ -241,7 +241,7 @@ static void test_modifier(const struct radeon_info *info, .rb = G_0098F8_NUM_RB_PER_SE(info->gb_addr_config) + G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config), .se = G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config), - .banks_or_pkrs = info->chip_class >= GFX10 ? + .banks_or_pkrs = info->gfx_level >= GFX10 ? G_0098F8_NUM_PKRS(info->gb_addr_config) : G_0098F8_NUM_BANKS(info->gb_addr_config) }; @@ -279,7 +279,7 @@ static void test_modifier(const struct radeon_info *info, uint64_t expected_offset = surf_size; if (ac_modifier_has_dcc_retile(modifier)) { - unsigned dcc_align = info->chip_class >= GFX10 ? 4096 : 65536; + unsigned dcc_align = info->gfx_level >= GFX10 ? 4096 : 65536; unsigned dcc_pitch; uint64_t dcc_size = block_count(dims[i][0], dims[i][1], elem_bits, 20, &dcc_pitch, @@ -296,9 +296,9 @@ static void test_modifier(const struct radeon_info *info, if (ac_modifier_has_dcc(modifier)) { uint64_t dcc_align = 1; unsigned block_bits; - if (info->chip_class >= GFX10) { + if (info->gfx_level >= GFX10) { unsigned num_pipes = G_0098F8_NUM_PIPES(info->gb_addr_config); - if (info->chip_class >= GFX10_3 && + if (info->gfx_level >= GFX10_3 && G_0098F8_NUM_PKRS(info->gb_addr_config) == num_pipes && num_pipes > 1) ++num_pipes; block_bits = 16 + diff --git a/src/amd/common/ac_surface_test_common.h b/src/amd/common/ac_surface_test_common.h index 928490efafd..adb0d53455d 100644 --- a/src/amd/common/ac_surface_test_common.h +++ b/src/amd/common/ac_surface_test_common.h @@ -35,7 +35,7 @@ typedef void (*gpu_init_func)(struct radeon_info *info); static void init_vega10(struct radeon_info *info) { info->family = CHIP_VEGA10; - info->chip_class = GFX9; + info->gfx_level = GFX9; info->family_id = AMDGPU_FAMILY_AI; info->chip_external_rev = 0x01; info->use_display_dcc_unaligned = false; @@ -50,7 +50,7 @@ static void init_vega10(struct radeon_info *info) static void init_vega20(struct radeon_info *info) { info->family = CHIP_VEGA20; - info->chip_class = GFX9; + info->gfx_level = GFX9; info->family_id = AMDGPU_FAMILY_AI; info->chip_external_rev = 0x30; info->use_display_dcc_unaligned = false; @@ -66,7 +66,7 @@ static void init_vega20(struct radeon_info *info) static void init_raven(struct radeon_info *info) { info->family = CHIP_RAVEN; - info->chip_class = GFX9; + info->gfx_level = GFX9; info->family_id = AMDGPU_FAMILY_RV; info->chip_external_rev = 0x01; info->use_display_dcc_unaligned = false; @@ -81,7 +81,7 @@ static void init_raven(struct radeon_info *info) static void init_raven2(struct radeon_info *info) { info->family = CHIP_RAVEN2; - info->chip_class = GFX9; + info->gfx_level = GFX9; info->family_id = AMDGPU_FAMILY_RV; info->chip_external_rev = 0x82; info->use_display_dcc_unaligned = true; @@ -96,7 +96,7 @@ static void init_raven2(struct radeon_info *info) static void init_navi10(struct radeon_info *info) { info->family = CHIP_NAVI10; - info->chip_class = GFX10; + info->gfx_level = GFX10; info->family_id = AMDGPU_FAMILY_NV; info->chip_external_rev = 3; info->use_display_dcc_unaligned = false; @@ -110,7 +110,7 @@ static void init_navi10(struct radeon_info *info) static void init_navi14(struct radeon_info *info) { info->family = CHIP_NAVI14; - info->chip_class = GFX10; + info->gfx_level = GFX10; info->family_id = AMDGPU_FAMILY_NV; info->chip_external_rev = 0x15; info->use_display_dcc_unaligned = false; @@ -124,7 +124,7 @@ static void init_navi14(struct radeon_info *info) static void init_gfx103(struct radeon_info *info) { info->family = CHIP_SIENNA_CICHLID; /* This doesn't affect tests. */ - info->chip_class = GFX10_3; + info->gfx_level = GFX10_3; info->family_id = AMDGPU_FAMILY_NV; info->chip_external_rev = 0x28; info->use_display_dcc_unaligned = false; @@ -140,7 +140,7 @@ static void init_gfx103(struct radeon_info *info) static void init_gfx11(struct radeon_info *info) { info->family = CHIP_UNKNOWN; - info->chip_class = GFX11; + info->gfx_level = GFX11; info->family_id = 0x00; info->chip_external_rev = 0x01; info->use_display_dcc_unaligned = false; @@ -192,7 +192,7 @@ static struct radeon_info get_radeon_info(struct testcase *testcase) testcase->init(&info); - switch(info.chip_class) { + switch(info.gfx_level) { case GFX9: info.gb_addr_config = (info.gb_addr_config & C_0098F8_NUM_PIPES & @@ -213,7 +213,7 @@ static struct radeon_info get_radeon_info(struct testcase *testcase) S_0098F8_NUM_PIPES(testcase->pipes) | S_0098F8_NUM_PKRS(testcase->banks_or_pkrs); /* 1 packer implies 1 RB except gfx10 where the field is ignored. */ - info.max_render_backends = info.chip_class == GFX10 || testcase->banks_or_pkrs ? 2 : 1; + info.max_render_backends = info.gfx_level == GFX10 || testcase->banks_or_pkrs ? 2 : 1; break; default: unreachable("Unhandled generation"); diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h index 92ac1d978ad..cb27f29ecae 100644 --- a/src/amd/common/amd_family.h +++ b/src/amd/common/amd_family.h @@ -135,7 +135,7 @@ enum radeon_family CHIP_LAST, }; -enum chip_class +enum amd_gfx_level { CLASS_UNKNOWN = 0, R300, diff --git a/src/amd/common/gfx10_format_table.h b/src/amd/common/gfx10_format_table.h index 9e88810d26a..4da6c34ce7b 100644 --- a/src/amd/common/gfx10_format_table.h +++ b/src/amd/common/gfx10_format_table.h @@ -47,7 +47,7 @@ extern const struct gfx10_format gfx11_format_table[PIPE_FORMAT_COUNT]; static inline const struct gfx10_format* ac_get_gfx10_format_table(struct radeon_info *info) { - if (info->chip_class >= GFX11) + if (info->gfx_level >= GFX11) return gfx11_format_table; else return gfx10_format_table; diff --git a/src/amd/common/sid_tables.py b/src/amd/common/sid_tables.py index c8fd312935b..5900ac8313e 100644 --- a/src/amd/common/sid_tables.py +++ b/src/amd/common/sid_tables.py @@ -360,7 +360,7 @@ def main(): print('Error reading {}'.format(sys.argv[1]), file=sys.stderr) raise - # The ac_debug code only distinguishes by chip_class + # The ac_debug code only distinguishes by gfx_level regdb.merge_chips(['gfx8', 'fiji', 'stoney'], 'gfx8') # Write it all out diff --git a/src/amd/compiler/aco_assembler.cpp b/src/amd/compiler/aco_assembler.cpp index 3095f0bda89..a9357cf968c 100644 --- a/src/amd/compiler/aco_assembler.cpp +++ b/src/amd/compiler/aco_assembler.cpp @@ -42,19 +42,19 @@ struct constaddr_info { struct asm_context { Program* program; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; std::vector<std::pair<int, SOPP_instruction*>> branches; std::map<unsigned, constaddr_info> constaddrs; const int16_t* opcode; // TODO: keep track of branch instructions referring blocks // and, when emitting the block, correct the offset in instr - asm_context(Program* program_) : program(program_), chip_class(program->chip_class) + asm_context(Program* program_) : program(program_), gfx_level(program->gfx_level) { - if (chip_class <= GFX7) + if (gfx_level <= GFX7) opcode = &instr_info.opcode_gfx7[0]; - else if (chip_class <= GFX9) + else if (gfx_level <= GFX9) opcode = &instr_info.opcode_gfx9[0]; - else if (chip_class >= GFX10) + else if (gfx_level >= GFX10) opcode = &instr_info.opcode_gfx10[0]; } @@ -121,11 +121,11 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst SOPK_instruction& sopk = instr->sopk(); if (instr->opcode == aco_opcode::s_subvector_loop_begin) { - assert(ctx.chip_class >= GFX10); + assert(ctx.gfx_level >= GFX10); assert(ctx.subvector_begin_pos == -1); ctx.subvector_begin_pos = out.size(); } else if (instr->opcode == aco_opcode::s_subvector_loop_end) { - assert(ctx.chip_class >= GFX10); + assert(ctx.gfx_level >= GFX10); assert(ctx.subvector_begin_pos != -1); /* Adjust s_subvector_loop_begin instruction to the address after the end */ out[ctx.subvector_begin_pos] |= (out.size() - ctx.subvector_begin_pos); @@ -147,8 +147,8 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst } case Format::SOP1: { uint32_t encoding = (0b101111101 << 23); - if (opcode >= 55 && ctx.chip_class <= GFX9) { - assert(ctx.chip_class == GFX9 && opcode < 60); + if (opcode >= 55 && ctx.gfx_level <= GFX9) { + assert(ctx.gfx_level == GFX9 && opcode < 60); opcode = opcode - 4; } encoding |= !instr->definitions.empty() ? instr->definitions[0].physReg() << 16 : 0; @@ -183,7 +183,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst bool is_load = !instr->definitions.empty(); uint32_t encoding = 0; - if (ctx.chip_class <= GFX7) { + if (ctx.gfx_level <= GFX7) { encoding = (0b11000 << 27); encoding |= opcode << 22; encoding |= instr->definitions.size() ? instr->definitions[0].physReg() << 15 : 0; @@ -206,7 +206,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst return; } - if (ctx.chip_class <= GFX9) { + if (ctx.gfx_level <= GFX9) { encoding = (0b110000 << 26); assert(!smem.dlc); /* Device-level coherent is not supported on GFX9 and lower */ encoding |= smem.nv ? 1 << 15 : 0; @@ -219,11 +219,11 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst encoding |= opcode << 18; encoding |= smem.glc ? 1 << 16 : 0; - if (ctx.chip_class <= GFX9) { + if (ctx.gfx_level <= GFX9) { if (instr->operands.size() >= 2) encoding |= instr->operands[1].isConstant() ? 1 << 17 : 0; /* IMM - immediate enable */ } - if (ctx.chip_class == GFX9) { + if (ctx.gfx_level == GFX9) { encoding |= soe ? 1 << 14 : 0; } @@ -239,13 +239,13 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst encoding = 0; int32_t offset = 0; - uint32_t soffset = ctx.chip_class >= GFX10 + uint32_t soffset = ctx.gfx_level >= GFX10 ? sgpr_null /* On GFX10 this is disabled by specifying SGPR_NULL */ : 0; /* On GFX9, it is disabled by the SOE bit (and it's not present on GFX8 and below) */ if (instr->operands.size() >= 2) { const Operand& op_off1 = instr->operands[1]; - if (ctx.chip_class <= GFX9) { + if (ctx.gfx_level <= GFX9) { offset = op_off1.isConstant() ? op_off1.constantValue() : op_off1.physReg(); } else { /* GFX10 only supports constants in OFFSET, so put the operand in SOFFSET if it's an @@ -260,7 +260,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst if (soe) { const Operand& op_off2 = instr->operands.back(); - assert(ctx.chip_class >= GFX9); /* GFX8 and below don't support specifying a constant + assert(ctx.gfx_level >= GFX9); /* GFX8 and below don't support specifying a constant and an SGPR at the same time */ assert(!op_off2.isConstant()); soffset = op_off2.physReg(); @@ -307,12 +307,12 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst instr->opcode == aco_opcode::v_interp_p1lv_f16 || instr->opcode == aco_opcode::v_interp_p2_legacy_f16 || instr->opcode == aco_opcode::v_interp_p2_f16) { - if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) { + if (ctx.gfx_level == GFX8 || ctx.gfx_level == GFX9) { encoding = (0b110100 << 26); - } else if (ctx.chip_class >= GFX10) { + } else if (ctx.gfx_level >= GFX10) { encoding = (0b110101 << 26); } else { - unreachable("Unknown chip_class."); + unreachable("Unknown gfx_level."); } encoding |= opcode << 16; @@ -330,7 +330,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst } out.push_back(encoding); } else { - if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) { + if (ctx.gfx_level == GFX8 || ctx.gfx_level == GFX9) { encoding = (0b110101 << 26); /* Vega ISA doc says 110010 but it's wrong */ } else { encoding = (0b110010 << 26); @@ -352,7 +352,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst case Format::DS: { DS_instruction& ds = instr->ds(); uint32_t encoding = (0b110110 << 26); - if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) { + if (ctx.gfx_level == GFX8 || ctx.gfx_level == GFX9) { encoding |= opcode << 17; encoding |= (ds.gds ? 1 : 0) << 16; } else { @@ -384,20 +384,20 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst encoding |= (mubuf.lds ? 1 : 0) << 16; encoding |= (mubuf.glc ? 1 : 0) << 14; encoding |= (mubuf.idxen ? 1 : 0) << 13; - assert(!mubuf.addr64 || ctx.chip_class <= GFX7); - if (ctx.chip_class == GFX6 || ctx.chip_class == GFX7) + assert(!mubuf.addr64 || ctx.gfx_level <= GFX7); + if (ctx.gfx_level == GFX6 || ctx.gfx_level == GFX7) encoding |= (mubuf.addr64 ? 1 : 0) << 15; encoding |= (mubuf.offen ? 1 : 0) << 12; - if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) { + if (ctx.gfx_level == GFX8 || ctx.gfx_level == GFX9) { assert(!mubuf.dlc); /* Device-level coherent is not supported on GFX9 and lower */ encoding |= (mubuf.slc ? 1 : 0) << 17; - } else if (ctx.chip_class >= GFX10) { + } else if (ctx.gfx_level >= GFX10) { encoding |= (mubuf.dlc ? 1 : 0) << 15; } encoding |= 0x0FFF & mubuf.offset; out.push_back(encoding); encoding = 0; - if (ctx.chip_class <= GFX7 || ctx.chip_class >= GFX10) { + if (ctx.gfx_level <= GFX7 || ctx.gfx_level >= GFX10) { encoding |= (mubuf.slc ? 1 : 0) << 22; } encoding |= instr->operands[2].physReg() << 24; @@ -413,10 +413,10 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst case Format::MTBUF: { MTBUF_instruction& mtbuf = instr->mtbuf(); - uint32_t img_format = ac_get_tbuffer_format(ctx.chip_class, mtbuf.dfmt, mtbuf.nfmt); + uint32_t img_format = ac_get_tbuffer_format(ctx.gfx_level, mtbuf.dfmt, mtbuf.nfmt); uint32_t encoding = (0b111010 << 26); assert(img_format <= 0x7F); - assert(!mtbuf.dlc || ctx.chip_class >= GFX10); + assert(!mtbuf.dlc || ctx.gfx_level >= GFX10); encoding |= (mtbuf.dlc ? 1 : 0) << 15; /* DLC bit replaces one bit of the OPCODE on GFX10 */ encoding |= (mtbuf.glc ? 1 : 0) << 14; encoding |= (mtbuf.idxen ? 1 : 0) << 13; @@ -424,7 +424,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst encoding |= 0x0FFF & mtbuf.offset; encoding |= (img_format << 19); /* Handles both the GFX10 FORMAT and the old NFMT+DFMT */ - if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) { + if (ctx.gfx_level == GFX8 || ctx.gfx_level == GFX9) { encoding |= opcode << 15; } else { encoding |= (opcode & 0x07) << 16; /* 3 LSBs of 4-bit OPCODE */ @@ -442,7 +442,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst encoding |= (0xFF & reg) << 8; encoding |= (0xFF & instr->operands[1].physReg()); - if (ctx.chip_class >= GFX10) { + if (ctx.gfx_level >= GFX10) { encoding |= (((opcode & 0x08) >> 3) << 21); /* MSB of 4-bit OPCODE */ } @@ -451,7 +451,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst } case Format::MIMG: { unsigned nsa_dwords = get_mimg_nsa_dwords(instr); - assert(!nsa_dwords || ctx.chip_class >= GFX10); + assert(!nsa_dwords || ctx.gfx_level >= GFX10); MIMG_instruction& mimg = instr->mimg(); uint32_t encoding = (0b111100 << 26); @@ -462,7 +462,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst encoding |= mimg.tfe ? 1 << 16 : 0; encoding |= mimg.glc ? 1 << 13 : 0; encoding |= mimg.unrm ? 1 << 12 : 0; - if (ctx.chip_class <= GFX9) { + if (ctx.gfx_level <= GFX9) { assert(!mimg.dlc); /* Device-level coherent is not supported on GFX9 and lower */ assert(!mimg.r128); encoding |= mimg.a16 ? 1 << 15 : 0; @@ -486,9 +486,9 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst if (!instr->operands[1].isUndefined()) encoding |= (0x1F & (instr->operands[1].physReg() >> 2)) << 21; /* sampler */ - assert(!mimg.d16 || ctx.chip_class >= GFX9); + assert(!mimg.d16 || ctx.gfx_level >= GFX9); encoding |= mimg.d16 ? 1 << 31 : 0; - if (ctx.chip_class >= GFX10) { + if (ctx.gfx_level >= GFX10) { /* GFX10: A16 still exists, but is in a different place */ encoding |= mimg.a16 ? 1 << 30 : 0; } @@ -509,7 +509,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst FLAT_instruction& flat = instr->flatlike(); uint32_t encoding = (0b110111 << 26); encoding |= opcode << 18; - if (ctx.chip_class <= GFX9) { + if (ctx.gfx_level <= GFX9) { assert(flat.offset <= 0x1fff); encoding |= flat.offset & 0x1fff; } else if (instr->isFlat()) { @@ -528,7 +528,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst encoding |= flat.lds ? 1 << 13 : 0; encoding |= flat.glc ? 1 << 16 : 0; encoding |= flat.slc ? 1 << 17 : 0; - if (ctx.chip_class >= GFX10) { + if (ctx.gfx_level >= GFX10) { assert(!flat.nv); encoding |= flat.dlc ? 1 << 12 : 0; } else { @@ -541,12 +541,12 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst if (instr->operands.size() >= 3) encoding |= (0xFF & instr->operands[2].physReg()) << 8; if (!instr->operands[1].isUndefined()) { - assert(ctx.chip_class >= GFX10 || instr->operands[1].physReg() != 0x7F); + assert(ctx.gfx_level >= GFX10 || instr->operands[1].physReg() != 0x7F); assert(instr->format != Format::FLAT); encoding |= instr->operands[1].physReg() << 16; } else if (instr->format != Format::FLAT || - ctx.chip_class >= GFX10) { /* SADDR is actually used with FLAT on GFX10 */ - if (ctx.chip_class <= GFX9) + ctx.gfx_level >= GFX10) { /* SADDR is actually used with FLAT on GFX10 */ + if (ctx.gfx_level <= GFX9) encoding |= 0x7F << 16; else encoding |= sgpr_null << 16; @@ -558,7 +558,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst case Format::EXP: { Export_instruction& exp = instr->exp(); uint32_t encoding; - if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) { + if (ctx.gfx_level == GFX8 || ctx.gfx_level == GFX9) { encoding = (0b110001 << 26); } else { encoding = (0b111110 << 26); @@ -589,7 +589,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst if (instr->isVOP2()) { opcode = opcode + 0x100; } else if (instr->isVOP1()) { - if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) + if (ctx.gfx_level == GFX8 || ctx.gfx_level == GFX9) opcode = opcode + 0x140; else opcode = opcode + 0x180; @@ -600,15 +600,15 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst } uint32_t encoding; - if (ctx.chip_class <= GFX9) { + if (ctx.gfx_level <= GFX9) { encoding = (0b110100 << 26); - } else if (ctx.chip_class >= GFX10) { + } else if (ctx.gfx_level >= GFX10) { encoding = (0b110101 << 26); } else { - unreachable("Unknown chip_class."); + unreachable("Unknown gfx_level."); } - if (ctx.chip_class <= GFX7) { + if (ctx.gfx_level <= GFX7) { encoding |= opcode << 17; encoding |= (vop3.clamp ? 1 : 0) << 11; } else { @@ -642,12 +642,12 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst VOP3P_instruction& vop3 = instr->vop3p(); uint32_t encoding; - if (ctx.chip_class == GFX9) { + if (ctx.gfx_level == GFX9) { encoding = (0b110100111 << 23); - } else if (ctx.chip_class >= GFX10) { + } else if (ctx.gfx_level >= GFX10) { encoding = (0b110011 << 26); } else { - unreachable("Unknown chip_class."); + unreachable("Unknown gfx_level."); } encoding |= opcode << 16; @@ -667,7 +667,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst out.push_back(encoding); } else if (instr->isDPP16()) { - assert(ctx.chip_class >= GFX8); + assert(ctx.gfx_level >= GFX8); DPP16_instruction& dpp = instr->dpp16(); /* first emit the instruction without the DPP operand */ @@ -681,7 +681,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst encoding |= dpp.neg[1] << 22; encoding |= dpp.abs[0] << 21; encoding |= dpp.neg[0] << 20; - if (ctx.chip_class >= GFX10) + if (ctx.gfx_level >= GFX10) encoding |= 1 << 18; /* set Fetch Inactive to match GFX9 behaviour */ encoding |= dpp.bound_ctrl << 19; encoding |= dpp.dpp_ctrl << 8; @@ -689,7 +689,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst out.push_back(encoding); return; } else if (instr->isDPP8()) { - assert(ctx.chip_class >= GFX10); + assert(ctx.gfx_level >= GFX10); DPP8_instruction& dpp = instr->dpp8(); /* first emit the instruction without the DPP operand */ @@ -938,7 +938,7 @@ fix_branches(asm_context& ctx, std::vector<uint32_t>& out) do { repeat = false; - if (ctx.chip_class == GFX10) + if (ctx.gfx_level == GFX10) fix_branches_gfx10(ctx, out); for (std::pair<int, SOPP_instruction*>& branch : ctx.branches) { @@ -995,7 +995,7 @@ emit_program(Program* program, std::vector<uint32_t>& code) unsigned exec_size = code.size() * sizeof(uint32_t); - if (program->chip_class >= GFX10) { + if (program->gfx_level >= GFX10) { /* Pad output with s_code_end so instruction prefetching doesn't cause * page faults */ unsigned final_size = align(code.size() + 3 * 16, 16); diff --git a/src/amd/compiler/aco_builder_h.py b/src/amd/compiler/aco_builder_h.py index 86d247a80a5..5801d3c523a 100644 --- a/src/amd/compiler/aco_builder_h.py +++ b/src/amd/compiler/aco_builder_h.py @@ -361,10 +361,10 @@ public: Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool bits24=false) { assert(tmp.type() == RegType::vgpr); - bool has_lshl_add = program->chip_class >= GFX9; + bool has_lshl_add = program->gfx_level >= GFX9; /* v_mul_lo_u32 has 1.6x the latency of most VALU on GFX10 (8 vs 5 cycles), * compared to 4x the latency on <GFX10. */ - unsigned mul_cost = program->chip_class >= GFX10 ? 1 : (4 + Operand::c32(imm).isLiteral()); + unsigned mul_cost = program->gfx_level >= GFX10 ? 1 : (4 + Operand::c32(imm).isLiteral()); if (imm == 0) { return copy(dst, Operand::zero()); } else if (imm == 1) { @@ -426,9 +426,9 @@ public: if (!carry_in.op.isUndefined()) return vop2(aco_opcode::v_addc_co_u32, Definition(dst), def(lm), a, b, carry_in); - else if (program->chip_class >= GFX10 && carry_out) + else if (program->gfx_level >= GFX10 && carry_out) return vop3(aco_opcode::v_add_co_u32_e64, Definition(dst), def(lm), a, b); - else if (program->chip_class < GFX9 || carry_out) + else if (program->gfx_level < GFX9 || carry_out) return vop2(aco_opcode::v_add_co_u32, Definition(dst), def(lm), a, b); else return vop2(aco_opcode::v_add_u32, Definition(dst), a, b); @@ -436,7 +436,7 @@ public: Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2))) { - if (!borrow.op.isUndefined() || program->chip_class < GFX9) + if (!borrow.op.isUndefined() || program->gfx_level < GFX9) carry_out = true; bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr; @@ -457,10 +457,10 @@ public: op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32; } bool vop3 = false; - if (program->chip_class >= GFX10 && op == aco_opcode::v_subrev_co_u32) { + if (program->gfx_level >= GFX10 && op == aco_opcode::v_subrev_co_u32) { vop3 = true; op = aco_opcode::v_subrev_co_u32_e64; - } else if (program->chip_class >= GFX10 && op == aco_opcode::v_sub_co_u32) { + } else if (program->gfx_level >= GFX10 && op == aco_opcode::v_sub_co_u32) { vop3 = true; op = aco_opcode::v_sub_co_u32_e64; } @@ -485,13 +485,13 @@ public: Result readlane(Definition dst, Op vsrc, Op lane) { - if (program->chip_class >= GFX8) + if (program->gfx_level >= GFX8) return vop3(aco_opcode::v_readlane_b32_e64, dst, vsrc, lane); else return vop2(aco_opcode::v_readlane_b32, dst, vsrc, lane); } Result writelane(Definition dst, Op val, Op lane, Op vsrc) { - if (program->chip_class >= GFX8) + if (program->gfx_level >= GFX8) return vop3(aco_opcode::v_writelane_b32_e64, dst, val, lane, vsrc); else return vop2(aco_opcode::v_writelane_b32, dst, val, lane, vsrc); diff --git a/src/amd/compiler/aco_form_hard_clauses.cpp b/src/amd/compiler/aco_form_hard_clauses.cpp index fe806f55c79..ebb9b05a62b 100644 --- a/src/amd/compiler/aco_form_hard_clauses.cpp +++ b/src/amd/compiler/aco_form_hard_clauses.cpp @@ -78,7 +78,7 @@ form_hard_clauses(Program* program) clause_type type = clause_other; if (instr->isVMEM() && !instr->operands.empty()) { - if (program->chip_class == GFX10 && instr->isMIMG() && + if (program->gfx_level == GFX10 && instr->isMIMG() && get_mimg_nsa_dwords(instr.get()) > 0) type = clause_other; else diff --git a/src/amd/compiler/aco_insert_NOPs.cpp b/src/amd/compiler/aco_insert_NOPs.cpp index 5dd1c7183e8..b0523868524 100644 --- a/src/amd/compiler/aco_insert_NOPs.cpp +++ b/src/amd/compiler/aco_insert_NOPs.cpp @@ -356,7 +356,7 @@ handle_instruction_gfx6(State& state, NOP_ctx_gfx6& ctx, aco_ptr<Instruction>& i int NOPs = 0; if (instr->isSMEM()) { - if (state.program->chip_class == GFX6) { + if (state.program->gfx_level == GFX6) { /* A read of an SGPR by SMRD instruction requires 4 wait states * when the SGPR was written by a VALU instruction. According to LLVM, * there is also an undocumented hardware behavior when the buffer @@ -382,7 +382,7 @@ handle_instruction_gfx6(State& state, NOP_ctx_gfx6& ctx, aco_ptr<Instruction>& i NOPs = MAX2(NOPs, ctx.setreg_then_getsetreg); } - if (state.program->chip_class == GFX9) { + if (state.program->gfx_level == GFX9) { if (instr->opcode == aco_opcode::s_movrels_b32 || instr->opcode == aco_opcode::s_movrels_b64 || instr->opcode == aco_opcode::s_movreld_b32 || @@ -428,7 +428,7 @@ handle_instruction_gfx6(State& state, NOP_ctx_gfx6& ctx, aco_ptr<Instruction>& i * hangs on GFX6. Note that v_writelane_* is apparently not affected. * This hazard isn't documented anywhere but AMD confirmed that hazard. */ - if (state.program->chip_class == GFX6 && + if (state.program->gfx_level == GFX6 && (instr->opcode == aco_opcode::v_readlane_b32 || /* GFX6 doesn't have v_readlane_b32_e64 */ instr->opcode == aco_opcode::v_readfirstlane_b32)) { handle_vintrp_then_read_hazard(state, &NOPs, 1, instr->operands[0]); @@ -448,7 +448,7 @@ handle_instruction_gfx6(State& state, NOP_ctx_gfx6& ctx, aco_ptr<Instruction>& i if (!instr->isSALU() && instr->format != Format::SMEM) NOPs = MAX2(NOPs, ctx.set_vskip_mode_then_vector); - if (state.program->chip_class == GFX9) { + if (state.program->gfx_level == GFX9) { bool lds_scratch_global = (instr->isScratch() || instr->isGlobal()) && instr->flatlike().lds; if (instr->isVINTRP() || lds_scratch_global || instr->opcode == aco_opcode::ds_read_addtid_b32 || @@ -886,9 +886,9 @@ mitigate_hazards(Program* program) void insert_NOPs(Program* program) { - if (program->chip_class >= GFX10_3) + if (program->gfx_level >= GFX10_3) ; /* no hazards/bugs to mitigate */ - else if (program->chip_class >= GFX10) + else if (program->gfx_level >= GFX10) mitigate_hazards<NOP_ctx_gfx10, handle_instruction_gfx10>(program); else mitigate_hazards<NOP_ctx_gfx6, handle_instruction_gfx6>(program); diff --git a/src/amd/compiler/aco_insert_waitcnt.cpp b/src/amd/compiler/aco_insert_waitcnt.cpp index 9a50597b29f..197d9d2e021 100644 --- a/src/amd/compiler/aco_insert_waitcnt.cpp +++ b/src/amd/compiler/aco_insert_waitcnt.cpp @@ -170,7 +170,7 @@ struct wait_entry { struct wait_ctx { Program* program; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; uint16_t max_vm_cnt; uint16_t max_exp_cnt; uint16_t max_lgkm_cnt; @@ -192,11 +192,11 @@ struct wait_ctx { wait_ctx() {} wait_ctx(Program* program_) - : program(program_), chip_class(program_->chip_class), - max_vm_cnt(program_->chip_class >= GFX9 ? 62 : 14), max_exp_cnt(6), - max_lgkm_cnt(program_->chip_class >= GFX10 ? 62 : 14), - max_vs_cnt(program_->chip_class >= GFX10 ? 62 : 0), - unordered_events(event_smem | (program_->chip_class < GFX10 ? event_flat : 0)) + : program(program_), gfx_level(program_->gfx_level), + max_vm_cnt(program_->gfx_level >= GFX9 ? 62 : 14), max_exp_cnt(6), + max_lgkm_cnt(program_->gfx_level >= GFX10 ? 62 : 14), + max_vs_cnt(program_->gfx_level >= GFX10 ? 62 : 0), + unordered_events(event_smem | (program_->gfx_level < GFX10 ? event_flat : 0)) {} bool join(const wait_ctx* other, bool logical) @@ -295,7 +295,7 @@ parse_wait_instr(wait_ctx& ctx, wait_imm& imm, Instruction* instr) imm.vs = std::min<uint8_t>(imm.vs, instr->sopk().imm); return true; } else if (instr->opcode == aco_opcode::s_waitcnt) { - imm.combine(wait_imm(ctx.chip_class, instr->sopp().imm)); + imm.combine(wait_imm(ctx.gfx_level, instr->sopp().imm)); return true; } return false; @@ -339,7 +339,7 @@ force_waitcnt(wait_ctx& ctx, wait_imm& imm) if (ctx.lgkm_cnt) imm.lgkm = 0; - if (ctx.chip_class >= GFX10) { + if (ctx.gfx_level >= GFX10) { if (ctx.vs_cnt) imm.vs = 0; } @@ -362,11 +362,11 @@ kill(wait_imm& imm, Instruction* instr, wait_ctx& ctx, memory_sync_info sync_inf * It shouldn't cost anything anyways since we're about to do s_endpgm. */ if (ctx.lgkm_cnt && instr->opcode == aco_opcode::s_dcache_wb) { - assert(ctx.chip_class >= GFX8); + assert(ctx.gfx_level >= GFX8); imm.lgkm = 0; } - if (ctx.chip_class >= GFX10 && instr->isSMEM()) { + if (ctx.gfx_level >= GFX10 && instr->isSMEM()) { /* GFX10: A store followed by a load at the same address causes a problem because * the load doesn't load the correct values unless we wait for the store first. * This is NOT mitigated by an s_nop. @@ -547,7 +547,7 @@ update_counters(wait_ctx& ctx, wait_event event, memory_sync_info sync = memory_ void update_counters_for_flat_load(wait_ctx& ctx, memory_sync_info sync = memory_sync_info()) { - assert(ctx.chip_class < GFX10); + assert(ctx.gfx_level < GFX10); if (ctx.lgkm_cnt <= ctx.max_lgkm_cnt) ctx.lgkm_cnt++; @@ -634,7 +634,7 @@ gen(Instruction* instr, wait_ctx& ctx) } case Format::FLAT: { FLAT_instruction& flat = instr->flat(); - if (ctx.chip_class < GFX10 && !instr->definitions.empty()) + if (ctx.gfx_level < GFX10 && !instr->definitions.empty()) update_counters_for_flat_load(ctx, flat.sync); else update_counters(ctx, event_flat, flat.sync); @@ -649,7 +649,7 @@ gen(Instruction* instr, wait_ctx& ctx) if (!instr->definitions.empty()) insert_wait_entry(ctx, instr->definitions[0], event_smem); - else if (ctx.chip_class >= GFX10 && !smem.sync.can_reorder()) + else if (ctx.gfx_level >= GFX10 && !smem.sync.can_reorder()) ctx.pending_s_buffer_store = true; break; @@ -675,7 +675,7 @@ gen(Instruction* instr, wait_ctx& ctx) case Format::MIMG: case Format::GLOBAL: { wait_event ev = - !instr->definitions.empty() || ctx.chip_class < GFX10 ? event_vmem : event_vmem_store; + !instr->definitions.empty() || ctx.gfx_level < GFX10 ? event_vmem : event_vmem_store; update_counters(ctx, ev, get_sync_info(instr)); bool has_sampler = instr->isMIMG() && !instr->operands[1].isUndefined() && @@ -684,11 +684,11 @@ gen(Instruction* instr, wait_ctx& ctx) if (!instr->definitions.empty()) insert_wait_entry(ctx, instr->definitions[0], ev, has_sampler); - if (ctx.chip_class == GFX6 && instr->format != Format::MIMG && instr->operands.size() == 4) { + if (ctx.gfx_level == GFX6 && instr->format != Format::MIMG && instr->operands.size() == 4) { ctx.exp_cnt++; update_counters(ctx, event_vmem_gpr_lock); insert_wait_entry(ctx, instr->operands[3], event_vmem_gpr_lock); - } else if (ctx.chip_class == GFX6 && instr->isMIMG() && !instr->operands[2].isUndefined()) { + } else if (ctx.gfx_level == GFX6 && instr->isMIMG() && !instr->operands[2].isUndefined()) { ctx.exp_cnt++; update_counters(ctx, event_vmem_gpr_lock); insert_wait_entry(ctx, instr->operands[2], event_vmem_gpr_lock); @@ -709,7 +709,7 @@ void emit_waitcnt(wait_ctx& ctx, std::vector<aco_ptr<Instruction>>& instructions, wait_imm& imm) { if (imm.vs != wait_imm::unset_counter) { - assert(ctx.chip_class >= GFX10); + assert(ctx.gfx_level >= GFX10); SOPK_instruction* waitcnt_vs = create_instruction<SOPK_instruction>(aco_opcode::s_waitcnt_vscnt, Format::SOPK, 0, 1); waitcnt_vs->definitions[0] = Definition(sgpr_null, s1); @@ -720,7 +720,7 @@ emit_waitcnt(wait_ctx& ctx, std::vector<aco_ptr<Instruction>>& instructions, wai if (!imm.empty()) { SOPP_instruction* waitcnt = create_instruction<SOPP_instruction>(aco_opcode::s_waitcnt, Format::SOPP, 0, 0); - waitcnt->imm = imm.pack(ctx.chip_class); + waitcnt->imm = imm.pack(ctx.gfx_level); waitcnt->block = -1; instructions.emplace_back(waitcnt); } diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 36698d96357..b34e71c836d 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -159,7 +159,7 @@ emit_mbcnt(isel_context* ctx, Temp dst, Operand mask = Operand(), Operand base = Temp mbcnt_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), mask_lo, base); - if (ctx->program->chip_class <= GFX7) + if (ctx->program->gfx_level <= GFX7) return bld.vop2(aco_opcode::v_mbcnt_hi_u32_b32, Definition(dst), mask_hi, mbcnt_lo); else return bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64, Definition(dst), mask_hi, mbcnt_lo); @@ -192,7 +192,7 @@ emit_bpermute(isel_context* ctx, Builder& bld, Temp index, Temp data) if (index.regClass() == s1) return bld.readlane(bld.def(s1), data, index); - if (ctx->options->chip_class <= GFX7) { + if (ctx->options->gfx_level <= GFX7) { /* GFX6-7: there is no bpermute instruction */ Operand index_op(index); Operand input_data(data); @@ -201,7 +201,7 @@ emit_bpermute(isel_context* ctx, Builder& bld, Temp index, Temp data) return bld.pseudo(aco_opcode::p_bpermute, bld.def(v1), bld.def(bld.lm), bld.def(bld.lm, vcc), index_op, input_data); - } else if (ctx->options->chip_class >= GFX10 && ctx->program->wave_size == 64) { + } else if (ctx->options->gfx_level >= GFX10 && ctx->program->wave_size == 64) { /* GFX10 wave64 mode: emulate full-wave bpermute */ Temp index_is_lo = @@ -235,7 +235,7 @@ emit_bpermute(isel_context* ctx, Builder& bld, Temp index, Temp data) static Temp emit_masked_swizzle(isel_context* ctx, Builder& bld, Temp src, unsigned mask) { - if (ctx->options->chip_class >= GFX8) { + if (ctx->options->gfx_level >= GFX8) { unsigned and_mask = mask & 0x1f; unsigned or_mask = (mask >> 5) & 0x1f; unsigned xor_mask = (mask >> 10) & 0x1f; @@ -253,7 +253,8 @@ emit_masked_swizzle(isel_context* ctx, Builder& bld, Temp src, unsigned mask) dpp_ctrl = dpp_row_mirror; } else if (and_mask == 0x1f && !or_mask && xor_mask == 0x7) { dpp_ctrl = dpp_row_half_mirror; - } else if (ctx->options->chip_class >= GFX10 && (and_mask & 0x18) == 0x18 && or_mask < 8 && xor_mask < 8) { + } else if (ctx->options->gfx_level >= GFX10 && (and_mask & 0x18) == 0x18 && or_mask < 8 && + xor_mask < 8) { // DPP8 comes last, as it does not allow several modifiers like `abs` that are available with DPP16 Builder::Result ret = bld.vop1_dpp8(aco_opcode::v_mov_b32, bld.def(v1), src); for (unsigned i = 0; i < 8; i++) { @@ -886,7 +887,7 @@ emit_vop2_instruction(isel_context* ctx, nir_alu_instr* instr, aco_opcode opc, T } } - if (flush_denorms && ctx->program->chip_class < GFX9) { + if (flush_denorms && ctx->program->gfx_level < GFX9) { assert(dst.size() == 1); Temp tmp = bld.vop2(opc, bld.def(v1), op[0], op[1]); bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand::c32(0x3f800000u), tmp); @@ -941,7 +942,7 @@ emit_vop3a_instruction(isel_context* ctx, nir_alu_instr* instr, aco_opcode op, T Builder bld(ctx->program, ctx->block); bld.is_precise = instr->exact; - if (flush_denorms && ctx->program->chip_class < GFX9) { + if (flush_denorms && ctx->program->gfx_level < GFX9) { Temp tmp; if (num_sources == 3) tmp = bld.vop3(op, bld.def(dst.regClass()), src[0], src[1], src[2]); @@ -1242,7 +1243,7 @@ emit_log2(isel_context* ctx, Builder& bld, Definition dst, Temp val) Temp emit_trunc_f64(isel_context* ctx, Builder& bld, Definition dst, Temp val) { - if (ctx->options->chip_class >= GFX7) + if (ctx->options->gfx_level >= GFX7) return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val); /* GFX6 doesn't support V_TRUNC_F64, lower it. */ @@ -1293,7 +1294,7 @@ emit_trunc_f64(isel_context* ctx, Builder& bld, Definition dst, Temp val) Temp emit_floor_f64(isel_context* ctx, Builder& bld, Definition dst, Temp val) { - if (ctx->options->chip_class >= GFX7) + if (ctx->options->gfx_level >= GFX7) return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val); /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually @@ -1327,14 +1328,14 @@ emit_floor_f64(isel_context* ctx, Builder& bld, Definition dst, Temp val) Temp uadd32_sat(Builder& bld, Definition dst, Temp src0, Temp src1) { - if (bld.program->chip_class < GFX8) { + if (bld.program->gfx_level < GFX8) { Builder::Result add = bld.vadd32(bld.def(v1), src0, src1, true); return bld.vop2_e64(aco_opcode::v_cndmask_b32, dst, add.def(0).getTemp(), Operand::c32(-1), add.def(1).getTemp()); } Builder::Result add(NULL); - if (bld.program->chip_class >= GFX9) { + if (bld.program->gfx_level >= GFX9) { add = bld.vop2_e64(aco_opcode::v_add_u32, dst, src0, src1); } else { add = bld.vop2_e64(aco_opcode::v_add_co_u32, dst, bld.def(bld.lm), src0, src1); @@ -1378,7 +1379,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) ctx->block->instructions.emplace_back(std::move(vec)); ctx->allocated_vec.emplace(dst.id(), elems); } else { - bool use_s_pack = ctx->program->chip_class >= GFX9; + bool use_s_pack = ctx->program->gfx_level >= GFX9; Temp mask = bld.copy(bld.def(s1), Operand::c32((1u << instr->dest.dest.ssa.bit_size) - 1)); std::array<Temp, NIR_MAX_VEC_COMPONENTS> packed; @@ -1498,7 +1499,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand::c32(63u)); Temp neqz; - if (ctx->program->chip_class >= GFX8) + if (ctx->program->gfx_level >= GFX8) neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand::zero()); else neqz = @@ -1522,7 +1523,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_imax: { - if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) { + if (dst.regClass() == v2b && ctx->program->gfx_level >= GFX10) { emit_vop3a_instruction(ctx, instr, aco_opcode::v_max_i16_e64, dst); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i16, dst, true); @@ -1538,7 +1539,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_umax: { - if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) { + if (dst.regClass() == v2b && ctx->program->gfx_level >= GFX10) { emit_vop3a_instruction(ctx, instr, aco_opcode::v_max_u16_e64, dst); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u16, dst, true); @@ -1554,7 +1555,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_imin: { - if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) { + if (dst.regClass() == v2b && ctx->program->gfx_level >= GFX10) { emit_vop3a_instruction(ctx, instr, aco_opcode::v_min_i16_e64, dst); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i16, dst, true); @@ -1570,7 +1571,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_umin: { - if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) { + if (dst.regClass() == v2b && ctx->program->gfx_level >= GFX10) { emit_vop3a_instruction(ctx, instr, aco_opcode::v_min_u16_e64, dst); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u16, dst, true); @@ -1634,7 +1635,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_ushr: { - if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) { + if (dst.regClass() == v2b && ctx->program->gfx_level >= GFX10) { emit_vop3a_instruction(ctx, instr, aco_opcode::v_lshrrev_b16_e64, dst, false, 2, true); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b16, dst, false, true); @@ -1642,7 +1643,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_lshrrev_b16, dst, true); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true); - } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) { + } else if (dst.regClass() == v2 && ctx->program->gfx_level >= GFX8) { bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst), get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0])); } else if (dst.regClass() == v2) { @@ -1657,7 +1658,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_ishl: { - if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) { + if (dst.regClass() == v2b && ctx->program->gfx_level >= GFX10) { emit_vop3a_instruction(ctx, instr, aco_opcode::v_lshlrev_b16_e64, dst, false, 2, true); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b16, dst, false, true); @@ -1666,7 +1667,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true, false, false, 2); - } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) { + } else if (dst.regClass() == v2 && ctx->program->gfx_level >= GFX8) { bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst), get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0])); } else if (dst.regClass() == v2) { @@ -1681,7 +1682,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_ishr: { - if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) { + if (dst.regClass() == v2b && ctx->program->gfx_level >= GFX10) { emit_vop3a_instruction(ctx, instr, aco_opcode::v_ashrrev_i16_e64, dst, false, 2, true); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i16, dst, false, true); @@ -1689,7 +1690,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_ashrrev_i16, dst, true); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true); - } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) { + } else if (dst.regClass() == v2 && ctx->program->gfx_level >= GFX8) { bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst), get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0])); } else if (dst.regClass() == v2) { @@ -1780,10 +1781,10 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) if (dst.regClass() == s1) { emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true); break; - } else if (dst.bytes() <= 2 && ctx->program->chip_class >= GFX10) { + } else if (dst.bytes() <= 2 && ctx->program->gfx_level >= GFX10) { emit_vop3a_instruction(ctx, instr, aco_opcode::v_add_u16_e64, dst); break; - } else if (dst.bytes() <= 2 && ctx->program->chip_class >= GFX8) { + } else if (dst.bytes() <= 2 && ctx->program->gfx_level >= GFX8) { emit_vop2_instruction(ctx, instr, aco_opcode::v_add_u16, dst, true); break; } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { @@ -1840,7 +1841,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } else if (dst.regClass() == v2b) { Instruction* add_instr; - if (ctx->program->chip_class >= GFX10) { + if (ctx->program->gfx_level >= GFX10) { add_instr = bld.vop3(aco_opcode::v_add_u16_e64, Definition(dst), src0, src1).instr; } else { if (src1.type() == RegType::sgpr) @@ -1885,7 +1886,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) Temp carry0 = bld.vadd32(Definition(no_sat0), src00, src10, true).def(1).getTemp(); Temp carry1; - if (ctx->program->chip_class >= GFX8) { + if (ctx->program->gfx_level >= GFX8) { carry1 = bld.tmp(bld.lm); bld.vop2_e64(aco_opcode::v_addc_co_u32, Definition(dst1), Definition(carry1), as_vgpr(ctx, src01), as_vgpr(ctx, src11), carry0) @@ -1995,11 +1996,11 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) bld.vsub32(Definition(dst), src0, src1); break; } else if (dst.bytes() <= 2) { - if (ctx->program->chip_class >= GFX10) + if (ctx->program->gfx_level >= GFX10) bld.vop3(aco_opcode::v_sub_u16_e64, Definition(dst), src0, src1); else if (src1.type() == RegType::sgpr) bld.vop2(aco_opcode::v_subrev_u16, Definition(dst), src1, as_vgpr(ctx, src0)); - else if (ctx->program->chip_class >= GFX8) + else if (ctx->program->gfx_level >= GFX8) bld.vop2(aco_opcode::v_sub_u16, Definition(dst), src0, as_vgpr(ctx, src1)); else bld.vsub32(Definition(dst), src0, src1); @@ -2068,9 +2069,9 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_imul: { - if (dst.bytes() <= 2 && ctx->program->chip_class >= GFX10) { + if (dst.bytes() <= 2 && ctx->program->gfx_level >= GFX10) { emit_vop3a_instruction(ctx, instr, aco_opcode::v_mul_lo_u16_e64, dst); - } else if (dst.bytes() <= 2 && ctx->program->chip_class >= GFX8) { + } else if (dst.bytes() <= 2 && ctx->program->gfx_level >= GFX8) { emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_lo_u16, dst, true); } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_mul_lo_u16, dst); @@ -2099,7 +2100,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_umul_high: { - if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) { + if (dst.regClass() == s1 && ctx->options->gfx_level >= GFX9) { emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_hi_u32, dst, false); } else if (dst.bytes() == 4) { uint32_t src0_ub = get_alu_src_ub(ctx, instr, 0); @@ -2122,7 +2123,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) case nir_op_imul_high: { if (dst.regClass() == v1) { emit_vop3a_instruction(ctx, instr, aco_opcode::v_mul_hi_i32, dst); - } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) { + } else if (dst.regClass() == s1 && ctx->options->gfx_level >= GFX9) { emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_hi_i32, dst, false); } else if (dst.regClass() == s1) { Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]), @@ -2503,7 +2504,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) } else if (dst.regClass() == v1) { emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst); } else if (dst.regClass() == v2) { - if (ctx->options->chip_class >= GFX7) { + if (ctx->options->gfx_level >= GFX7) { emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst); } else { /* GFX6 doesn't support V_CEIL_F64, lower it. */ @@ -2548,7 +2549,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) } else if (dst.regClass() == v1) { emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst); } else if (dst.regClass() == v2) { - if (ctx->options->chip_class >= GFX7) { + if (ctx->options->gfx_level >= GFX7) { emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst); } else { /* GFX6 doesn't support V_RNDNE_F64, lower it. */ @@ -2605,7 +2606,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, src); /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */ - if (ctx->options->chip_class < GFX9) + if (ctx->options->gfx_level < GFX9) tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp); aco_opcode opcode = @@ -2658,7 +2659,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) case nir_op_fsign: { Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0])); if (dst.regClass() == v2b) { - assert(ctx->program->chip_class >= GFX9); + assert(ctx->program->gfx_level >= GFX9); /* replace negative zero with positive zero */ src = bld.vop2(aco_opcode::v_add_f16, bld.def(v2b), Operand::zero(), src); src = @@ -2705,7 +2706,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) src = bld.vop1(aco_opcode::v_cvt_f32_f64, bld.def(v1), src); if (ctx->block->fp_mode.round16_64 == fp_round_tz) bld.vop1(aco_opcode::v_cvt_f16_f32, Definition(dst), src); - else if (ctx->program->chip_class == GFX8 || ctx->program->chip_class == GFX9) + else if (ctx->program->gfx_level == GFX8 || ctx->program->gfx_level == GFX9) bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32_e64, Definition(dst), src, Operand::zero()); else bld.vop2(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src, as_vgpr(ctx, src)); @@ -2734,7 +2735,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) const unsigned input_size = instr->src[0].src.ssa->bit_size; if (input_size <= 16) { /* Expand integer to the size expected by the uint→float converter used below */ - unsigned target_size = (ctx->program->chip_class >= GFX8 ? 16 : 32); + unsigned target_size = (ctx->program->gfx_level >= GFX8 ? 16 : 32); if (input_size != target_size) { src = convert_int(ctx, bld, src, input_size, target_size, true); } @@ -2747,7 +2748,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) src = convert_int(ctx, bld, src, 64, 32, false); } - if (ctx->program->chip_class >= GFX8 && input_size <= 16) { + if (ctx->program->gfx_level >= GFX8 && input_size <= 16) { bld.vop1(aco_opcode::v_cvt_f16_i16, Definition(dst), src); } else { /* Convert to f32 and then down to f16. This is needed to handle @@ -2814,7 +2815,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) const unsigned input_size = instr->src[0].src.ssa->bit_size; if (input_size <= 16) { /* Expand integer to the size expected by the uint→float converter used below */ - unsigned target_size = (ctx->program->chip_class >= GFX8 ? 16 : 32); + unsigned target_size = (ctx->program->gfx_level >= GFX8 ? 16 : 32); if (input_size != target_size) { src = convert_int(ctx, bld, src, input_size, target_size, false); } @@ -2827,7 +2828,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) src = convert_int(ctx, bld, src, 64, 32, false); } - if (ctx->program->chip_class >= GFX8) { + if (ctx->program->gfx_level >= GFX8) { /* float16 has a range of [0, 65519]. Converting from larger * inputs is UB, so we just need to consider the lower 16 bits */ bld.vop1(aco_opcode::v_cvt_f16_u16, Definition(dst), src); @@ -2884,7 +2885,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) case nir_op_f2i8: case nir_op_f2i16: { if (instr->src[0].src.ssa->bit_size == 16) { - if (ctx->program->chip_class >= GFX8) { + if (ctx->program->gfx_level >= GFX8) { emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_i16_f16, dst); } else { /* GFX7 and earlier do not support direct f16⟷i16 conversions */ @@ -2907,7 +2908,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) case nir_op_f2u8: case nir_op_f2u16: { if (instr->src[0].src.ssa->bit_size == 16) { - if (ctx->program->chip_class >= GFX8) { + if (ctx->program->gfx_level >= GFX8) { emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u16_f16, dst); } else { /* GFX7 and earlier do not support direct f16⟷u16 conversions */ @@ -2982,7 +2983,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) Temp new_exponent = bld.tmp(v1); Temp borrow = bld.vsub32(Definition(new_exponent), Operand::c32(63u), exponent, true).def(1).getTemp(); - if (ctx->program->chip_class >= GFX8) + if (ctx->program->gfx_level >= GFX8) mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa); else mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent); @@ -3078,7 +3079,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) Temp new_exponent = bld.tmp(v1); Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand::c32(24u), true).def(1).getTemp(); - if (ctx->program->chip_class >= GFX8) + if (ctx->program->gfx_level >= GFX8) mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa); else mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent); @@ -3267,7 +3268,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) } else { assert(src.regClass() == s1 || src.regClass() == s2); Temp tmp; - if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) { + if (src.regClass() == s2 && ctx->program->gfx_level <= GFX7) { tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand::zero(), src) .def(1) @@ -3338,7 +3339,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) case nir_op_pack_32_4x8: bld.copy(Definition(dst), get_alu_src(ctx, instr->src[0], 4)); break; case nir_op_pack_half_2x16_split: { if (dst.regClass() == v1) { - if (ctx->program->chip_class == GFX8 || ctx->program->chip_class == GFX9) + if (ctx->program->gfx_level == GFX8 || ctx->program->gfx_level == GFX9) emit_vop3a_instruction(ctx, instr, aco_opcode::v_cvt_pkrtz_f16_f32_e64, dst); else emit_vop2_instruction(ctx, instr, aco_opcode::v_cvt_pkrtz_f16_f32, dst, false); @@ -3409,7 +3410,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v2b), src); Temp f32, cmp_res; - if (ctx->program->chip_class >= GFX8) { + if (ctx->program->gfx_level >= GFX8) { Temp mask = bld.copy( bld.def(s1), Operand::c32(0x36Fu)); /* value is NOT negative/positive denormal value */ cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.def(bld.lm), f16, mask); @@ -3665,7 +3666,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_comparison( ctx, instr, dst, aco_opcode::v_cmp_eq_i16, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32, - ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes); + ctx->program->gfx_level >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes); break; } case nir_op_ine: { @@ -3675,7 +3676,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_comparison( ctx, instr, dst, aco_opcode::v_cmp_lg_i16, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32, - ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes); + ctx->program->gfx_level >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes); break; } case nir_op_ult: { @@ -3719,7 +3720,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) } Temp tmp; - if (ctx->program->chip_class >= GFX8) { + if (ctx->program->gfx_level >= GFX8) { Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1); tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2); } else { @@ -4073,7 +4074,7 @@ Operand load_lds_size_m0(Builder& bld) { /* m0 does not need to be initialized on GFX9+ */ - if (bld.program->chip_class >= GFX9) + if (bld.program->gfx_level >= GFX9) return Operand(s1); return bld.m0((Temp)bld.copy(bld.def(s1, m0), Operand::c32(0xffffffffu))); @@ -4087,8 +4088,8 @@ lds_load_callback(Builder& bld, const LoadEmitInfo& info, Temp offset, unsigned Operand m = load_lds_size_m0(bld); - bool large_ds_read = bld.program->chip_class >= GFX7; - bool usable_read2 = bld.program->chip_class >= GFX7; + bool large_ds_read = bld.program->gfx_level >= GFX7; + bool usable_read2 = bld.program->gfx_level >= GFX7; bool read2 = false; unsigned size = 0; @@ -4115,10 +4116,10 @@ lds_load_callback(Builder& bld, const LoadEmitInfo& info, Temp offset, unsigned op = aco_opcode::ds_read_b32; } else if (bytes_needed >= 2 && align % 2 == 0) { size = 2; - op = bld.program->chip_class >= GFX9 ? aco_opcode::ds_read_u16_d16 : aco_opcode::ds_read_u16; + op = bld.program->gfx_level >= GFX9 ? aco_opcode::ds_read_u16_d16 : aco_opcode::ds_read_u16; } else { size = 1; - op = bld.program->chip_class >= GFX9 ? aco_opcode::ds_read_u8_d16 : aco_opcode::ds_read_u8; + op = bld.program->gfx_level >= GFX9 ? aco_opcode::ds_read_u8_d16 : aco_opcode::ds_read_u8; } unsigned const_offset_unit = read2 ? size / 2u : 1u; @@ -4201,7 +4202,7 @@ smem_load_callback(Builder& bld, const LoadEmitInfo& info, Temp offset, unsigned Temp val = dst_hint.id() && dst_hint.regClass() == rc ? dst_hint : bld.tmp(rc); load->definitions[0] = Definition(val); load->glc = info.glc; - load->dlc = info.glc && (bld.program->chip_class == GFX10 || bld.program->chip_class == GFX10_3); + load->dlc = info.glc && (bld.program->gfx_level == GFX10 || bld.program->gfx_level == GFX10_3); load->sync = info.sync; bld.insert(std::move(load)); return val; @@ -4236,7 +4237,7 @@ mubuf_load_callback(Builder& bld, const LoadEmitInfo& info, Temp offset, unsigne } else if (bytes_needed <= 8) { bytes_size = 8; op = aco_opcode::buffer_load_dwordx2; - } else if (bytes_needed <= 12 && bld.program->chip_class > GFX6) { + } else if (bytes_needed <= 12 && bld.program->gfx_level > GFX6) { bytes_size = 12; op = aco_opcode::buffer_load_dwordx3; } else { @@ -4250,7 +4251,7 @@ mubuf_load_callback(Builder& bld, const LoadEmitInfo& info, Temp offset, unsigne mubuf->offen = (offset.type() == RegType::vgpr); mubuf->glc = info.glc; mubuf->dlc = - info.glc && (bld.program->chip_class == GFX10 || bld.program->chip_class == GFX10_3); + info.glc && (bld.program->gfx_level == GFX10 || bld.program->gfx_level == GFX10_3); mubuf->slc = info.slc; mubuf->sync = info.sync; mubuf->offset = const_offset; @@ -4310,10 +4311,10 @@ lower_global_address(Builder& bld, uint32_t offset_in, Temp* address_inout, uint64_t max_const_offset_plus_one = 1; /* GFX7/8/9: FLAT loads do not support constant offsets */ - if (bld.program->chip_class >= GFX10) + if (bld.program->gfx_level >= GFX10) max_const_offset_plus_one = 2048; /* GLOBAL has a 11-bit signed offset field (12 bits if signed) */ - else if (bld.program->chip_class == GFX6 || bld.program->chip_class == GFX9) + else if (bld.program->gfx_level == GFX6 || bld.program->gfx_level == GFX9) max_const_offset_plus_one = 4096; /* MUBUF/GLOBAL has a 12-bit unsigned offset field (13 bits if signed for GLOBAL) */ uint64_t excess_offset = const_offset - (const_offset % max_const_offset_plus_one); @@ -4340,14 +4341,14 @@ lower_global_address(Builder& bld, uint32_t offset_in, Temp* address_inout, } } - if (bld.program->chip_class == GFX6) { + if (bld.program->gfx_level == GFX6) { /* GFX6 (MUBUF): (SGPR address, SGPR offset) or (VGPR address, SGPR offset) */ if (offset.type() != RegType::sgpr) { address = add64_32(bld, address, offset); offset = Temp(); } offset = offset.id() ? offset : bld.copy(bld.def(s1), Operand::zero()); - } else if (bld.program->chip_class <= GFX8) { + } else if (bld.program->gfx_level <= GFX8) { /* GFX7,8 (FLAT): VGPR address */ if (offset.id()) { address = add64_32(bld, address, offset); @@ -4383,8 +4384,8 @@ global_load_callback(Builder& bld, const LoadEmitInfo& info, Temp offset, unsign lower_global_address(bld, 0, &addr, &const_offset, &offset); unsigned bytes_size = 0; - bool use_mubuf = bld.program->chip_class == GFX6; - bool global = bld.program->chip_class >= GFX9; + bool use_mubuf = bld.program->gfx_level == GFX6; + bool global = bld.program->gfx_level >= GFX9; aco_opcode op; if (bytes_needed == 1 || align_ % 2u) { bytes_size = 1; @@ -4445,7 +4446,7 @@ global_load_callback(Builder& bld, const LoadEmitInfo& info, Temp offset, unsign } flat->glc = info.glc; flat->dlc = - info.glc && (bld.program->chip_class == GFX10 || bld.program->chip_class == GFX10_3); + info.glc && (bld.program->gfx_level == GFX10 || bld.program->gfx_level == GFX10_3); flat->sync = info.sync; assert(global || !const_offset); flat->offset = const_offset; @@ -4597,8 +4598,8 @@ store_lds(isel_context* ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmas assert(util_is_power_of_two_nonzero(elem_size_bytes) && elem_size_bytes <= 8); Builder bld(ctx->program, ctx->block); - bool large_ds_write = ctx->options->chip_class >= GFX7; - bool usable_write2 = ctx->options->chip_class >= GFX7; + bool large_ds_write = ctx->options->gfx_level >= GFX7; + bool usable_write2 = ctx->options->gfx_level >= GFX7; unsigned write_count = 0; Temp write_datas[32]; @@ -4752,7 +4753,7 @@ split_buffer_store(isel_context* ctx, nir_intrinsic_instr* instr, bool smem, Reg byte = byte > 4 ? byte & ~0x3 : MIN2(byte, 2); /* SMEM and GFX6 VMEM can't emit 12-byte stores */ - if ((ctx->program->chip_class == GFX6 || smem) && byte == 12) + if ((ctx->program->gfx_level == GFX6 || smem) && byte == 12) byte = 8; /* dword or larger stores have to be dword-aligned */ @@ -4845,7 +4846,7 @@ emit_single_mubuf_store(isel_context* ctx, Temp descriptor, Temp voffset, Temp s bool slc = false, bool swizzled = false) { assert(vdata.id()); - assert(vdata.size() != 3 || ctx->program->chip_class != GFX6); + assert(vdata.size() != 3 || ctx->program->gfx_level != GFX6); assert(vdata.size() >= 1 && vdata.size() <= 4); Builder bld(ctx->program, ctx->block); @@ -4854,7 +4855,7 @@ emit_single_mubuf_store(isel_context* ctx, Temp descriptor, Temp voffset, Temp s Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1); Operand soffset_op = soffset.id() ? Operand(soffset) : Operand::zero(); - bool glc = ctx->program->chip_class < GFX11; + bool glc = ctx->program->gfx_level < GFX11; Builder::Result r = bld.mubuf(op, Operand(descriptor), voffset_op, soffset_op, Operand(vdata), const_offset, /* offen */ !voffset_op.isUndefined(), /* swizzled */ swizzled, @@ -5033,7 +5034,7 @@ emit_interp_instr(isel_context* ctx, unsigned idx, unsigned component, Temp src, if (dst.regClass() == v2b) { if (ctx->program->dev.has_16bank_lds) { - assert(ctx->options->chip_class <= GFX8); + assert(ctx->options->gfx_level <= GFX8); Builder::Result interp_p1 = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand::c32(2u) /* P0 */, bld.m0(prim_mask), idx, component); @@ -5044,7 +5045,7 @@ emit_interp_instr(isel_context* ctx, unsigned idx, unsigned component, Temp src, } else { aco_opcode interp_p2_op = aco_opcode::v_interp_p2_f16; - if (ctx->options->chip_class == GFX8) + if (ctx->options->gfx_level == GFX8) interp_p2_op = aco_opcode::v_interp_p2_legacy_f16; Builder::Result interp_p1 = bld.vintrp(aco_opcode::v_interp_p1ll_f16, bld.def(v1), coord1, @@ -5159,7 +5160,7 @@ check_vertex_fetch_size(isel_context* ctx, const ac_data_format_info* vtx_info, * also if the VBO offset is aligned to a scalar (eg. stride is 8 and VBO * offset is 2 for R16G16B16A16_SNORM). */ - return (ctx->options->chip_class >= GFX7 && ctx->options->chip_class <= GFX9) || + return (ctx->options->gfx_level >= GFX7 && ctx->options->gfx_level <= GFX9) || (offset % vertex_byte_size == 0 && MAX2(binding_align, 1) % vertex_byte_size == 0); } @@ -5330,7 +5331,7 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr) get_fetch_data_format(ctx, vtx_info, fetch_offset, &fetch_component, vtx_info->num_channels - channel_start, binding_align); } else { - if (fetch_component == 3 && ctx->options->chip_class == GFX6) { + if (fetch_component == 3 && ctx->options->gfx_level == GFX6) { /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */ fetch_component = 4; expanded = true; @@ -5381,8 +5382,8 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr) } break; case 12: - assert(ctx->options->chip_class >= GFX7 || - (!use_mubuf && ctx->options->chip_class == GFX6)); + assert(ctx->options->gfx_level >= GFX7 || + (!use_mubuf && ctx->options->gfx_level == GFX6)); opcode = use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz; break; @@ -5565,14 +5566,14 @@ load_buffer(isel_context* ctx, unsigned num_components, unsigned component_size, Builder bld(ctx->program, ctx->block); bool use_smem = - dst.type() != RegType::vgpr && (!glc || ctx->options->chip_class >= GFX8) && allow_smem; + dst.type() != RegType::vgpr && (!glc || ctx->options->gfx_level >= GFX8) && allow_smem; if (use_smem) offset = bld.as_uniform(offset); else { /* GFX6-7 are affected by a hw bug that prevents address clamping to * work correctly when the SGPR offset is used. */ - if (offset.type() == RegType::sgpr && ctx->options->chip_class < GFX8) + if (offset.type() == RegType::sgpr && ctx->options->gfx_level < GFX8) offset = as_vgpr(ctx, offset); } @@ -5710,10 +5711,10 @@ visit_load_constant(isel_context* ctx, nir_intrinsic_instr* instr) uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (ctx->options->chip_class >= GFX10) { + if (ctx->options->gfx_level >= GFX10) { desc_type |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | - S_008F0C_RESOURCE_LEVEL(ctx->options->chip_class < GFX11); + S_008F0C_RESOURCE_LEVEL(ctx->options->gfx_level < GFX11); } else { desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); @@ -5744,7 +5745,7 @@ should_declare_array(isel_context* ctx, enum glsl_sampler_dim sampler_dim, bool { if (sampler_dim == GLSL_SAMPLER_DIM_BUF) return false; - ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array); + ac_image_dim dim = ac_get_sampler_dim(ctx->options->gfx_level, sampler_dim, is_array); return dim == ac_image_cube || dim == ac_image_1darray || dim == ac_image_2darray || dim == ac_image_2darraymsaa; } @@ -5772,8 +5773,8 @@ emit_mimg(Builder& bld, aco_opcode op, Definition dst, Temp rsrc, Operand samp, std::vector<Temp> coords, unsigned wqm_mask = 0, Operand vdata = Operand(v1)) { /* Limit NSA instructions to 3 dwords on GFX10 to avoid stability issues. */ - unsigned max_nsa_size = bld.program->chip_class >= GFX10_3 ? 13 : 5; - bool use_nsa = bld.program->chip_class >= GFX10 && coords.size() <= max_nsa_size; + unsigned max_nsa_size = bld.program->gfx_level >= GFX10_3 ? 13 : 5; + bool use_nsa = bld.program->gfx_level >= GFX10 && coords.size() <= max_nsa_size; if (!use_nsa) { Temp coord = coords[0]; @@ -5871,7 +5872,7 @@ get_image_coords(isel_context* ctx, const nir_intrinsic_instr* instr) (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS); assert(!add_frag_pos && "Input attachments should be lowered."); bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS); - bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D; + bool gfx9_1d = ctx->options->gfx_level == GFX9 && dim == GLSL_SAMPLER_DIM_1D; int count = image_type_to_components_count(dim, is_array); std::vector<Temp> coords(count); Builder bld(ctx->program, ctx->block); @@ -5896,7 +5897,7 @@ get_image_coords(isel_context* ctx, const nir_intrinsic_instr* instr) * ignores BASE_ARRAY if the target is 3D. The workaround is to read * BASE_ARRAY and set it as the 3rd address operand for all 2D images. */ - assert(ctx->options->chip_class == GFX9); + assert(ctx->options->gfx_level == GFX9); Temp rsrc = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa)); Temp rsrc_word5 = emit_extract_vector(ctx, rsrc, 5, v1); /* Extract the BASE_ARRAY field [0:12] from the descriptor. */ @@ -6027,7 +6028,7 @@ visit_image_load(isel_context* ctx, nir_intrinsic_instr* instr) load->idxen = true; load->glc = access & (ACCESS_VOLATILE | ACCESS_COHERENT); load->dlc = - load->glc && (ctx->options->chip_class == GFX10 || ctx->options->chip_class == GFX10_3); + load->glc && (ctx->options->gfx_level == GFX10 || ctx->options->gfx_level == GFX10_3); load->sync = sync; load->tfe = is_sparse; if (load->tfe) @@ -6044,8 +6045,8 @@ visit_image_load(isel_context* ctx, nir_intrinsic_instr* instr) emit_mimg(bld, opcode, Definition(tmp), resource, Operand(s4), coords, 0, vdata); load->glc = access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0; load->dlc = - load->glc && (ctx->options->chip_class == GFX10 || ctx->options->chip_class == GFX10_3); - load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array); + load->glc && (ctx->options->gfx_level == GFX10 || ctx->options->gfx_level == GFX10_3); + load->dim = ac_get_image_dim(ctx->options->gfx_level, dim, is_array); load->d16 = d16; load->dmask = dmask; load->unrm = true; @@ -6084,9 +6085,9 @@ visit_image_store(isel_context* ctx, nir_intrinsic_instr* instr) memory_sync_info sync = get_memory_sync_info(instr, storage_image, 0); unsigned access = nir_intrinsic_access(instr); - bool glc = ctx->options->chip_class == GFX6 || + bool glc = ctx->options->gfx_level == GFX6 || ((access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE)) && - ctx->program->chip_class < GFX11); + ctx->program->gfx_level < GFX11); if (dim == GLSL_SAMPLER_DIM_BUF) { Temp rsrc = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa)); @@ -6171,7 +6172,7 @@ visit_image_store(isel_context* ctx, nir_intrinsic_instr* instr) emit_mimg(bld, opcode, Definition(), resource, Operand(s4), coords, 0, Operand(data)); store->glc = glc; store->dlc = false; - store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array); + store->dim = ac_get_image_dim(ctx->options->gfx_level, dim, is_array); store->d16 = d16; store->dmask = dmask; store->unrm = true; @@ -6272,7 +6273,7 @@ visit_image_atomic(isel_context* ctx, nir_intrinsic_instr* instr) if (dim == GLSL_SAMPLER_DIM_BUF) { Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1); Temp resource = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa)); - // assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet + // assert(ctx->options->gfx_level < GFX9 && "GFX9 stride size workaround not yet // implemented."); aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>( is_64bit ? buf_op64 : buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)}; @@ -6305,7 +6306,7 @@ visit_image_atomic(isel_context* ctx, nir_intrinsic_instr* instr) emit_mimg(bld, image_op, def, resource, Operand(s4), coords, 0, Operand(data)); mimg->glc = return_previous; mimg->dlc = false; /* Not needed for atomics */ - mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array); + mimg->dim = ac_get_image_dim(ctx->options->gfx_level, dim, is_array); mimg->dmask = (1 << data.size()) - 1; mimg->unrm = true; mimg->da = should_declare_array(ctx, dim, is_array); @@ -6320,7 +6321,7 @@ visit_image_atomic(isel_context* ctx, nir_intrinsic_instr* instr) void get_buffer_size(isel_context* ctx, Temp desc, Temp dst) { - if (ctx->options->chip_class == GFX8) { + if (ctx->options->gfx_level == GFX8) { /* we only have to divide by 1, 2, 4, 8, 12 or 16 */ Builder bld(ctx->program, ctx->block); @@ -6374,11 +6375,11 @@ visit_image_size(isel_context* ctx, nir_intrinsic_instr* instr) MIMG_instruction* mimg = emit_mimg(bld, aco_opcode::image_get_resinfo, Definition(dst), resource, Operand(s4), lod); uint8_t& dmask = mimg->dmask; - mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array); + mimg->dim = ac_get_image_dim(ctx->options->gfx_level, dim, is_array); mimg->dmask = (1 << instr->dest.ssa.num_components) - 1; mimg->da = is_array; - if (ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D && is_array) { + if (ctx->options->gfx_level == GFX9 && dim == GLSL_SAMPLER_DIM_1D && is_array) { assert(instr->dest.ssa.num_components == 2); dmask = 0x5; } @@ -6457,7 +6458,7 @@ visit_store_ssbo(isel_context* ctx, nir_intrinsic_instr* instr) memory_sync_info sync = get_memory_sync_info(instr, storage_buffer, 0); bool glc = (nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE)) && - ctx->program->chip_class < GFX11; + ctx->program->gfx_level < GFX11; unsigned write_count = 0; Temp write_datas[32]; @@ -6468,7 +6469,7 @@ visit_store_ssbo(isel_context* ctx, nir_intrinsic_instr* instr) /* GFX6-7 are affected by a hw bug that prevents address clamping to work * correctly when the SGPR offset is used. */ - if (offset.type() == RegType::sgpr && ctx->options->chip_class < GFX8) + if (offset.type() == RegType::sgpr && ctx->options->gfx_level < GFX8) offset = as_vgpr(ctx, offset); for (unsigned i = 0; i < write_count; i++) { @@ -6637,10 +6638,10 @@ visit_load_global(isel_context* ctx, nir_intrinsic_instr* instr) * it's safe to use SMEM */ bool can_use_smem = (nir_intrinsic_access(instr) & ACCESS_NON_WRITEABLE) && byte_align_for_smem_mubuf; - if (info.dst.type() == RegType::vgpr || (info.glc && ctx->options->chip_class < GFX8) || + if (info.dst.type() == RegType::vgpr || (info.glc && ctx->options->gfx_level < GFX8) || !can_use_smem) { EmitLoadParameters params = global_load_params; - params.byte_align_loads = ctx->options->chip_class > GFX6 || byte_align_for_smem_mubuf; + params.byte_align_loads = ctx->options->gfx_level > GFX6 || byte_align_for_smem_mubuf; emit_load(ctx, bld, info, params); } else { info.offset = Operand(bld.as_uniform(info.offset)); @@ -6659,7 +6660,7 @@ visit_store_global(isel_context* ctx, nir_intrinsic_instr* instr) memory_sync_info sync = get_memory_sync_info(instr, storage_buffer, 0); bool glc = (nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE)) && - ctx->program->chip_class < GFX11; + ctx->program->gfx_level < GFX11; unsigned write_count = 0; Temp write_datas[32]; @@ -6677,8 +6678,8 @@ visit_store_global(isel_context* ctx, nir_intrinsic_instr* instr) Temp write_offset = offset; lower_global_address(bld, offsets[i], &write_address, &write_const_offset, &write_offset); - if (ctx->options->chip_class >= GFX7) { - bool global = ctx->options->chip_class >= GFX9; + if (ctx->options->gfx_level >= GFX7) { + bool global = ctx->options->gfx_level >= GFX9; aco_opcode op; switch (write_datas[i].bytes()) { case 1: op = global ? aco_opcode::global_store_byte : aco_opcode::flat_store_byte; break; @@ -6717,7 +6718,7 @@ visit_store_global(isel_context* ctx, nir_intrinsic_instr* instr) ctx->program->needs_exact = true; ctx->block->instructions.emplace_back(std::move(flat)); } else { - assert(ctx->options->chip_class == GFX6); + assert(ctx->options->gfx_level == GFX6); aco_opcode op = get_buffer_store_op(write_datas[i].bytes()); @@ -6763,8 +6764,8 @@ visit_global_atomic(isel_context* ctx, nir_intrinsic_instr* instr) parse_global(ctx, instr, &addr, &const_offset, &offset); lower_global_address(bld, 0, &addr, &const_offset, &offset); - if (ctx->options->chip_class >= GFX7) { - bool global = ctx->options->chip_class >= GFX9; + if (ctx->options->gfx_level >= GFX7) { + bool global = ctx->options->gfx_level >= GFX9; switch (instr->intrinsic) { case nir_intrinsic_global_atomic_add_amd: op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add; @@ -6843,7 +6844,7 @@ visit_global_atomic(isel_context* ctx, nir_intrinsic_instr* instr) ctx->program->needs_exact = true; ctx->block->instructions.emplace_back(std::move(flat)); } else { - assert(ctx->options->chip_class == GFX6); + assert(ctx->options->gfx_level == GFX6); switch (instr->intrinsic) { case nir_intrinsic_global_atomic_add_amd: @@ -6962,7 +6963,7 @@ visit_load_buffer(isel_context* ctx, nir_intrinsic_instr* intrin) unsigned const_offset = nir_intrinsic_base(intrin); unsigned elem_size_bytes = intrin->dest.ssa.bit_size / 8u; unsigned num_components = intrin->dest.ssa.num_components; - unsigned swizzle_element_size = swizzled ? (ctx->program->chip_class <= GFX8 ? 4 : 16) : 0; + unsigned swizzle_element_size = swizzled ? (ctx->program->gfx_level <= GFX8 ? 4 : 16) : 0; nir_variable_mode mem_mode = nir_intrinsic_memory_modes(intrin); memory_sync_info sync(aco_storage_mode_from_nir_mem_mode(mem_mode)); @@ -7062,7 +7063,7 @@ emit_scoped_barrier(isel_context* ctx, nir_intrinsic_instr* instr) */ bool shared_storage_used = ctx->stage.hw == HWStage::CS || ctx->stage.hw == HWStage::LS || ctx->stage.hw == HWStage::HS || - (ctx->stage.hw == HWStage::GS && ctx->program->chip_class >= GFX9) || + (ctx->stage.hw == HWStage::GS && ctx->program->gfx_level >= GFX9) || ctx->stage.hw == HWStage::NGG; if (shared_storage_used) @@ -7264,7 +7265,7 @@ visit_access_shared2_amd(isel_context* ctx, nir_intrinsic_instr* instr) Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[is_store].ssa)); Builder bld(ctx->program, ctx->block); - assert(bld.program->chip_class >= GFX7); + assert(bld.program->gfx_level >= GFX7); bool is64bit = (is_store ? instr->src[0].ssa->bit_size : instr->dest.ssa.bit_size) == 64; uint8_t offset0 = nir_intrinsic_offset0(instr); @@ -7329,18 +7330,18 @@ get_scratch_resource(isel_context* ctx) uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) | S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2); - if (ctx->program->chip_class >= GFX10) { + if (ctx->program->gfx_level >= GFX10) { rsrc_conf |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | - S_008F0C_RESOURCE_LEVEL(ctx->program->chip_class < GFX11); - } else if (ctx->program->chip_class <= + S_008F0C_RESOURCE_LEVEL(ctx->program->gfx_level < GFX11); + } else if (ctx->program->gfx_level <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */ rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); } /* older generations need element size = 4 bytes. element size removed in GFX9 */ - if (ctx->program->chip_class <= GFX8) + if (ctx->program->gfx_level <= GFX8) rsrc_conf |= S_008F0C_ELEMENT_SIZE(1); return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand::c32(-1u), @@ -7359,7 +7360,7 @@ visit_load_scratch(isel_context* ctx, nir_intrinsic_instr* instr) instr->dest.ssa.bit_size / 8u, rsrc}; info.align_mul = nir_intrinsic_align_mul(instr); info.align_offset = nir_intrinsic_align_offset(instr); - info.swizzle_component_size = ctx->program->chip_class <= GFX8 ? 4 : 0; + info.swizzle_component_size = ctx->program->gfx_level <= GFX8 ? 4 : 0; info.sync = memory_sync_info(storage_scratch, semantic_private); info.soffset = ctx->program->scratch_offset; emit_load(ctx, bld, info, scratch_load_params); @@ -7379,7 +7380,7 @@ visit_store_scratch(isel_context* ctx, nir_intrinsic_instr* instr) unsigned write_count = 0; Temp write_datas[32]; unsigned offsets[32]; - unsigned swizzle_component_size = ctx->program->chip_class <= GFX8 ? 4 : 16; + unsigned swizzle_component_size = ctx->program->gfx_level <= GFX8 ? 4 : 16; split_buffer_store(ctx, instr, false, RegType::vgpr, data, writemask, swizzle_component_size, &write_count, write_datas, offsets); @@ -7473,7 +7474,7 @@ visit_emit_vertex_with_counter(isel_context* ctx, nir_intrinsic_instr* instr) mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32; mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT; mtbuf->offset = const_offset; - mtbuf->glc = ctx->program->chip_class < GFX11; + mtbuf->glc = ctx->program->gfx_level < GFX11; mtbuf->slc = true; mtbuf->sync = memory_sync_info(storage_vmem_output, semantic_can_reorder); bld.insert(std::move(mtbuf)); @@ -7558,7 +7559,7 @@ emit_boolean_reduce(isel_context* ctx, nir_op op, unsigned cluster_size, Temp sr uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u; - if (ctx->program->chip_class <= GFX7) + if (ctx->program->gfx_level <= GFX7) tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset); else if (ctx->program->wave_size == 64) tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp); @@ -7728,9 +7729,9 @@ emit_addition_uniform_reduce(isel_context* ctx, nir_op op, Definition dst, nir_s bld.v_mul_imm(dst, count, nir_src_as_uint(src)); else bld.sop2(aco_opcode::s_mul_i32, dst, src_tmp, count); - } else if (dst.bytes() <= 2 && ctx->program->chip_class >= GFX10) { + } else if (dst.bytes() <= 2 && ctx->program->gfx_level >= GFX10) { bld.vop3(aco_opcode::v_mul_lo_u16_e64, dst, src_tmp, count); - } else if (dst.bytes() <= 2 && ctx->program->chip_class >= GFX8) { + } else if (dst.bytes() <= 2 && ctx->program->gfx_level >= GFX8) { bld.vop2(aco_opcode::v_mul_lo_u16, dst, src_tmp, count); } else if (dst.getTemp().type() == RegType::vgpr) { bld.vop3(aco_opcode::v_mul_lo_u32, dst, src_tmp, count); @@ -7836,7 +7837,7 @@ emit_reduction_instr(isel_context* ctx, aco_opcode aco_op, ReduceOp op, unsigned defs[num_defs++] = bld.def(bld.lm); /* used internally to save/restore exec */ /* scalar identity temporary */ - bool need_sitmp = (ctx->program->chip_class <= GFX7 || ctx->program->chip_class >= GFX10) && + bool need_sitmp = (ctx->program->gfx_level <= GFX7 || ctx->program->gfx_level >= GFX10) && aco_op != aco_opcode::p_reduce; if (aco_op == aco_opcode::p_exclusive_scan) { need_sitmp |= (op == imin8 || op == imin16 || op == imin32 || op == imin64 || op == imax8 || @@ -7852,9 +7853,9 @@ emit_reduction_instr(isel_context* ctx, aco_opcode aco_op, ReduceOp op, unsigned /* vcc clobber */ bool clobber_vcc = false; - if ((op == iadd32 || op == imul64) && ctx->program->chip_class < GFX9) + if ((op == iadd32 || op == imul64) && ctx->program->gfx_level < GFX9) clobber_vcc = true; - if ((op == iadd8 || op == iadd16) && ctx->program->chip_class < GFX8) + if ((op == iadd8 || op == iadd16) && ctx->program->gfx_level < GFX8) clobber_vcc = true; if (op == iadd64 || op == umin64 || op == umax64 || op == imin64 || op == imax64) clobber_vcc = true; @@ -7890,7 +7891,7 @@ emit_interp_center(isel_context* ctx, Temp dst, Temp bary, Temp pos1, Temp pos2) uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2); /* Build DD X/Y */ - if (ctx->program->chip_class >= GFX8) { + if (ctx->program->gfx_level >= GFX8) { Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0); ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1); ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2); @@ -7913,7 +7914,7 @@ emit_interp_center(isel_context* ctx, Temp dst, Temp bary, Temp pos1, Temp pos2) /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */ aco_opcode mad = - ctx->program->chip_class >= GFX10_3 ? aco_opcode::v_fma_f32 : aco_opcode::v_mad_f32; + ctx->program->gfx_level >= GFX10_3 ? aco_opcode::v_fma_f32 : aco_opcode::v_mad_f32; Temp tmp1 = bld.vop3(mad, bld.def(v1), ddx_1, pos1, p1); Temp tmp2 = bld.vop3(mad, bld.def(v1), ddx_2, pos1, p2); tmp1 = bld.vop3(mad, bld.def(v1), ddy_1, pos2, tmp1); @@ -7990,7 +7991,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) if (const_addr) { sample_pos_offset += const_addr->u32 << 3; offset = Operand::c32(sample_pos_offset); - } else if (ctx->options->chip_class >= GFX9) { + } else if (ctx->options->gfx_level >= GFX9) { offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand::c32(sample_pos_offset)); } else { @@ -8004,11 +8005,11 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off); - } else if (ctx->options->chip_class >= GFX9) { + } else if (ctx->options->gfx_level >= GFX9) { addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand::c32(3u), addr); sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset); - } else if (ctx->options->chip_class >= GFX7) { + } else if (ctx->options->gfx_level >= GFX7) { /* addr += private_segment_buffer + sample_pos_offset */ Temp tmp0 = bld.tmp(s1); Temp tmp1 = bld.tmp(s1); @@ -8030,7 +8031,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) /* sample_pos = flat_load_dwordx2 addr */ sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1)); } else { - assert(ctx->options->chip_class == GFX6); + assert(ctx->options->gfx_level == GFX6); uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); @@ -8202,7 +8203,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) } case nir_intrinsic_load_local_invocation_id: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - if (ctx->options->chip_class >= GFX11) { + if (ctx->options->gfx_level >= GFX11) { Temp local_ids[3]; /* Thread IDs are packed in VGPR0, 10 bits per component. */ @@ -8236,7 +8237,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) } case nir_intrinsic_load_local_invocation_index: { if (ctx->stage.hw == HWStage::LS || ctx->stage.hw == HWStage::HS) { - if (ctx->options->chip_class >= GFX11) { + if (ctx->options->gfx_level >= GFX11) { /* On GFX11, RelAutoIndex is WaveID * WaveSize + ThreadID. */ Temp wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), @@ -8378,7 +8379,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) { assert(src.regClass() == bld.lm); Temp tmp; - if (ctx->program->chip_class <= GFX7) + if (ctx->program->gfx_level <= GFX7) tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid); else if (ctx->program->wave_size == 64) tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src); @@ -8583,7 +8584,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) unsigned excess_bytes = bool_use_valu ? 0 : 4 - instr->dest.ssa.bit_size / 8; Definition def = excess_bytes ? bld.def(v1) : Definition(tmp); - if (ctx->program->chip_class >= GFX8) + if (ctx->program->gfx_level >= GFX8) bld.vop1_dpp(aco_opcode::v_mov_b32, def, src, dpp_ctrl); else bld.ds(aco_opcode::ds_swizzle_b32, def, src, (1 << 15) | dpp_ctrl); @@ -8595,7 +8596,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) Temp lo = bld.tmp(v1), hi = bld.tmp(v1); bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src); - if (ctx->program->chip_class >= GFX8) { + if (ctx->program->gfx_level >= GFX8) { lo = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl); hi = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl); } else { @@ -8693,7 +8694,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) case nir_intrinsic_byte_permute_amd: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); assert(dst.regClass() == v1); - assert(ctx->program->chip_class >= GFX8); + assert(ctx->program->gfx_level >= GFX8); bld.vop3(aco_opcode::v_perm_b32, Definition(dst), get_ssa_temp(ctx, instr->src[0].ssa), as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa)), as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa))); @@ -8702,7 +8703,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) case nir_intrinsic_lane_permute_16_amd: { Temp src = get_ssa_temp(ctx, instr->src[0].ssa); Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - assert(ctx->program->chip_class >= GFX10); + assert(ctx->program->gfx_level >= GFX10); if (src.regClass() == s1) { bld.copy(Definition(dst), src); @@ -8792,7 +8793,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) case nir_intrinsic_shader_clock: { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); if (nir_intrinsic_memory_scope(instr) == NIR_SCOPE_SUBGROUP && - ctx->options->chip_class >= GFX10_3) { + ctx->options->gfx_level >= GFX10_3) { /* "((size - 1) << 11) | register" (SHADER_CYCLES is encoded as register 29) */ Temp clock = bld.sopk(aco_opcode::s_getreg_b32, bld.def(s1), ((20 - 1) << 11) | 29); bld.pseudo(aco_opcode::p_create_vector, Definition(dst), clock, Operand::zero()); @@ -8834,7 +8835,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) { - if (ctx->options->chip_class >= GFX10) + if (ctx->options->gfx_level >= GFX10) bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand::c32(127u), get_arg(ctx, ctx->args->ac.gs_invocation_id)); else @@ -9015,15 +9016,15 @@ prepare_cube_coords(isel_context* ctx, std::vector<Temp>& coords, Temp* ddx, Tem Builder bld(ctx->program, ctx->block); Temp ma, tc, sc, id; aco_opcode madak = - ctx->program->chip_class >= GFX10_3 ? aco_opcode::v_fmaak_f32 : aco_opcode::v_madak_f32; + ctx->program->gfx_level >= GFX10_3 ? aco_opcode::v_fmaak_f32 : aco_opcode::v_madak_f32; aco_opcode madmk = - ctx->program->chip_class >= GFX10_3 ? aco_opcode::v_fmamk_f32 : aco_opcode::v_madmk_f32; + ctx->program->gfx_level >= GFX10_3 ? aco_opcode::v_fmamk_f32 : aco_opcode::v_madmk_f32; if (is_array) { coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]); /* see comment in ac_prepare_cube_coords() */ - if (ctx->options->chip_class <= GFX8) + if (ctx->options->gfx_level <= GFX8) coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand::zero(), coords[3]); } @@ -9122,7 +9123,7 @@ visit_tex(isel_context* ctx, nir_tex_instr* instr) } } - bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 && + bool tg4_integer_workarounds = ctx->options->gfx_level <= GFX8 && instr->op == nir_texop_tg4 && (instr->dest_type & (nir_type_int | nir_type_uint)); bool tg4_integer_cube_workaround = tg4_integer_workarounds && instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE; @@ -9260,7 +9261,7 @@ visit_tex(isel_context* ctx, nir_tex_instr* instr) /* pack derivatives */ if (has_ddx || has_ddy) { - if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) { + if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->gfx_level == GFX9) { assert(has_ddx && has_ddy && ddx.size() == 1 && ddy.size() == 1); Temp zero = bld.copy(bld.def(v1), Operand::zero()); derivs = {ddx, zero, ddy, zero}; @@ -9285,7 +9286,7 @@ visit_tex(isel_context* ctx, nir_tex_instr* instr) instr->op != nir_texop_fragment_mask_fetch_amd) coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]); - if (ctx->options->chip_class == GFX9 && instr->sampler_dim == GLSL_SAMPLER_DIM_1D && + if (ctx->options->gfx_level == GFX9 && instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->op != nir_texop_lod && instr->coord_components) { assert(coords.size() > 0 && coords.size() < 3); @@ -9311,8 +9312,8 @@ visit_tex(isel_context* ctx, nir_tex_instr* instr) if (instr->is_sparse) dmask = MAX2(dmask, 1) | 0x10; unsigned dim = - ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF - ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array) + ctx->options->gfx_level >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF + ? ac_get_sampler_dim(ctx->options->gfx_level, instr->sampler_dim, instr->is_array) : 0; bool d16 = instr->dest.ssa.bit_size == 16; Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); @@ -9341,7 +9342,7 @@ visit_tex(isel_context* ctx, nir_tex_instr* instr) MIMG_instruction* tex = emit_mimg(bld, aco_opcode::image_get_resinfo, Definition(tmp_dst), resource, Operand(s4), std::vector<Temp>{lod}); - if (ctx->options->chip_class == GFX9 && instr->op == nir_texop_txs && + if (ctx->options->gfx_level == GFX9 && instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array) { tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1); } else if (instr->op == nir_texop_query_levels) { @@ -10559,7 +10560,7 @@ export_vs_varying(isel_context* ctx, int slot, bool is_pos, int* next_pos) /* GFX10 (Navi1x) skip POS0 exports if EXEC=0 and DONE=0, causing a hang. * Setting valid_mask=1 prevents it and has no other effect. */ - exp->valid_mask = ctx->options->chip_class == GFX10 && is_pos && *next_pos == 0; + exp->valid_mask = ctx->options->gfx_level == GFX10 && is_pos && *next_pos == 0; exp->done = false; exp->compressed = false; if (is_pos) @@ -10587,7 +10588,7 @@ export_vs_psiz_layer_viewport_vrs(isel_context* ctx, int* next_pos, exp->enabled_mask |= 0x4; } if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT] && !outinfo->writes_viewport_index_per_primitive) { - if (ctx->options->chip_class < GFX9) { + if (ctx->options->gfx_level < GFX9) { exp->operands[3] = Operand(ctx->outputs.temps[VARYING_SLOT_VIEWPORT * 4u]); exp->enabled_mask |= 0x8; } else { @@ -10607,7 +10608,7 @@ export_vs_psiz_layer_viewport_vrs(isel_context* ctx, int* next_pos, exp->enabled_mask |= 0x2; } - exp->valid_mask = ctx->options->chip_class == GFX10 && *next_pos == 0; + exp->valid_mask = ctx->options->gfx_level == GFX10 && *next_pos == 0; exp->done = false; exp->compressed = false; exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++; @@ -10743,25 +10744,25 @@ export_fs_mrt_z(isel_context* ctx) /* Both stencil and sample mask only need 16-bits. */ if (!ctx->program->info.ps.writes_z && (ctx->program->info.ps.writes_stencil || ctx->program->info.ps.writes_sample_mask)) { - compr = ctx->program->chip_class < GFX11; /* COMPR flag */ + compr = ctx->program->gfx_level < GFX11; /* COMPR flag */ if (ctx->program->info.ps.writes_stencil) { /* Stencil should be in X[23:16]. */ values[0] = Operand(ctx->outputs.temps[FRAG_RESULT_STENCIL * 4u]); values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand::c32(16u), values[0]); - enabled_channels |= ctx->program->chip_class >= GFX11 ? 0x1 : 0x3; + enabled_channels |= ctx->program->gfx_level >= GFX11 ? 0x1 : 0x3; } if (ctx->program->info.ps.writes_sample_mask) { /* SampleMask should be in Y[15:0]. */ values[1] = Operand(ctx->outputs.temps[FRAG_RESULT_SAMPLE_MASK * 4u]); - enabled_channels |= ctx->program->chip_class >= GFX11 ? 0x2 : 0xc; + enabled_channels |= ctx->program->gfx_level >= GFX11 ? 0x2 : 0xc; } if (ctx->options->key.ps.alpha_to_coverage_via_mrtz && (ctx->outputs.mask[FRAG_RESULT_DATA0] & 0x8)) { /* MRT0 alpha should be in Y[31:16] if alpha-to-coverage is enabled and MRTZ is present. */ - assert(ctx->program->chip_class >= GFX11); + assert(ctx->program->gfx_level >= GFX11); Operand mrtz_alpha = Operand(ctx->outputs.temps[FRAG_RESULT_DATA0 + 3u]); mrtz_alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand::c32(16u), mrtz_alpha); @@ -10792,7 +10793,7 @@ export_fs_mrt_z(isel_context* ctx) if (ctx->options->key.ps.alpha_to_coverage_via_mrtz && (ctx->outputs.mask[FRAG_RESULT_DATA0] & 0x8)) { - assert(ctx->program->chip_class >= GFX11); + assert(ctx->program->gfx_level >= GFX11); values[3] = Operand(ctx->outputs.temps[FRAG_RESULT_DATA0 + 3u]); enabled_channels |= 0x8; } @@ -10801,7 +10802,7 @@ export_fs_mrt_z(isel_context* ctx) /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X * writemask component. */ - if (ctx->options->chip_class == GFX6 && ctx->options->family != CHIP_OLAND && + if (ctx->options->gfx_level == GFX6 && ctx->options->family != CHIP_OLAND && ctx->options->family != CHIP_HAINAN) { enabled_channels |= 0x1; } @@ -10841,7 +10842,7 @@ export_fs_mrt_color(isel_context* ctx, int slot) case V_028714_SPI_SHADER_32_GR: enabled_channels = 0x3; break; case V_028714_SPI_SHADER_32_AR: - if (ctx->options->chip_class >= GFX10) { + if (ctx->options->gfx_level >= GFX10) { /* Special case: on GFX10, the outputs are different for 32_AR */ enabled_channels = 0x3; values[1] = values[3]; @@ -10871,7 +10872,7 @@ export_fs_mrt_color(isel_context* ctx, int slot) values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1); } - if (ctx->program->chip_class >= GFX11) { + if (ctx->program->gfx_level >= GFX11) { /* GFX11 doesn't use COMPR for exports, but the channel mask should be * 0x3 instead. */ @@ -10893,7 +10894,7 @@ create_fs_null_export(isel_context* ctx) Builder bld(ctx->program, ctx->block); /* GFX11 doesn't support NULL exports, and MRT0 should be exported instead. */ - unsigned dest = ctx->options->chip_class >= GFX11 ? V_008DFC_SQ_EXP_MRT : V_008DFC_SQ_EXP_NULL; + unsigned dest = ctx->options->gfx_level >= GFX11 ? V_008DFC_SQ_EXP_MRT : V_008DFC_SQ_EXP_NULL; bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1), /* enabled_mask */ 0, dest, /* compr */ false, /* done */ true, /* vm */ true); } @@ -10932,7 +10933,7 @@ emit_stream_output(isel_context* ctx, Temp const* so_buffers, Temp const* so_wri while (writemask) { int start, count; u_bit_scan_consecutive_range(&writemask, &start, &count); - if (count == 3 && ctx->options->chip_class == GFX6) { + if (count == 3 && ctx->options->gfx_level == GFX6) { /* GFX6 doesn't support storing vec3, split it. */ writemask |= 1u << (start + 2); count = 2; @@ -10964,7 +10965,7 @@ emit_stream_output(isel_context* ctx, Temp const* so_buffers, Temp const* so_wri store->offset = offset; } store->offen = true; - store->glc = ctx->program->chip_class < GFX11; + store->glc = ctx->program->gfx_level < GFX11; store->dlc = false; store->slc = true; ctx->block->instructions.emplace_back(std::move(store)); @@ -11311,7 +11312,7 @@ ngg_emit_sendmsg_gs_alloc_req(isel_context* ctx, Temp vtx_cnt, Temp prm_cnt) Builder bld(ctx->program, ctx->block); Temp prm_cnt_0; - if (ctx->program->chip_class == GFX10 && + if (ctx->program->gfx_level == GFX10 && (ctx->stage.has(SWStage::GS) || ctx->program->info.has_ngg_culling)) { /* Navi 1x workaround: check whether the workgroup has no output. * If so, change the number of exported vertices and primitives to 1. @@ -11414,7 +11415,7 @@ select_program(Program* program, unsigned shader_count, struct nir_shader* const bool endif_merged_wave_info = ctx.tcs_in_out_eq ? i == 1 : (check_merged_wave_info && !(ngg_gs && i == 1)); - if (program->chip_class == GFX10 && program->stage.hw == HWStage::NGG && + if (program->gfx_level == GFX10 && program->stage.hw == HWStage::NGG && program->stage.num_sw_stages() == 1) { /* Workaround for Navi1x HW bug to ensure that all NGG waves launch before * s_sendmsg(GS_ALLOC_REQ). */ @@ -11602,10 +11603,10 @@ select_trap_handler_shader(Program* program, struct nir_shader* shader, ac_shade const struct aco_shader_info* info, const struct radv_shader_args* args) { - assert(options->chip_class == GFX8); + assert(options->gfx_level == GFX8); - init_program(program, compute_cs, info, options->chip_class, - options->family, options->wgp_mode, config); + init_program(program, compute_cs, info, options->gfx_level, options->family, options->wgp_mode, + config); isel_context ctx = {}; ctx.program = program; @@ -11676,7 +11677,7 @@ load_vb_descs(Builder& bld, PhysReg dest, Operand base, unsigned start, unsigned unsigned count = MIN2((bld.program->dev.sgpr_limit - dest.reg()) / 4u, max); unsigned num_loads = (count / 4u) + util_bitcount(count & 0x3); - if (bld.program->chip_class >= GFX10 && num_loads > 1) + if (bld.program->gfx_level >= GFX10 && num_loads > 1) bld.sopp(aco_opcode::s_clause, -1, num_loads - 1); for (unsigned i = 0; i < count;) { @@ -11709,15 +11710,15 @@ calc_nontrivial_instance_id(Builder& bld, const struct radv_shader_args* args, u wait_imm lgkm_imm; lgkm_imm.lgkm = 0; - bld.sopp(aco_opcode::s_waitcnt, -1, lgkm_imm.pack(bld.program->chip_class)); + bld.sopp(aco_opcode::s_waitcnt, -1, lgkm_imm.pack(bld.program->gfx_level)); Definition fetch_index_def(tmp_vgpr0, v1); Operand fetch_index(tmp_vgpr0, v1); Operand div_info(tmp_sgpr, s1); - if (bld.program->chip_class >= GFX8) { + if (bld.program->gfx_level >= GFX8) { /* use SDWA */ - if (bld.program->chip_class < GFX9) { + if (bld.program->gfx_level < GFX9) { bld.vop1(aco_opcode::v_mov_b32, Definition(tmp_vgpr1, v1), div_info); div_info = Operand(tmp_vgpr1, v1); } @@ -11725,7 +11726,7 @@ calc_nontrivial_instance_id(Builder& bld, const struct radv_shader_args* args, u bld.vop2(aco_opcode::v_lshrrev_b32, fetch_index_def, div_info, instance_id); Instruction* instr; - if (bld.program->chip_class >= GFX9) + if (bld.program->gfx_level >= GFX9) instr = bld.vop2_sdwa(aco_opcode::v_add_u32, fetch_index_def, div_info, fetch_index).instr; else instr = bld.vop2_sdwa(aco_opcode::v_add_co_u32, fetch_index_def, Definition(vcc, bld.lm), @@ -11769,11 +11770,11 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_key* key, ac_shade assert(key->num_attributes > 0); /* This should be enough for any shader/stage. */ - unsigned max_user_sgprs = options->chip_class >= GFX9 ? 32 : 16; + unsigned max_user_sgprs = options->gfx_level >= GFX9 ? 32 : 16; *num_preserved_sgprs = max_user_sgprs + 14; - init_program(program, compute_cs, info, options->chip_class, - options->family, options->wgp_mode, config); + init_program(program, compute_cs, info, options->gfx_level, options->family, options->wgp_mode, + config); Block* block = program->create_and_insert_block(); block->kind = block_kind_top_level; @@ -11823,7 +11824,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_key* key, ac_shade /* calculate vgpr requirements */ unsigned num_vgprs = attributes_start.reg() - 256; num_vgprs += key->num_attributes * 4; - if (has_nontrivial_divisors && program->chip_class <= GFX8) + if (has_nontrivial_divisors && program->gfx_level <= GFX8) num_vgprs++; /* make space for nontrivial_tmp_vgpr1 */ unsigned num_sgprs = 0; @@ -11863,7 +11864,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_key* key, ac_shade bld.vop1(aco_opcode::v_mov_b32, Definition(start_instance_vgpr, v1), start_instance); } - bld.sopp(aco_opcode::s_waitcnt, -1, lgkm_imm.pack(program->chip_class)); + bld.sopp(aco_opcode::s_waitcnt, -1, lgkm_imm.pack(program->gfx_level)); for (unsigned i = 0; i < num_descs; i++, loc++) { PhysReg dest(attributes_start.reg() + loc * 4u); @@ -11930,7 +11931,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_key* key, ac_shade if (key->state.alpha_adjust_lo | key->state.alpha_adjust_hi) { wait_imm vm_imm; vm_imm.vm = 0; - bld.sopp(aco_opcode::s_waitcnt, -1, vm_imm.pack(program->chip_class)); + bld.sopp(aco_opcode::s_waitcnt, -1, vm_imm.pack(program->gfx_level)); } /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW. @@ -11972,7 +11973,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_key* key, ac_shade if (has_nontrivial_divisors) { bld.smem(aco_opcode::s_load_dwordx2, Definition(prolog_input, s2), get_arg_fixed(args, args->prolog_inputs), Operand::c32(0u)); - bld.sopp(aco_opcode::s_waitcnt, -1, lgkm_imm.pack(program->chip_class)); + bld.sopp(aco_opcode::s_waitcnt, -1, lgkm_imm.pack(program->gfx_level)); continue_pc = Operand(prolog_input, s2); } @@ -11980,7 +11981,7 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_key* key, ac_shade program->config->float_mode = program->blocks[0].fp_mode.val; /* addition on GFX6-8 requires a carry-out (we use VCC) */ - program->needs_vcc = program->chip_class <= GFX8; + program->needs_vcc = program->gfx_level <= GFX8; program->config->num_vgprs = get_vgpr_alloc(program, num_vgprs); program->config->num_sgprs = get_sgpr_alloc(program, num_sgprs); } diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index a0ff8164b47..2ec35b23531 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -262,7 +262,7 @@ setup_vs_output_info(isel_context* ctx, nir_shader* nir, * as soon as it encounters a DONE pos export. When this happens, PS waves can launch * before the NGG (or VS) waves finish. */ - ctx->program->early_rast = ctx->program->chip_class >= GFX10 && outinfo->param_exports == 0; + ctx->program->early_rast = ctx->program->gfx_level >= GFX10 && outinfo->param_exports == 0; } void @@ -863,8 +863,8 @@ setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* c default: unreachable("Shader stage not implemented"); } } - bool gfx9_plus = options->chip_class >= GFX9; - bool ngg = info->is_ngg && options->chip_class >= GFX10; + bool gfx9_plus = options->gfx_level >= GFX9; + bool ngg = info->is_ngg && options->gfx_level >= GFX10; HWStage hw_stage{}; if (sw_stage == SWStage::VS && info->vs.as_es && !ngg) hw_stage = HWStage::ES; @@ -907,8 +907,8 @@ setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* c else unreachable("Shader stage not implemented"); - init_program(program, Stage{hw_stage, sw_stage}, info, options->chip_class, - options->family, options->wgp_mode, config); + init_program(program, Stage{hw_stage, sw_stage}, info, options->gfx_level, options->family, + options->wgp_mode, config); isel_context ctx = {}; ctx.program = program; @@ -921,7 +921,7 @@ setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* c /* Mesh shading only works on GFX10.3+. */ ASSERTED bool mesh_shading = ctx.stage.has(SWStage::TS) || ctx.stage.has(SWStage::MS); - assert(!mesh_shading || ctx.program->chip_class >= GFX10_3); + assert(!mesh_shading || ctx.program->gfx_level >= GFX10_3); if (ctx.stage == tess_control_hs) setup_tcs_info(&ctx, shaders[0], NULL); diff --git a/src/amd/compiler/aco_interface.cpp b/src/amd/compiler/aco_interface.cpp index a2f85f64d73..200c5932717 100644 --- a/src/amd/compiler/aco_interface.cpp +++ b/src/amd/compiler/aco_interface.cpp @@ -212,7 +212,7 @@ aco_compile_shader(const struct radv_nir_compiler_options* options, aco::insert_wait_states(program.get()); aco::insert_NOPs(program.get()); - if (program->chip_class >= GFX10) + if (program->gfx_level >= GFX10) aco::form_hard_clauses(program.get()); if (program->collect_statistics || (aco::debug_flags & aco::DEBUG_PERF_INFO)) diff --git a/src/amd/compiler/aco_ir.cpp b/src/amd/compiler/aco_ir.cpp index 2bc5b4e447a..0e0f76c73d4 100644 --- a/src/amd/compiler/aco_ir.cpp +++ b/src/amd/compiler/aco_ir.cpp @@ -66,15 +66,15 @@ init() void init_program(Program* program, Stage stage, const struct aco_shader_info* info, - enum chip_class chip_class, enum radeon_family family, bool wgp_mode, + enum amd_gfx_level gfx_level, enum radeon_family family, bool wgp_mode, ac_shader_config* config) { program->stage = stage; program->config = config; program->info = *info; - program->chip_class = chip_class; + program->gfx_level = gfx_level; if (family == CHIP_UNKNOWN) { - switch (chip_class) { + switch (gfx_level) { case GFX6: program->family = CHIP_TAHITI; break; case GFX7: program->family = CHIP_BONAIRE; break; case GFX8: program->family = CHIP_POLARIS10; break; @@ -88,12 +88,10 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info, program->wave_size = info->wave_size; program->lane_mask = program->wave_size == 32 ? s1 : s2; - program->dev.lds_encoding_granule = chip_class >= GFX11 && stage == fragment_fs ? 1024 - : chip_class >= GFX7 ? 512 - : 256; - program->dev.lds_alloc_granule = - chip_class >= GFX10_3 ? 1024 : program->dev.lds_encoding_granule; - program->dev.lds_limit = chip_class >= GFX7 ? 65536 : 32768; + program->dev.lds_encoding_granule = gfx_level >= GFX11 && stage == fragment_fs ? 1024 : + gfx_level >= GFX7 ? 512 : 256; + program->dev.lds_alloc_granule = gfx_level >= GFX10_3 ? 1024 : program->dev.lds_encoding_granule; + program->dev.lds_limit = gfx_level >= GFX7 ? 65536 : 32768; /* apparently gfx702 also has 16-bank LDS but I can't find a family for that */ program->dev.has_16bank_lds = family == CHIP_KABINI || family == CHIP_STONEY; @@ -101,17 +99,17 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info, program->dev.physical_vgprs = 256; program->dev.vgpr_alloc_granule = 4; - if (chip_class >= GFX10) { + if (gfx_level >= GFX10) { program->dev.physical_sgprs = 5120; /* doesn't matter as long as it's at least 128 * 40 */ program->dev.physical_vgprs = program->wave_size == 32 ? 1024 : 512; program->dev.sgpr_alloc_granule = 128; program->dev.sgpr_limit = 108; /* includes VCC, which can be treated as s[106-107] on GFX10+ */ - if (chip_class == GFX10_3) + if (gfx_level == GFX10_3) program->dev.vgpr_alloc_granule = program->wave_size == 32 ? 16 : 8; else program->dev.vgpr_alloc_granule = program->wave_size == 32 ? 8 : 4; - } else if (program->chip_class >= GFX8) { + } else if (program->gfx_level >= GFX8) { program->dev.physical_sgprs = 800; program->dev.sgpr_alloc_granule = 16; program->dev.sgpr_limit = 102; @@ -124,14 +122,14 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info, } program->dev.max_wave64_per_simd = 10; - if (program->chip_class >= GFX10_3) + if (program->gfx_level >= GFX10_3) program->dev.max_wave64_per_simd = 16; - else if (program->chip_class == GFX10) + else if (program->gfx_level == GFX10) program->dev.max_wave64_per_simd = 20; else if (program->family >= CHIP_POLARIS10 && program->family <= CHIP_VEGAM) program->dev.max_wave64_per_simd = 8; - program->dev.simd_per_cu = program->chip_class >= GFX10 ? 2 : 4; + program->dev.simd_per_cu = program->gfx_level >= GFX10 ? 2 : 4; switch (program->family) { /* GFX8 APUs */ @@ -146,13 +144,13 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info, program->dev.sram_ecc_enabled = program->family == CHIP_ARCTURUS; /* apparently gfx702 also has fast v_fma_f32 but I can't find a family for that */ - program->dev.has_fast_fma32 = program->chip_class >= GFX9; + program->dev.has_fast_fma32 = program->gfx_level >= GFX9; if (program->family == CHIP_TAHITI || program->family == CHIP_CARRIZO || program->family == CHIP_HAWAII) program->dev.has_fast_fma32 = true; - program->dev.has_mac_legacy32 = program->chip_class <= GFX7 || program->chip_class >= GFX10; + program->dev.has_mac_legacy32 = program->gfx_level <= GFX7 || program->gfx_level >= GFX10; - program->dev.fused_mad_mix = program->chip_class >= GFX10; + program->dev.fused_mad_mix = program->gfx_level >= GFX10; if (program->family == CHIP_VEGA12 || program->family == CHIP_VEGA20 || program->family == CHIP_ARCTURUS || program->family == CHIP_ALDEBARAN) program->dev.fused_mad_mix = true; @@ -190,12 +188,12 @@ get_sync_info(const Instruction* instr) } bool -can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_ra) +can_use_SDWA(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, bool pre_ra) { if (!instr->isVALU()) return false; - if (chip < GFX8 || instr->isDPP() || instr->isVOP3P()) + if (gfx_level < GFX8 || instr->isDPP() || instr->isVOP3P()) return false; if (instr->isSDWA()) @@ -205,9 +203,9 @@ can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_ra) VOP3_instruction& vop3 = instr->vop3(); if (instr->format == Format::VOP3) return false; - if (vop3.clamp && instr->isVOPC() && chip != GFX8) + if (vop3.clamp && instr->isVOPC() && gfx_level != GFX8) return false; - if (vop3.omod && chip < GFX9) + if (vop3.omod && gfx_level < GFX9) return false; // TODO: return true if we know we will use vcc @@ -217,7 +215,7 @@ can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_ra) for (unsigned i = 1; i < instr->operands.size(); i++) { if (instr->operands[i].isLiteral()) return false; - if (chip < GFX9 && !instr->operands[i].isOfType(RegType::vgpr)) + if (gfx_level < GFX9 && !instr->operands[i].isOfType(RegType::vgpr)) return false; } } @@ -228,7 +226,7 @@ can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_ra) if (!instr->operands.empty()) { if (instr->operands[0].isLiteral()) return false; - if (chip < GFX9 && !instr->operands[0].isOfType(RegType::vgpr)) + if (gfx_level < GFX9 && !instr->operands[0].isOfType(RegType::vgpr)) return false; if (instr->operands[0].bytes() > 4) return false; @@ -239,11 +237,11 @@ can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_ra) bool is_mac = instr->opcode == aco_opcode::v_mac_f32 || instr->opcode == aco_opcode::v_mac_f16 || instr->opcode == aco_opcode::v_fmac_f32 || instr->opcode == aco_opcode::v_fmac_f16; - if (chip != GFX8 && is_mac) + if (gfx_level != GFX8 && is_mac) return false; // TODO: return true if we know we will use vcc - if (!pre_ra && instr->isVOPC() && chip == GFX8) + if (!pre_ra && instr->isVOPC() && gfx_level == GFX8) return false; if (!pre_ra && instr->operands.size() >= 3 && !is_mac) return false; @@ -256,7 +254,7 @@ can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_ra) /* updates "instr" and returns the old instruction (or NULL if no update was needed) */ aco_ptr<Instruction> -convert_to_SDWA(chip_class chip, aco_ptr<Instruction>& instr) +convert_to_SDWA(amd_gfx_level gfx_level, aco_ptr<Instruction>& instr) { if (instr->isSDWA()) return NULL; @@ -289,7 +287,7 @@ convert_to_SDWA(chip_class chip, aco_ptr<Instruction>& instr) sdwa.dst_sel = SubdwordSel(instr->definitions[0].bytes(), 0, false); - if (instr->definitions[0].getTemp().type() == RegType::sgpr && chip == GFX8) + if (instr->definitions[0].getTemp().type() == RegType::sgpr && gfx_level == GFX8) instr->definitions[0].setFixed(vcc); if (instr->definitions.size() >= 2) instr->definitions[1].setFixed(vcc); @@ -390,10 +388,10 @@ convert_to_DPP(aco_ptr<Instruction>& instr, bool dpp8) } bool -can_use_opsel(chip_class chip, aco_opcode op, int idx) +can_use_opsel(amd_gfx_level gfx_level, aco_opcode op, int idx) { /* opsel is only GFX9+ */ - if (chip < GFX9) + if (gfx_level < GFX9) return false; switch (op) { @@ -433,10 +431,10 @@ can_use_opsel(chip_class chip, aco_opcode op, int idx) } bool -instr_is_16bit(chip_class chip, aco_opcode op) +instr_is_16bit(amd_gfx_level gfx_level, aco_opcode op) { /* partial register writes are GFX9+, only */ - if (chip < GFX9) + if (gfx_level < GFX9) return false; switch (op) { @@ -451,7 +449,7 @@ instr_is_16bit(chip_class chip, aco_opcode op) /* VOP2 */ case aco_opcode::v_mac_f16: case aco_opcode::v_madak_f16: - case aco_opcode::v_madmk_f16: return chip >= GFX9; + case aco_opcode::v_madmk_f16: return gfx_level >= GFX9; case aco_opcode::v_add_f16: case aco_opcode::v_sub_f16: case aco_opcode::v_subrev_f16: @@ -479,7 +477,7 @@ instr_is_16bit(chip_class chip, aco_opcode op) case aco_opcode::v_rndne_f16: case aco_opcode::v_fract_f16: case aco_opcode::v_sin_f16: - case aco_opcode::v_cos_f16: return chip >= GFX10; + case aco_opcode::v_cos_f16: return gfx_level >= GFX10; // TODO: confirm whether these write 16 or 32 bit on GFX10+ // case aco_opcode::v_cvt_u16_f16: // case aco_opcode::v_cvt_i16_f16: @@ -487,7 +485,7 @@ instr_is_16bit(chip_class chip, aco_opcode op) // case aco_opcode::v_cvt_norm_i16_f16: // case aco_opcode::v_cvt_norm_u16_f16: /* on GFX10, all opsel instructions preserve the high bits */ - default: return chip >= GFX10 && can_use_opsel(chip, op, -1); + default: return gfx_level >= GFX10 && can_use_opsel(gfx_level, op, -1); } } @@ -760,25 +758,25 @@ wait_imm::wait_imm(uint16_t vm_, uint16_t exp_, uint16_t lgkm_, uint16_t vs_) : vm(vm_), exp(exp_), lgkm(lgkm_), vs(vs_) {} -wait_imm::wait_imm(enum chip_class chip, uint16_t packed) : vs(unset_counter) +wait_imm::wait_imm(enum amd_gfx_level gfx_level, uint16_t packed) : vs(unset_counter) { vm = packed & 0xf; - if (chip >= GFX9) + if (gfx_level >= GFX9) vm |= (packed >> 10) & 0x30; exp = (packed >> 4) & 0x7; lgkm = (packed >> 8) & 0xf; - if (chip >= GFX10) + if (gfx_level >= GFX10) lgkm |= (packed >> 8) & 0x30; } uint16_t -wait_imm::pack(enum chip_class chip) const +wait_imm::pack(enum amd_gfx_level gfx_level) const { uint16_t imm = 0; assert(exp == unset_counter || exp <= 0x7); - switch (chip) { + switch (gfx_level) { case GFX11: assert(lgkm == unset_counter || lgkm <= 0x3f); assert(vm == unset_counter || vm <= 0x3f); @@ -801,10 +799,10 @@ wait_imm::pack(enum chip_class chip) const imm = ((lgkm & 0xf) << 8) | ((exp & 0x7) << 4) | (vm & 0xf); break; } - if (chip < GFX9 && vm == wait_imm::unset_counter) + if (gfx_level < GFX9 && vm == wait_imm::unset_counter) imm |= 0xc000; /* should have no effect on pre-GFX9 and now we won't have to worry about the architecture when interpreting the immediate */ - if (chip < GFX10 && lgkm == wait_imm::unset_counter) + if (gfx_level < GFX10 && lgkm == wait_imm::unset_counter) imm |= 0x3000; /* should have no effect on pre-GFX10 and now we won't have to worry about the architecture when interpreting the immediate */ return imm; diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index a6dbbe0d902..9f860c38f5e 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -270,9 +270,9 @@ struct wait_imm { wait_imm(); wait_imm(uint16_t vm_, uint16_t exp_, uint16_t lgkm_, uint16_t vs_); - wait_imm(enum chip_class chip, uint16_t packed); + wait_imm(enum amd_gfx_level chip, uint16_t packed); - uint16_t pack(enum chip_class chip) const; + uint16_t pack(enum amd_gfx_level chip) const; bool combine(const wait_imm& other); @@ -668,10 +668,10 @@ public: return Operand::c8(0); } - /* This is useful over the constructors when you want to take a chip class + /* This is useful over the constructors when you want to take a gfx level * for 1/2 PI or an unknown operand size. */ - static Operand get_const(enum chip_class chip, uint64_t val, unsigned bytes) + static Operand get_const(enum amd_gfx_level chip, uint64_t val, unsigned bytes) { if (val == 0x3e22f983 && bytes == 4 && chip >= GFX8) { /* 1/2 PI can be an inline constant on GFX8+ */ @@ -1766,12 +1766,12 @@ memory_sync_info get_sync_info(const Instruction* instr); bool is_dead(const std::vector<uint16_t>& uses, Instruction* instr); -bool can_use_opsel(chip_class chip, aco_opcode op, int idx); -bool instr_is_16bit(chip_class chip, aco_opcode op); -bool can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr, bool pre_ra); +bool can_use_opsel(amd_gfx_level gfx_level, aco_opcode op, int idx); +bool instr_is_16bit(amd_gfx_level gfx_level, aco_opcode op); +bool can_use_SDWA(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, bool pre_ra); bool can_use_DPP(const aco_ptr<Instruction>& instr, bool pre_ra, bool dpp8); /* updates "instr" and returns the old instruction (or NULL if no update was needed) */ -aco_ptr<Instruction> convert_to_SDWA(chip_class chip, aco_ptr<Instruction>& instr); +aco_ptr<Instruction> convert_to_SDWA(amd_gfx_level gfx_level, aco_ptr<Instruction>& instr); aco_ptr<Instruction> convert_to_DPP(aco_ptr<Instruction>& instr, bool dpp8); bool needs_exec_mask(const Instruction* instr); @@ -2053,7 +2053,7 @@ public: RegisterDemand max_reg_demand = RegisterDemand(); ac_shader_config* config; struct aco_shader_info info; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; enum radeon_family family; DeviceInfo dev; unsigned wave_size; @@ -2151,7 +2151,7 @@ struct ra_test_policy { void init(); void init_program(Program* program, Stage stage, const struct aco_shader_info* info, - enum chip_class chip_class, enum radeon_family family, bool wgp_mode, + enum amd_gfx_level gfx_level, enum radeon_family family, bool wgp_mode, ac_shader_config* config); void select_program(Program* program, unsigned shader_count, struct nir_shader* const* shaders, diff --git a/src/amd/compiler/aco_live_var_analysis.cpp b/src/amd/compiler/aco_live_var_analysis.cpp index f6489f6fb09..0449fa1cdff 100644 --- a/src/amd/compiler/aco_live_var_analysis.cpp +++ b/src/amd/compiler/aco_live_var_analysis.cpp @@ -293,11 +293,11 @@ calc_waves_per_workgroup(Program* program) uint16_t get_extra_sgprs(Program* program) { - if (program->chip_class >= GFX10) { + if (program->gfx_level >= GFX10) { assert(!program->needs_flat_scr); assert(!program->dev.xnack_enabled); return 0; - } else if (program->chip_class >= GFX8) { + } else if (program->gfx_level >= GFX8) { if (program->needs_flat_scr) return 6; else if (program->dev.xnack_enabled) @@ -439,7 +439,7 @@ live_var_analysis(Program* program) std::vector<PhiInfo> phi_info(program->blocks.size()); RegisterDemand new_demand; - program->needs_vcc = program->chip_class >= GFX10; + program->needs_vcc = program->gfx_level >= GFX10; /* this implementation assumes that the block idx corresponds to the block's position in * program->blocks vector */ diff --git a/src/amd/compiler/aco_lower_to_cssa.cpp b/src/amd/compiler/aco_lower_to_cssa.cpp index 753a869cc41..3dacd29ee78 100644 --- a/src/amd/compiler/aco_lower_to_cssa.cpp +++ b/src/amd/compiler/aco_lower_to_cssa.cpp @@ -104,7 +104,7 @@ collect_parallelcopies(cssa_ctx& ctx) /* SGPR inline constants and literals on GFX10+ can be spilled * and reloaded directly (without intermediate register) */ if (op.isConstant()) { - if (ctx.program->chip_class >= GFX10) + if (ctx.program->gfx_level >= GFX10) continue; if (op.size() == 1 && !op.isLiteral()) continue; diff --git a/src/amd/compiler/aco_lower_to_hw_instr.cpp b/src/amd/compiler/aco_lower_to_hw_instr.cpp index 94747db3061..38a553b8572 100644 --- a/src/amd/compiler/aco_lower_to_hw_instr.cpp +++ b/src/amd/compiler/aco_lower_to_hw_instr.cpp @@ -68,7 +68,7 @@ uint8_t int8_mul_table[512] = { 1, 250, 1, 251, 1, 252, 1, 253, 1, 254, 1, 255}; aco_opcode -get_reduce_opcode(chip_class chip, ReduceOp op) +get_reduce_opcode(amd_gfx_level gfx_level, ReduceOp op) { /* Because some 16-bit instructions are already VOP3 on GFX10, we use the * 32-bit opcodes (VOP2) which allows to remove the tempory VGPR and to use @@ -77,9 +77,9 @@ get_reduce_opcode(chip_class chip, ReduceOp op) switch (op) { case iadd8: case iadd16: - if (chip >= GFX10) { + if (gfx_level >= GFX10) { return aco_opcode::v_add_u32; - } else if (chip >= GFX8) { + } else if (gfx_level >= GFX8) { return aco_opcode::v_add_u16; } else { return aco_opcode::v_add_co_u32; @@ -87,9 +87,9 @@ get_reduce_opcode(chip_class chip, ReduceOp op) break; case imul8: case imul16: - if (chip >= GFX10) { + if (gfx_level >= GFX10) { return aco_opcode::v_mul_lo_u16_e64; - } else if (chip >= GFX8) { + } else if (gfx_level >= GFX8) { return aco_opcode::v_mul_lo_u16; } else { return aco_opcode::v_mul_u32_u24; @@ -99,9 +99,9 @@ get_reduce_opcode(chip_class chip, ReduceOp op) case fmul16: return aco_opcode::v_mul_f16; case imax8: case imax16: - if (chip >= GFX10) { + if (gfx_level >= GFX10) { return aco_opcode::v_max_i32; - } else if (chip >= GFX8) { + } else if (gfx_level >= GFX8) { return aco_opcode::v_max_i16; } else { return aco_opcode::v_max_i32; @@ -109,9 +109,9 @@ get_reduce_opcode(chip_class chip, ReduceOp op) break; case imin8: case imin16: - if (chip >= GFX10) { + if (gfx_level >= GFX10) { return aco_opcode::v_min_i32; - } else if (chip >= GFX8) { + } else if (gfx_level >= GFX8) { return aco_opcode::v_min_i16; } else { return aco_opcode::v_min_i32; @@ -119,9 +119,9 @@ get_reduce_opcode(chip_class chip, ReduceOp op) break; case umin8: case umin16: - if (chip >= GFX10) { + if (gfx_level >= GFX10) { return aco_opcode::v_min_u32; - } else if (chip >= GFX8) { + } else if (gfx_level >= GFX8) { return aco_opcode::v_min_u16; } else { return aco_opcode::v_min_u32; @@ -129,9 +129,9 @@ get_reduce_opcode(chip_class chip, ReduceOp op) break; case umax8: case umax16: - if (chip >= GFX10) { + if (gfx_level >= GFX10) { return aco_opcode::v_max_u32; - } else if (chip >= GFX8) { + } else if (gfx_level >= GFX8) { return aco_opcode::v_max_u16; } else { return aco_opcode::v_max_u32; @@ -139,7 +139,7 @@ get_reduce_opcode(chip_class chip, ReduceOp op) break; case fmin16: return aco_opcode::v_min_f16; case fmax16: return aco_opcode::v_max_f16; - case iadd32: return chip >= GFX9 ? aco_opcode::v_add_u32 : aco_opcode::v_add_co_u32; + case iadd32: return gfx_level >= GFX9 ? aco_opcode::v_add_u32 : aco_opcode::v_add_co_u32; case imul32: return aco_opcode::v_mul_lo_u32; case fadd32: return aco_opcode::v_add_f32; case fmul32: return aco_opcode::v_mul_f32; @@ -209,7 +209,7 @@ emit_int64_dpp_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg Operand vtmp_op[] = {Operand(vtmp_reg, v1), Operand(PhysReg{vtmp_reg + 1}, v1)}; Operand vtmp_op64 = Operand(vtmp_reg, v2); if (op == iadd64) { - if (ctx->program->chip_class >= GFX10) { + if (ctx->program->gfx_level >= GFX10) { if (identity) bld.vop1(aco_opcode::v_mov_b32, vtmp_def[0], identity[0]); bld.vop1_dpp(aco_opcode::v_mov_b32, vtmp_def[0], src0[0], dpp_ctrl, row_mask, bank_mask, @@ -323,7 +323,7 @@ emit_int64_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src } if (op == iadd64) { - if (ctx->program->chip_class >= GFX10) { + if (ctx->program->gfx_level >= GFX10) { bld.vop3(aco_opcode::v_add_co_u32_e64, dst[0], bld.def(bld.lm, vcc), src0[0], src1[0]); } else { bld.vop2(aco_opcode::v_add_co_u32, dst[0], bld.def(bld.lm, vcc), src0[0], src1[0]); @@ -393,7 +393,7 @@ emit_dpp_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_ Operand src0(src0_reg, rc); Operand src1(src1_reg, rc); - aco_opcode opcode = get_reduce_opcode(ctx->program->chip_class, op); + aco_opcode opcode = get_reduce_opcode(ctx->program->gfx_level, op); bool vop3 = is_vop3_reduce_opcode(opcode); if (!vop3) { @@ -433,7 +433,7 @@ emit_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size)); Operand src1(src1_reg, rc); - aco_opcode opcode = get_reduce_opcode(ctx->program->chip_class, op); + aco_opcode opcode = get_reduce_opcode(ctx->program->gfx_level, op); bool vop3 = is_vop3_reduce_opcode(opcode); if (opcode == aco_opcode::num_opcodes) { @@ -492,7 +492,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c /* p_exclusive_scan needs it to be a sgpr or inline constant for the v_writelane_b32 * except on GFX10, where v_writelane_b32 can take a literal. */ if (identity[i].isLiteral() && op == aco_opcode::p_exclusive_scan && - ctx->program->chip_class < GFX10) { + ctx->program->gfx_level < GFX10) { bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg{sitmp + i}, s1), identity[i]); identity[i] = Operand(PhysReg{sitmp + i}, s1); @@ -511,7 +511,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c } if (src.regClass() == v1b) { - if (ctx->program->chip_class >= GFX8) { + if (ctx->program->gfx_level >= GFX8) { aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>( aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1)}; sdwa->operands[0] = Operand(PhysReg{tmp}, v1); @@ -532,7 +532,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c Operand::c32(8u)); } } else if (src.regClass() == v2b) { - if (ctx->program->chip_class >= GFX10 && + if (ctx->program->gfx_level >= GFX10 && (reduce_op == iadd16 || reduce_op == imax16 || reduce_op == imin16 || reduce_op == umin16 || reduce_op == umax16)) { aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>( @@ -543,7 +543,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c sdwa->sel[0] = SubdwordSel(2, 0, sext); sdwa->dst_sel = SubdwordSel::dword; bld.insert(std::move(sdwa)); - } else if (ctx->program->chip_class == GFX6 || ctx->program->chip_class == GFX7) { + } else if (ctx->program->gfx_level == GFX6 || ctx->program->gfx_level == GFX7) { aco_opcode opcode; if (reduce_op == imin16 || reduce_op == imax16 || reduce_op == iadd16) @@ -562,7 +562,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c if (cluster_size == 1) break; - if (ctx->program->chip_class <= GFX7) { + if (ctx->program->gfx_level <= GFX7) { reduction_needs_last_op = true; emit_ds_swizzle(bld, vtmp, tmp, src.size(), (1 << 15) | dpp_quad_perm(1, 0, 3, 2)); if (cluster_size == 2) @@ -609,7 +609,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c if (cluster_size == 16) break; - if (ctx->program->chip_class >= GFX10) { + if (ctx->program->gfx_level >= GFX10) { /* GFX10+ doesn't support row_bcast15 and row_bcast31 */ for (unsigned i = 0; i < src.size(); i++) bld.vop3(aco_opcode::v_permlanex16_b32, Definition(PhysReg{vtmp + i}, v1), @@ -641,7 +641,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c false); break; case aco_opcode::p_exclusive_scan: - if (ctx->program->chip_class >= GFX10) { /* gfx10 doesn't support wf_sr1, so emulate it */ + if (ctx->program->gfx_level >= GFX10) { /* gfx10 doesn't support wf_sr1, so emulate it */ /* shift rows right */ emit_dpp_mov(ctx, vtmp, tmp, src.size(), dpp_row_sr(1), 0xf, 0xf, true); @@ -668,7 +668,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c } } std::swap(tmp, vtmp); - } else if (ctx->program->chip_class >= GFX8) { + } else if (ctx->program->gfx_level >= GFX8) { emit_dpp_mov(ctx, tmp, tmp, src.size(), dpp_wf_sr1, 0xf, 0xf, true); } else { // TODO: use LDS on CS with a single write and shifted read @@ -718,7 +718,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c for (unsigned i = 0; i < src.size(); i++) { if (!identity[i].isConstant() || identity[i].constantValue()) { /* bound_ctrl should take care of this overwise */ - if (ctx->program->chip_class < GFX10) + if (ctx->program->gfx_level < GFX10) assert((identity[i].isConstant() && !identity[i].isLiteral()) || identity[i].physReg() == PhysReg{sitmp + i}); bld.writelane(Definition(PhysReg{tmp + i}, v1), identity[i], Operand::zero(), @@ -728,7 +728,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c FALLTHROUGH; case aco_opcode::p_inclusive_scan: assert(cluster_size == ctx->program->wave_size); - if (ctx->program->chip_class <= GFX7) { + if (ctx->program->gfx_level <= GFX7) { emit_ds_swizzle(bld, vtmp, tmp, src.size(), ds_pattern_bitmode(0x1e, 0x00, 0x00)); bld.sop1(aco_opcode::s_mov_b32, Definition(exec_lo, s1), Operand::c32(0xAAAAAAAAu)); bld.sop1(aco_opcode::s_mov_b32, Definition(exec_hi, s1), Operand(exec_lo, s1)); @@ -777,7 +777,7 @@ emit_reduction(lower_context* ctx, aco_opcode op, ReduceOp reduce_op, unsigned c identity); emit_dpp_op(ctx, tmp, tmp, tmp, vtmp, reduce_op, src.size(), dpp_row_sr(8), 0xf, 0xf, false, identity); - if (ctx->program->chip_class >= GFX10) { + if (ctx->program->gfx_level >= GFX10) { bld.sop2(aco_opcode::s_bfm_b32, Definition(exec_lo, s1), Operand::c32(16u), Operand::c32(16u)); bld.sop2(aco_opcode::s_bfm_b32, Definition(exec_hi, s1), Operand::c32(16u), @@ -847,7 +847,7 @@ emit_gfx10_wave64_bpermute(Program* program, aco_ptr<Instruction>& instr, Builde * manually swap the data between the two halves using two shared VGPRs. */ - assert(program->chip_class >= GFX10); + assert(program->gfx_level >= GFX10); assert(program->wave_size == 64); unsigned shared_vgpr_reg_0 = align(program->config->num_vgprs, 4) + 256; @@ -976,7 +976,7 @@ split_copy(lower_context* ctx, unsigned offset, Definition* def, Operand* op, op_reg.reg_b += offset; /* 64-bit VGPR copies (implemented with v_lshrrev_b64) are slow before GFX10 */ - if (ctx->program->chip_class < GFX10 && src.def.regClass().type() == RegType::vgpr) + if (ctx->program->gfx_level < GFX10 && src.def.regClass().type() == RegType::vgpr) max_size = MIN2(max_size, 4); unsigned max_align = src.def.regClass().type() == RegType::vgpr ? 4 : 16; @@ -998,7 +998,7 @@ split_copy(lower_context* ctx, unsigned offset, Definition* def, Operand* op, if (src.op.isConstant()) { assert(bytes >= 1 && bytes <= 8); uint64_t val = src.op.constantValue64() >> (offset * 8u); - *op = Operand::get_const(ctx->program->chip_class, val, bytes); + *op = Operand::get_const(ctx->program->gfx_level, val, bytes); } else { RegClass op_cls = src.op.regClass().resize(bytes); *op = Operand(op_reg, op_cls); @@ -1045,7 +1045,7 @@ copy_constant(lower_context* ctx, Builder& bld, Definition dst, Operand op) } } - if (op.bytes() == 4 && op.constantEquals(0x3e22f983) && ctx->program->chip_class >= GFX8) + if (op.bytes() == 4 && op.constantEquals(0x3e22f983) && ctx->program->gfx_level >= GFX8) op.setFixed(PhysReg{248}); /* it can be an inline constant on GFX8+ */ if (dst.regClass() == s1) { @@ -1066,7 +1066,7 @@ copy_constant(lower_context* ctx, Builder& bld, Definition dst, Operand op) } else { assert(dst.regClass() == v1b || dst.regClass() == v2b); - if (dst.regClass() == v1b && ctx->program->chip_class >= GFX9) { + if (dst.regClass() == v1b && ctx->program->gfx_level >= GFX9) { uint8_t val = op.constantValue(); Operand op32 = Operand::c32((uint32_t)val | (val & 0x80u ? 0xffffff00u : 0u)); if (op32.isLiteral()) { @@ -1078,7 +1078,7 @@ copy_constant(lower_context* ctx, Builder& bld, Definition dst, Operand op) } else { bld.vop1_sdwa(aco_opcode::v_mov_b32, dst, op32); } - } else if (dst.regClass() == v2b && ctx->program->chip_class >= GFX9 && !op.isLiteral()) { + } else if (dst.regClass() == v2b && ctx->program->gfx_level >= GFX9 && !op.isLiteral()) { if (op.constantValue() >= 0xfff0 || op.constantValue() <= 64) { /* use v_mov_b32 to avoid possible issues with denormal flushing or * NaN. v_add_f16 is still needed for float constants. */ @@ -1087,7 +1087,7 @@ copy_constant(lower_context* ctx, Builder& bld, Definition dst, Operand op) } else { bld.vop2_sdwa(aco_opcode::v_add_f16, dst, op, Operand::zero()); } - } else if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10 && + } else if (dst.regClass() == v2b && ctx->program->gfx_level >= GFX10 && (ctx->block->fp_mode.denorm16_64 & fp_denorm_keep_in)) { if (dst.physReg().byte() == 2) { Operand def_lo(dst.physReg().advance(-2), v2b); @@ -1144,7 +1144,7 @@ swap_linear_vgpr(Builder& bld, Definition def, Operand op, bool preserve_scc, Ph Definition op_as_def = Definition(op.physReg(), op.regClass()); for (unsigned i = 0; i < 2; i++) { - if (bld.program->chip_class >= GFX9) { + if (bld.program->gfx_level >= GFX9) { bld.vop1(aco_opcode::v_swap_b32, def, op_as_def, op, def_as_op); } else { bld.vop2(aco_opcode::v_xor_b32, op_as_def, op, def_as_op); @@ -1191,7 +1191,7 @@ do_copy(lower_context* ctx, Builder& bld, const copy_operation& copy, bool* pres bld.sop1(aco_opcode::s_mov_b32, def, op); } else if (def.regClass() == s2) { bld.sop1(aco_opcode::s_mov_b64, def, op); - } else if (def.regClass().is_subdword() && ctx->program->chip_class < GFX8) { + } else if (def.regClass().is_subdword() && ctx->program->gfx_level < GFX8) { if (op.physReg().byte()) { assert(def.physReg().byte() == 0); bld.vop2(aco_opcode::v_lshrrev_b32, def, Operand::c32(op.physReg().byte() * 8), op); @@ -1284,7 +1284,7 @@ do_swap(lower_context* ctx, Builder& bld, const copy_operation& copy, bool prese Definition op_as_def = Definition(op.physReg(), op.regClass()); if (def.regClass().is_linear_vgpr()) { swap_linear_vgpr(bld, def, op, preserve_scc, pi->scratch_sgpr); - } else if (ctx->program->chip_class >= GFX9 && def.regClass() == v1) { + } else if (ctx->program->gfx_level >= GFX9 && def.regClass() == v1) { bld.vop1(aco_opcode::v_swap_b32, def, op_as_def, op, def_as_op); } else if (def.regClass() == v1) { assert(def.physReg().byte() == 0 && op.physReg().byte() == 0); @@ -1333,7 +1333,7 @@ do_swap(lower_context* ctx, Builder& bld, const copy_operation& copy, bool prese offset += def.bytes(); } - if (ctx->program->chip_class <= GFX7) + if (ctx->program->gfx_level <= GFX7) return; /* fixup in case we swapped bytes we shouldn't have */ @@ -1352,8 +1352,8 @@ do_pack_2x16(lower_context* ctx, Builder& bld, Definition def, Operand lo, Opera } bool can_use_pack = (ctx->block->fp_mode.denorm16_64 & fp_denorm_keep_in) && - (ctx->program->chip_class >= GFX10 || - (ctx->program->chip_class >= GFX9 && !lo.isLiteral() && !hi.isLiteral())); + (ctx->program->gfx_level >= GFX10 || + (ctx->program->gfx_level >= GFX9 && !lo.isLiteral() && !hi.isLiteral())); if (can_use_pack) { Instruction* instr = bld.vop3(aco_opcode::v_pack_b32_f16, def, lo, hi); @@ -1365,7 +1365,7 @@ do_pack_2x16(lower_context* ctx, Builder& bld, Definition def, Operand lo, Opera /* a single alignbyte can be sufficient: hi can be a 32-bit integer constant */ if (lo.physReg().byte() == 2 && hi.physReg().byte() == 0 && (!hi.isConstant() || !Operand::c32(hi.constantValue()).isLiteral() || - ctx->program->chip_class >= GFX10)) { + ctx->program->gfx_level >= GFX10)) { bld.vop3(aco_opcode::v_alignbyte_b32, def, hi, lo, Operand::c32(2u)); return; } @@ -1404,7 +1404,7 @@ do_pack_2x16(lower_context* ctx, Builder& bld, Definition def, Operand lo, Opera assert(hi.physReg().byte() == 0); bld.vop2(aco_opcode::v_lshlrev_b32, def_hi, Operand::c32(16u), hi); hi.setFixed(def.physReg().advance(2)); - } else if (ctx->program->chip_class >= GFX8) { + } else if (ctx->program->gfx_level >= GFX8) { /* either lo or hi can be placed with just a v_mov */ assert(lo.physReg().byte() == 0 || hi.physReg().byte() == 2); Operand& op = lo.physReg().byte() == 0 ? lo : hi; @@ -1413,7 +1413,7 @@ do_pack_2x16(lower_context* ctx, Builder& bld, Definition def, Operand lo, Opera op.setFixed(reg); } - if (ctx->program->chip_class >= GFX8) { + if (ctx->program->gfx_level >= GFX8) { /* either hi or lo are already placed correctly */ if (lo.physReg().reg() == def.physReg().reg()) bld.vop1_sdwa(aco_opcode::v_mov_b32, def_hi, hi); @@ -1467,7 +1467,7 @@ try_coalesce_copies(lower_context* ctx, std::map<PhysReg, copy_operation>& copy_ /* don't create 64-bit copies before GFX10 */ if (copy.bytes >= 4 && copy.def.regClass().type() == RegType::vgpr && - ctx->program->chip_class < GFX10) + ctx->program->gfx_level < GFX10) return; unsigned new_size = copy.bytes + other->second.bytes; @@ -1479,7 +1479,7 @@ try_coalesce_copies(lower_context* ctx, std::map<PhysReg, copy_operation>& copy_ if (!Operand::is_constant_representable(val, new_size, true, copy.def.regClass().type() == RegType::vgpr)) return; - copy.op = Operand::get_const(ctx->program->chip_class, val, new_size); + copy.op = Operand::get_const(ctx->program->gfx_level, val, new_size); } else { if (other->second.op.physReg() != copy.op.physReg().advance(copy.bytes)) return; @@ -1493,7 +1493,7 @@ try_coalesce_copies(lower_context* ctx, std::map<PhysReg, copy_operation>& copy_ void handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context* ctx, - chip_class chip_class, Pseudo_instruction* pi) + amd_gfx_level gfx_level, Pseudo_instruction* pi) { Builder bld(ctx->program, &ctx->instructions); unsigned num_instructions_before = ctx->instructions.size(); @@ -1599,7 +1599,7 @@ handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context* ctx, /* on GFX6/7, we need some small workarounds as there is no * SDWA instruction to do partial register writes */ - if (ctx->program->chip_class < GFX8 && it->second.bytes < 4) { + if (ctx->program->gfx_level < GFX8 && it->second.bytes < 4) { if (it->first.byte() == 0 && it->second.op.physReg().byte() == 0 && !it->second.is_used && pi->opcode == aco_opcode::p_split_vector) { /* Other operations might overwrite the high bits, so change all users @@ -1664,7 +1664,7 @@ handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context* ctx, bool partial_copy = (has_zero_use_bytes == 0xf) || (has_zero_use_bytes == 0xf0); for (std::pair<const PhysReg, copy_operation>& copy : copy_map) { /* on GFX6/7, we can only do copies with full registers */ - if (partial_copy || ctx->program->chip_class <= GFX7) + if (partial_copy || ctx->program->gfx_level <= GFX7) break; for (uint16_t i = 0; i < copy.second.bytes; i++) { /* distance might underflow */ @@ -1790,7 +1790,7 @@ handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context* ctx, } /* GFX6-7 can only swap full registers */ - if (ctx->program->chip_class <= GFX7) + if (ctx->program->gfx_level <= GFX7) swap.bytes = align(swap.bytes, 4); do_swap(ctx, bld, swap, preserve_scc, pi); @@ -1868,7 +1868,7 @@ handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context* ctx, void emit_set_mode(Builder& bld, float_mode new_mode, bool set_round, bool set_denorm) { - if (bld.program->chip_class >= GFX10) { + if (bld.program->gfx_level >= GFX10) { if (set_round) bld.sopp(aco_opcode::s_round_mode, -1, new_mode.round); if (set_denorm) @@ -1938,7 +1938,7 @@ lower_to_hw_instr(Program* program) : RegClass(instr->operands[0].getTemp().type(), def.size()); std::map<PhysReg, copy_operation> copy_operations; copy_operations[def.physReg()] = {Operand(reg, op_rc), def, def.bytes()}; - handle_operands(copy_operations, &ctx, program->chip_class, pi); + handle_operands(copy_operations, &ctx, program->gfx_level, pi); break; } case aco_opcode::p_create_vector: { @@ -1967,7 +1967,7 @@ lower_to_hw_instr(Program* program) copy_operations[def.physReg()] = {op, def, op.bytes()}; reg.reg_b += op.bytes(); } - handle_operands(copy_operations, &ctx, program->chip_class, pi); + handle_operands(copy_operations, &ctx, program->gfx_level, pi); break; } case aco_opcode::p_split_vector: { @@ -1982,7 +1982,7 @@ lower_to_hw_instr(Program* program) copy_operations[def.physReg()] = {op, def, def.bytes()}; reg.reg_b += def.bytes(); } - handle_operands(copy_operations, &ctx, program->chip_class, pi); + handle_operands(copy_operations, &ctx, program->gfx_level, pi); break; } case aco_opcode::p_parallelcopy: @@ -1993,7 +1993,7 @@ lower_to_hw_instr(Program* program) copy_operations[instr->definitions[j].physReg()] = { instr->operands[j], instr->definitions[j], instr->operands[j].bytes()}; } - handle_operands(copy_operations, &ctx, program->chip_class, pi); + handle_operands(copy_operations, &ctx, program->gfx_level, pi); break; } case aco_opcode::p_exit_early_if: { @@ -2030,7 +2030,7 @@ lower_to_hw_instr(Program* program) bld.reset(discard_block); bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1), 0, - program->chip_class >= GFX11 ? V_008DFC_SQ_EXP_MRT : V_008DFC_SQ_EXP_NULL, + program->gfx_level >= GFX11 ? V_008DFC_SQ_EXP_MRT : V_008DFC_SQ_EXP_NULL, false, true, true); bld.sopp(aco_opcode::s_endpgm); @@ -2072,7 +2072,7 @@ lower_to_hw_instr(Program* program) std::map<PhysReg, copy_operation> copy_operations; copy_operations[instr->definitions[0].physReg()] = { instr->operands[0], instr->definitions[0], instr->definitions[0].bytes()}; - handle_operands(copy_operations, &ctx, program->chip_class, pi); + handle_operands(copy_operations, &ctx, program->gfx_level, pi); } else { assert(instr->operands[0].regClass().type() == RegType::vgpr); assert(instr->definitions[0].regClass().type() == RegType::sgpr); @@ -2086,9 +2086,9 @@ lower_to_hw_instr(Program* program) break; } case aco_opcode::p_bpermute: { - if (ctx.program->chip_class <= GFX7) + if (ctx.program->gfx_level <= GFX7) emit_gfx6_bpermute(program, instr, bld); - else if (ctx.program->chip_class >= GFX10 && ctx.program->wave_size == 64) + else if (ctx.program->gfx_level >= GFX10 && ctx.program->wave_size == 64) emit_gfx10_wave64_bpermute(program, instr, bld); else unreachable("Current hardware supports ds_bpermute, don't emit p_bpermute."); @@ -2129,7 +2129,7 @@ lower_to_hw_instr(Program* program) bld.def(s1, scc), op, Operand::c32((bits << 16) | offset)); } } else if ((dst.regClass() == v1 && op.regClass() == v1) || - ctx.program->chip_class <= GFX7) { + ctx.program->gfx_level <= GFX7) { assert(op.physReg().byte() == 0 && dst.physReg().byte() == 0); if (offset == (32 - bits) && op.regClass() != s1) { bld.vop2(signext ? aco_opcode::v_ashrrev_i32 : aco_opcode::v_lshrrev_b32, dst, @@ -2171,13 +2171,13 @@ lower_to_hw_instr(Program* program) bld.sop2(aco_opcode::s_lshl_b32, dst, bld.def(s1, scc), Operand(dst.physReg(), s1), Operand::c32(offset)); } - } else if (dst.regClass() == v1 || ctx.program->chip_class <= GFX7) { + } else if (dst.regClass() == v1 || ctx.program->gfx_level <= GFX7) { if (offset == (dst.bytes() * 8u - bits)) { bld.vop2(aco_opcode::v_lshlrev_b32, dst, Operand::c32(offset), op); } else if (offset == 0) { bld.vop3(aco_opcode::v_bfe_u32, dst, op, Operand::zero(), Operand::c32(bits)); - } else if (program->chip_class >= GFX9 || - (op.regClass() != s1 && program->chip_class >= GFX8)) { + } else if (program->gfx_level >= GFX9 || + (op.regClass() != s1 && program->gfx_level >= GFX8)) { bld.vop1_sdwa(aco_opcode::v_mov_b32, dst, op).instr->sdwa().dst_sel = SubdwordSel(bits / 8, offset / 8, false); } else { @@ -2237,7 +2237,7 @@ lower_to_hw_instr(Program* program) } else if (inst->isVALU() || inst->isVINTRP()) { num_vector++; /* VALU which writes SGPRs are always executed on GFX10+ */ - if (ctx.program->chip_class >= GFX10) { + if (ctx.program->gfx_level >= GFX10) { for (Definition& def : inst->definitions) { if (def.regClass().type() == RegType::sgpr) num_scalar++; @@ -2259,7 +2259,7 @@ lower_to_hw_instr(Program* program) /* Under these conditions, we shouldn't remove the branch */ unsigned est_cycles; - if (ctx.program->chip_class >= GFX10) + if (ctx.program->gfx_level >= GFX10) est_cycles = num_scalar * 2 + num_vector; else est_cycles = num_scalar * 4 + num_vector * 4; diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp index 104dea4041f..7f79a541d8c 100644 --- a/src/amd/compiler/aco_optimizer.cpp +++ b/src/amd/compiler/aco_optimizer.cpp @@ -193,15 +193,15 @@ struct ssa_info { bool is_vec() { return label & label_vec; } - void set_constant(chip_class chip, uint64_t constant) + void set_constant(amd_gfx_level gfx_level, uint64_t constant) { Operand op16 = Operand::c16(constant); - Operand op32 = Operand::get_const(chip, constant, 4); + Operand op32 = Operand::get_const(gfx_level, constant, 4); add_label(label_literal); val = constant; /* check that no upper bits are lost in case of packed 16bit constants */ - if (chip >= GFX8 && !op16.isLiteral() && op16.constantValue64() == constant) + if (gfx_level >= GFX8 && !op16.isLiteral() && op16.constantValue64() == constant) add_label(label_constant_16bit); if (!op32.isLiteral()) @@ -515,7 +515,7 @@ can_use_VOP3(opt_ctx& ctx, const aco_ptr<Instruction>& instr) if (instr->isVOP3P()) return false; - if (instr->operands.size() && instr->operands[0].isLiteral() && ctx.program->chip_class < GFX10) + if (instr->operands.size() && instr->operands[0].isLiteral() && ctx.program->gfx_level < GFX10) return false; if (instr->isDPP() || instr->isSDWA()) @@ -546,7 +546,7 @@ pseudo_propagate_temp(opt_ctx& ctx, aco_ptr<Instruction>& instr, Temp temp, unsi return false; bool can_accept_sgpr = - ctx.program->chip_class >= GFX9 || + ctx.program->gfx_level >= GFX9 || std::none_of(instr->definitions.begin(), instr->definitions.end(), [](const Definition& def) { return def.regClass().is_subdword(); }); @@ -597,7 +597,7 @@ pseudo_propagate_temp(opt_ctx& ctx, aco_ptr<Instruction>& instr, Temp temp, unsi bool can_apply_sgprs(opt_ctx& ctx, aco_ptr<Instruction>& instr) { - if (instr->isSDWA() && ctx.program->chip_class < GFX9) + if (instr->isSDWA() && ctx.program->gfx_level < GFX9) return false; return instr->opcode != aco_opcode::v_readfirstlane_b32 && instr->opcode != aco_opcode::v_readlane_b32 && @@ -642,7 +642,7 @@ is_operand_vgpr(Operand op) void to_SDWA(opt_ctx& ctx, aco_ptr<Instruction>& instr) { - aco_ptr<Instruction> tmp = convert_to_SDWA(ctx.program->chip_class, instr); + aco_ptr<Instruction> tmp = convert_to_SDWA(ctx.program->gfx_level, instr); if (!tmp) return; @@ -695,7 +695,7 @@ valu_can_accept_vgpr(aco_ptr<Instruction>& instr, unsigned operand) bool check_vop3_operands(opt_ctx& ctx, unsigned num_operands, Operand* operands) { - int limit = ctx.program->chip_class >= GFX10 ? 2 : 1; + int limit = ctx.program->gfx_level >= GFX10 ? 2 : 1; Operand literal32(s1); Operand literal64(s2); unsigned num_sgprs = 0; @@ -714,7 +714,7 @@ check_vop3_operands(opt_ctx& ctx, unsigned num_operands, Operand* operands) return false; } } else if (op.isLiteral()) { - if (ctx.program->chip_class < GFX10) + if (ctx.program->gfx_level < GFX10) return false; if (!literal32.isUndefined() && literal32.constantValue() != op.constantValue()) @@ -834,12 +834,12 @@ smem_combine(opt_ctx& ctx, aco_ptr<Instruction>& instr) uint32_t offset; bool prevent_overflow = smem.operands[0].size() > 2 || smem.prevent_overflow; if (info.is_constant_or_literal(32) && - ((ctx.program->chip_class == GFX6 && info.val <= 0x3FF) || - (ctx.program->chip_class == GFX7 && info.val <= 0xFFFFFFFF) || - (ctx.program->chip_class >= GFX8 && info.val <= 0xFFFFF))) { + ((ctx.program->gfx_level == GFX6 && info.val <= 0x3FF) || + (ctx.program->gfx_level == GFX7 && info.val <= 0xFFFFFFFF) || + (ctx.program->gfx_level >= GFX8 && info.val <= 0xFFFFF))) { instr->operands[1] = Operand::c32(info.val); } else if (parse_base_offset(ctx, instr.get(), 1, &base, &offset, prevent_overflow) && - base.regClass() == s1 && offset <= 0xFFFFF && ctx.program->chip_class >= GFX9 && + base.regClass() == s1 && offset <= 0xFFFFF && ctx.program->gfx_level >= GFX9 && offset % 4u == 0) { bool soe = smem.operands.size() >= (!smem.definitions.empty() ? 3 : 4); if (soe) { @@ -895,7 +895,7 @@ get_constant_op(opt_ctx& ctx, ssa_info info, uint32_t bits) { if (bits == 64) return Operand::c32_or_c64(info.val, true); - return Operand::get_const(ctx.program->chip_class, info.val, bits / 8u); + return Operand::get_const(ctx.program->gfx_level, info.val, bits / 8u); } void @@ -1023,13 +1023,13 @@ can_apply_extract(opt_ctx& ctx, aco_ptr<Instruction>& instr, unsigned idx, ssa_i return true; } else if (instr->opcode == aco_opcode::v_cvt_f32_u32 && sel.size() == 1 && !sel.sign_extend()) { return true; - } else if (can_use_SDWA(ctx.program->chip_class, instr, true) && - (tmp.type() == RegType::vgpr || ctx.program->chip_class >= GFX9)) { + } else if (can_use_SDWA(ctx.program->gfx_level, instr, true) && + (tmp.type() == RegType::vgpr || ctx.program->gfx_level >= GFX9)) { if (instr->isSDWA() && instr->sdwa().sel[idx] != SubdwordSel::dword) return false; return true; } else if (instr->isVOP3() && sel.size() == 2 && - can_use_opsel(ctx.program->chip_class, instr->opcode, idx) && + can_use_opsel(ctx.program->gfx_level, instr->opcode, idx) && !(instr->vop3().opsel & (1 << idx))) { return true; } else if (instr->opcode == aco_opcode::p_extract) { @@ -1079,8 +1079,8 @@ apply_extract(opt_ctx& ctx, aco_ptr<Instruction>& instr, unsigned idx, ssa_info& (sel.size() == 1 && instr->operands[0].constantValue() >= 24u))) { /* The undesireable upper bits are already shifted out. */ return; - } else if (can_use_SDWA(ctx.program->chip_class, instr, true) && - (tmp.type() == RegType::vgpr || ctx.program->chip_class >= GFX9)) { + } else if (can_use_SDWA(ctx.program->gfx_level, instr, true) && + (tmp.type() == RegType::vgpr || ctx.program->gfx_level >= GFX9)) { to_SDWA(ctx, instr); static_cast<SDWA_instruction*>(instr.get())->sel[idx] = sel; } else if (instr->isVOP3()) { @@ -1126,7 +1126,7 @@ check_sdwa_extract(opt_ctx& ctx, aco_ptr<Instruction>& instr) bool does_fp_op_flush_denorms(opt_ctx& ctx, aco_opcode op) { - if (ctx.program->chip_class <= GFX8) { + if (ctx.program->gfx_level <= GFX8) { switch (op) { case aco_opcode::v_min_f32: case aco_opcode::v_max_f32: @@ -1318,7 +1318,7 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) } if (info.is_constant(bits) && alu_can_accept_constant(instr->opcode, i) && - (!instr->isSDWA() || ctx.program->chip_class >= GFX9)) { + (!instr->isSDWA() || ctx.program->gfx_level >= GFX9)) { Operand op = get_constant_op(ctx, info, bits); perfwarn(ctx.program, instr->opcode == aco_opcode::v_cndmask_b32 && i == 2, "v_cndmask_b32 with a constant selector", instr.get()); @@ -1353,7 +1353,7 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) * scratch accesses and other accesses and swizzling changing how * addressing works significantly, this probably applies to swizzled * MUBUF accesses. */ - bool vaddr_prevent_overflow = mubuf.swizzled && ctx.program->chip_class < GFX9; + bool vaddr_prevent_overflow = mubuf.swizzled && ctx.program->gfx_level < GFX9; if (mubuf.offen && i == 1 && info.is_constant_or_literal(32) && mubuf.offset + info.val < 4096) { @@ -1388,7 +1388,7 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) DS_instruction& ds = instr->ds(); Temp base; uint32_t offset; - bool has_usable_ds_offset = ctx.program->chip_class >= GFX7; + bool has_usable_ds_offset = ctx.program->gfx_level >= GFX7; if (has_usable_ds_offset && i == 0 && parse_base_offset(ctx, instr.get(), i, &base, &offset, false) && base.regClass() == instr->operands[i].regClass() && @@ -1530,7 +1530,7 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) uint64_t val = info.val; for (Definition def : instr->definitions) { uint32_t mask = u_bit_consecutive(0, def.bytes() * 8u); - ctx.info[def.tempId()].set_constant(ctx.program->chip_class, val & mask); + ctx.info[def.tempId()].set_constant(ctx.program->gfx_level, val & mask); val >>= def.bytes() * 8u; } break; @@ -1562,7 +1562,7 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) Operand vec_op = vec->operands[vec_index]; if (vec_op.isConstant()) { - ctx.info[instr->definitions[i].tempId()].set_constant(ctx.program->chip_class, + ctx.info[instr->definitions[i].tempId()].set_constant(ctx.program->gfx_level, vec_op.constantValue64()); } else if (vec_op.isUndefined()) { ctx.info[instr->definitions[i].tempId()].set_undefined(); @@ -1598,7 +1598,7 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) uint32_t mask = u_bit_consecutive(0, instr->definitions[0].bytes() * 8u); uint32_t val = (info.val >> (dst_offset * 8u)) & mask; instr->operands[0] = - Operand::get_const(ctx.program->chip_class, val, instr->definitions[0].bytes()); + Operand::get_const(ctx.program->gfx_level, val, instr->definitions[0].bytes()); ; } @@ -1648,7 +1648,7 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) // TODO } else if (instr->operands[0].isConstant()) { ctx.info[instr->definitions[0].tempId()].set_constant( - ctx.program->chip_class, instr->operands[0].constantValue64()); + ctx.program->gfx_level, instr->operands[0].constantValue64()); } else if (instr->operands[0].isTemp()) { ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp()); if (ctx.info[instr->operands[0].tempId()].is_canonicalized()) @@ -1668,7 +1668,7 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) break; case aco_opcode::p_is_helper: if (!ctx.program->needs_wqm) - ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, 0u); + ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->gfx_level, 0u); break; case aco_opcode::v_mul_f64: ctx.info[instr->definitions[0].tempId()].set_mul(instr.get()); break; case aco_opcode::v_mul_f16: @@ -1718,7 +1718,7 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) (!(fp16 ? ctx.fp_mode.preserve_signed_zero_inf_nan16_64 : ctx.fp_mode.preserve_signed_zero_inf_nan32) || instr->opcode == aco_opcode::v_mul_legacy_f32)) { /* 0.0 */ - ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, 0u); + ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->gfx_level, 0u); } else { continue; } @@ -2048,7 +2048,7 @@ combine_ordering_test(opt_ctx& ctx, aco_ptr<Instruction>& instr) if (op[1].type() == RegType::sgpr) std::swap(op[0], op[1]); unsigned num_sgprs = (op[0].type() == RegType::sgpr) + (op[1].type() == RegType::sgpr); - if (num_sgprs > (ctx.program->chip_class >= GFX10 ? 2 : 1)) + if (num_sgprs > (ctx.program->gfx_level >= GFX10 ? 2 : 1)) return false; ctx.uses[op[0].id()]++; @@ -2720,7 +2720,7 @@ combine_add_sub_b2i(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode new_op if (instr->operands[!i].isTemp() && instr->operands[!i].getTemp().type() == RegType::vgpr) { new_instr.reset(create_instruction<VOP2_instruction>(new_op, Format::VOP2, 3, 2)); - } else if (ctx.program->chip_class >= GFX10 || + } else if (ctx.program->gfx_level >= GFX10 || (instr->operands[!i].isConstant() && !instr->operands[!i].isLiteral())) { new_instr.reset( create_instruction<VOP3_instruction>(new_op, asVOP3(Format::VOP2), 3, 2)); @@ -2959,7 +2959,7 @@ apply_sgprs(opt_ctx& ctx, aco_ptr<Instruction>& instr) operand_mask |= 1u << i; } unsigned max_sgprs = 1; - if (ctx.program->chip_class >= GFX10 && !is_shift64) + if (ctx.program->gfx_level >= GFX10 && !is_shift64) max_sgprs = 2; if (has_literal) max_sgprs--; @@ -3066,7 +3066,7 @@ apply_omod_clamp(opt_ctx& ctx, aco_ptr<Instruction>& instr) return false; /* omod flushes -0 to +0 and has no effect if denormals are enabled. SDWA omod is GFX9+. */ - bool can_use_omod = (can_vop3 || ctx.program->chip_class >= GFX9) && !instr->isVOP3P(); + bool can_use_omod = (can_vop3 || ctx.program->gfx_level >= GFX9) && !instr->isVOP3P(); if (instr->definitions[0].bytes() == 4) can_use_omod = can_use_omod && ctx.fp_mode.denorm32 == 0 && !ctx.fp_mode.preserve_signed_zero_inf_nan32; @@ -3133,13 +3133,13 @@ apply_insert(opt_ctx& ctx, aco_ptr<Instruction>& instr) assert(sel); if (instr->isVOP3() && sel.size() == 2 && !sel.sign_extend() && - can_use_opsel(ctx.program->chip_class, instr->opcode, -1)) { + can_use_opsel(ctx.program->gfx_level, instr->opcode, -1)) { if (instr->vop3().opsel & (1 << 3)) return false; if (sel.offset()) instr->vop3().opsel |= 1 << 3; } else { - if (!can_use_SDWA(ctx.program->chip_class, instr, true)) + if (!can_use_SDWA(ctx.program->gfx_level, instr, true)) return false; to_SDWA(ctx, instr); @@ -3224,7 +3224,7 @@ combine_and_subbrev(opt_ctx& ctx, aco_ptr<Instruction>& instr) instr->operands[!i].getTemp().type() == RegType::vgpr) { new_instr.reset( create_instruction<VOP2_instruction>(aco_opcode::v_cndmask_b32, Format::VOP2, 3, 1)); - } else if (ctx.program->chip_class >= GFX10 || + } else if (ctx.program->gfx_level >= GFX10 || (instr->operands[!i].isConstant() && !instr->operands[!i].isLiteral())) { new_instr.reset(create_instruction<VOP3_instruction>(aco_opcode::v_cndmask_b32, asVOP3(Format::VOP2), 3, 1)); @@ -3484,11 +3484,11 @@ combine_vop3p(opt_ctx& ctx, aco_ptr<Instruction>& instr) bool can_use_mad_mix(opt_ctx& ctx, aco_ptr<Instruction>& instr) { - if (ctx.program->chip_class < GFX9) + if (ctx.program->gfx_level < GFX9) return false; /* v_mad_mix* on GFX9 always flushes denormals for 16-bit inputs/outputs */ - if (ctx.program->chip_class == GFX9 && ctx.fp_mode.denorm16_64) + if (ctx.program->gfx_level == GFX9 && ctx.fp_mode.denorm16_64) return false; switch (instr->opcode) { @@ -3808,12 +3808,12 @@ combine_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) bool legacy = info.instr->opcode == aco_opcode::v_mul_legacy_f32; bool mad_mix = is_add_mix || info.instr->isVOP3P(); - bool has_fma = mad16 || mad64 || (legacy && ctx.program->chip_class >= GFX10_3) || + bool has_fma = mad16 || mad64 || (legacy && ctx.program->gfx_level >= GFX10_3) || (mad32 && !legacy && !mad_mix && ctx.program->dev.has_fast_fma32) || (mad_mix && ctx.program->dev.fused_mad_mix); bool has_mad = mad_mix ? !ctx.program->dev.fused_mad_mix - : ((mad32 && ctx.program->chip_class < GFX10_3) || - (mad16 && ctx.program->chip_class <= GFX9)); + : ((mad32 && ctx.program->gfx_level < GFX10_3) || + (mad16 && ctx.program->gfx_level <= GFX9)); bool can_use_fma = has_fma && !info.instr->definitions[0].isPrecise() && !instr->definitions[0].isPrecise(); bool can_use_mad = @@ -3938,13 +3938,13 @@ combine_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) } else { aco_opcode mad_op = emit_fma ? aco_opcode::v_fma_f32 : aco_opcode::v_mad_f32; if (mul_instr->opcode == aco_opcode::v_mul_legacy_f32) { - assert(emit_fma == (ctx.program->chip_class >= GFX10_3)); + assert(emit_fma == (ctx.program->gfx_level >= GFX10_3)); mad_op = emit_fma ? aco_opcode::v_fma_legacy_f32 : aco_opcode::v_mad_legacy_f32; } else if (mad16) { - mad_op = emit_fma ? (ctx.program->chip_class == GFX8 ? aco_opcode::v_fma_legacy_f16 - : aco_opcode::v_fma_f16) - : (ctx.program->chip_class == GFX8 ? aco_opcode::v_mad_legacy_f16 - : aco_opcode::v_mad_f16); + mad_op = emit_fma ? (ctx.program->gfx_level == GFX8 ? aco_opcode::v_fma_legacy_f16 + : aco_opcode::v_fma_f16) + : (ctx.program->gfx_level == GFX8 ? aco_opcode::v_mad_legacy_f16 + : aco_opcode::v_mad_f16); } else if (mad64) { mad_op = aco_opcode::v_fma_f64; } @@ -3992,14 +3992,14 @@ combine_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) return; } } - } else if (instr->opcode == aco_opcode::v_or_b32 && ctx.program->chip_class >= GFX9) { + } else if (instr->opcode == aco_opcode::v_or_b32 && ctx.program->gfx_level >= GFX9) { if (combine_three_valu_op(ctx, instr, aco_opcode::s_or_b32, aco_opcode::v_or3_b32, "012", 1 | 2)) { } else if (combine_three_valu_op(ctx, instr, aco_opcode::v_or_b32, aco_opcode::v_or3_b32, "012", 1 | 2)) { } else if (combine_add_or_then_and_lshl(ctx, instr)) { } - } else if (instr->opcode == aco_opcode::v_xor_b32 && ctx.program->chip_class >= GFX10) { + } else if (instr->opcode == aco_opcode::v_xor_b32 && ctx.program->gfx_level >= GFX10) { if (combine_three_valu_op(ctx, instr, aco_opcode::v_xor_b32, aco_opcode::v_xor3_b32, "012", 1 | 2)) { } else if (combine_three_valu_op(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::v_xor3_b32, @@ -4008,7 +4008,7 @@ combine_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) } else if (instr->opcode == aco_opcode::v_add_u16) { combine_three_valu_op( ctx, instr, aco_opcode::v_mul_lo_u16, - ctx.program->chip_class == GFX8 ? aco_opcode::v_mad_legacy_u16 : aco_opcode::v_mad_u16, + ctx.program->gfx_level == GFX8 ? aco_opcode::v_mad_legacy_u16 : aco_opcode::v_mad_u16, "120", 1 | 2); } else if (instr->opcode == aco_opcode::v_add_u16_e64) { combine_three_valu_op(ctx, instr, aco_opcode::v_mul_lo_u16_e64, aco_opcode::v_mad_u16, "120", @@ -4018,7 +4018,7 @@ combine_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) } else if (combine_add_bcnt(ctx, instr)) { } else if (combine_three_valu_op(ctx, instr, aco_opcode::v_mul_u32_u24, aco_opcode::v_mad_u32_u24, "120", 1 | 2)) { - } else if (ctx.program->chip_class >= GFX9 && !instr->usesModifiers()) { + } else if (ctx.program->gfx_level >= GFX9 && !instr->usesModifiers()) { if (combine_three_valu_op(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::v_xad_u32, "120", 1 | 2)) { } else if (combine_three_valu_op(ctx, instr, aco_opcode::v_xor_b32, aco_opcode::v_xad_u32, @@ -4052,11 +4052,11 @@ combine_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) instr->opcode == aco_opcode::v_subrev_co_u32 || instr->opcode == aco_opcode::v_subrev_co_u32_e64) { combine_add_sub_b2i(ctx, instr, aco_opcode::v_subbrev_co_u32, 1); - } else if (instr->opcode == aco_opcode::v_lshlrev_b32 && ctx.program->chip_class >= GFX9) { + } else if (instr->opcode == aco_opcode::v_lshlrev_b32 && ctx.program->gfx_level >= GFX9) { combine_three_valu_op(ctx, instr, aco_opcode::v_add_u32, aco_opcode::v_add_lshl_u32, "120", 2); } else if ((instr->opcode == aco_opcode::s_add_u32 || instr->opcode == aco_opcode::s_add_i32) && - ctx.program->chip_class >= GFX9) { + ctx.program->gfx_level >= GFX9) { combine_salu_lshl_add(ctx, instr); } else if (instr->opcode == aco_opcode::s_not_b32 || instr->opcode == aco_opcode::s_not_b64) { combine_salu_not_bitwise(ctx, instr); @@ -4080,7 +4080,7 @@ combine_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) aco_opcode min, max, min3, max3, med3; bool some_gfx9_only; if (get_minmax_info(instr->opcode, &min, &max, &min3, &max3, &med3, &some_gfx9_only) && - (!some_gfx9_only || ctx.program->chip_class >= GFX9)) { + (!some_gfx9_only || ctx.program->gfx_level >= GFX9)) { if (combine_minmax(ctx, instr, instr->opcode == min ? max : min, instr->opcode == min ? min3 : max3)) { } else { @@ -4236,7 +4236,7 @@ select_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) instr->opcode != aco_opcode::v_fma_legacy_f32) { /* FMA can only take literals on GFX10+ */ if ((instr->opcode == aco_opcode::v_fma_f32 || instr->opcode == aco_opcode::v_fma_f16) && - ctx.program->chip_class < GFX10) + ctx.program->gfx_level < GFX10) return; /* There are no v_fmaak_legacy_f16/v_fmamk_legacy_f16 and on chips where VOP3 can take * literals (GFX10+), these instructions don't exist. @@ -4261,7 +4261,7 @@ select_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) /* Encoding limitations requires a VGPR operand. The constant bus limitations before * GFX10 disallows SGPRs. */ - if ((!has_sgpr || ctx.program->chip_class >= GFX10) && has_vgpr) { + if ((!has_sgpr || ctx.program->gfx_level >= GFX10) && has_vgpr) { literal_idx = 2; literal_uses = ctx.uses[instr->operands[2].tempId()]; } @@ -4275,7 +4275,7 @@ select_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) continue; /* The constant bus limitations before GFX10 disallows SGPRs. */ - if (ctx.program->chip_class < GFX10 && instr->operands[!i].isTemp() && + if (ctx.program->gfx_level < GFX10 && instr->operands[!i].isTemp() && instr->operands[!i].getTemp().type() == RegType::sgpr) continue; @@ -4385,8 +4385,8 @@ select_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) } } - if (instr->isSDWA() || (instr->isVOP3() && ctx.program->chip_class < GFX10) || - (instr->isVOP3P() && ctx.program->chip_class < GFX10)) + if (instr->isSDWA() || (instr->isVOP3() && ctx.program->gfx_level < GFX10) || + (instr->isVOP3P() && ctx.program->gfx_level < GFX10)) return; /* some encodings can't ever take literals */ /* we do not apply the literals yet as we don't know if it is profitable */ @@ -4397,7 +4397,7 @@ select_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) Operand literal(s1); unsigned num_operands = 1; if (instr->isSALU() || - (ctx.program->chip_class >= GFX10 && (can_use_VOP3(ctx, instr) || instr->isVOP3P()))) + (ctx.program->gfx_level >= GFX10 && (can_use_VOP3(ctx, instr) || instr->isVOP3P()))) num_operands = instr->operands.size(); /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */ else if (instr->isVALU() && instr->operands.size() >= 3) @@ -4442,7 +4442,7 @@ select_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr) instr->opcode == aco_opcode::v_lshrrev_b64 || instr->opcode == aco_opcode::v_ashrrev_i64; unsigned const_bus_limit = instr->isVALU() ? 1 : UINT32_MAX; - if (ctx.program->chip_class >= GFX10 && !is_shift64) + if (ctx.program->gfx_level >= GFX10 && !is_shift64) const_bus_limit = 2; unsigned num_sgprs = !!sgpr_ids[0] + !!sgpr_ids[1]; diff --git a/src/amd/compiler/aco_optimizer_postRA.cpp b/src/amd/compiler/aco_optimizer_postRA.cpp index 1953c00d4a6..726cff40a0c 100644 --- a/src/amd/compiler/aco_optimizer_postRA.cpp +++ b/src/amd/compiler/aco_optimizer_postRA.cpp @@ -194,7 +194,7 @@ try_apply_branch_vcc(pr_opt_ctx& ctx, aco_ptr<Instruction>& instr) */ /* Don't try to optimize this on GFX6-7 because SMEM may corrupt the vccz bit. */ - if (ctx.program->chip_class < GFX8) + if (ctx.program->gfx_level < GFX8) return; if (instr->format != Format::PSEUDO_BRANCH || instr->operands.size() == 0 || diff --git a/src/amd/compiler/aco_print_asm.cpp b/src/amd/compiler/aco_print_asm.cpp index 8cbd77cd7ac..2535de23076 100644 --- a/src/amd/compiler/aco_print_asm.cpp +++ b/src/amd/compiler/aco_print_asm.cpp @@ -100,9 +100,9 @@ print_constant_data(FILE* output, Program* program) * Determines the GPU type to use for CLRXdisasm */ const char* -to_clrx_device_name(chip_class cc, radeon_family family) +to_clrx_device_name(amd_gfx_level gfx_level, radeon_family family) { - switch (cc) { + switch (gfx_level) { case GFX6: switch (family) { case CHIP_TAHITI: return "tahiti"; @@ -182,7 +182,7 @@ print_asm_clrx(Program* program, std::vector<uint32_t>& binary, unsigned exec_si FILE* p; int fd; - const char* gpu_type = to_clrx_device_name(program->chip_class, program->family); + const char* gpu_type = to_clrx_device_name(program->gfx_level, program->family); /* Dump the binary into a temporary file. */ fd = mkstemp(path); @@ -268,14 +268,14 @@ fail: #ifdef LLVM_AVAILABLE std::pair<bool, size_t> -disasm_instr(chip_class chip, LLVMDisasmContextRef disasm, uint32_t* binary, unsigned exec_size, - size_t pos, char* outline, unsigned outline_size) +disasm_instr(amd_gfx_level gfx_level, LLVMDisasmContextRef disasm, uint32_t* binary, + unsigned exec_size, size_t pos, char* outline, unsigned outline_size) { size_t l = LLVMDisasmInstruction(disasm, (uint8_t*)&binary[pos], (exec_size - pos) * sizeof(uint32_t), pos * 4, outline, outline_size); - if (chip >= GFX10 && l == 8 && ((binary[pos] & 0xffff0000) == 0xd7610000) && + if (gfx_level >= GFX10 && l == 8 && ((binary[pos] & 0xffff0000) == 0xd7610000) && ((binary[pos + 1] & 0x1ff) == 0xff)) { /* v_writelane with literal uses 3 dwords but llvm consumes only 2 */ l += 4; @@ -284,16 +284,19 @@ disasm_instr(chip_class chip, LLVMDisasmContextRef disasm, uint32_t* binary, uns bool invalid = false; size_t size; if (!l && - ((chip >= GFX9 && (binary[pos] & 0xffff8000) == 0xd1348000) || /* v_add_u32_e64 + clamp */ - (chip >= GFX10 && (binary[pos] & 0xffff8000) == 0xd7038000) || /* v_add_u16_e64 + clamp */ - (chip <= GFX9 && (binary[pos] & 0xffff8000) == 0xd1268000) || /* v_add_u16_e64 + clamp */ - (chip >= GFX10 && (binary[pos] & 0xffff8000) == 0xd76d8000) || /* v_add3_u32 + clamp */ - (chip == GFX9 && (binary[pos] & 0xffff8000) == 0xd1ff8000)) /* v_add3_u32 + clamp */) { + ((gfx_level >= GFX9 && + (binary[pos] & 0xffff8000) == 0xd1348000) || /* v_add_u32_e64 + clamp */ + (gfx_level >= GFX10 && + (binary[pos] & 0xffff8000) == 0xd7038000) || /* v_add_u16_e64 + clamp */ + (gfx_level <= GFX9 && + (binary[pos] & 0xffff8000) == 0xd1268000) || /* v_add_u16_e64 + clamp */ + (gfx_level >= GFX10 && (binary[pos] & 0xffff8000) == 0xd76d8000) || /* v_add3_u32 + clamp */ + (gfx_level == GFX9 && (binary[pos] & 0xffff8000) == 0xd1ff8000)) /* v_add3_u32 + clamp */) { strcpy(outline, "\tinteger addition + clamp"); - bool has_literal = chip >= GFX10 && (((binary[pos + 1] & 0x1ff) == 0xff) || - (((binary[pos + 1] >> 9) & 0x1ff) == 0xff)); + bool has_literal = gfx_level >= GFX10 && (((binary[pos + 1] & 0x1ff) == 0xff) || + (((binary[pos + 1] >> 9) & 0x1ff) == 0xff)); size = 2 + has_literal; - } else if (chip >= GFX10 && l == 4 && ((binary[pos] & 0xfe0001ff) == 0x020000f9)) { + } else if (gfx_level >= GFX10 && l == 4 && ((binary[pos] & 0xfe0001ff) == 0x020000f9)) { strcpy(outline, "\tv_cndmask_b32 + sdwa"); size = 2; } else if (!l) { @@ -308,11 +311,11 @@ disasm_instr(chip_class chip, LLVMDisasmContextRef disasm, uint32_t* binary, uns /* See: https://github.com/GPUOpen-Tools/radeon_gpu_profiler/issues/65 and * https://github.com/llvm/llvm-project/issues/38652 */ - if (chip == GFX9 && (binary[pos] & 0xfc024000) == 0xc0024000) { + if (gfx_level == GFX9 && (binary[pos] & 0xfc024000) == 0xc0024000) { /* SMEM with IMM=1 and SOE=1: LLVM ignores SOFFSET */ size_t len = strlen(outline); snprintf(outline + len, outline_size - len, ", s%u", binary[pos + 1] >> 25); - } else if (chip >= GFX10 && (binary[pos] & 0xfc000000) == 0xf4000000 && + } else if (gfx_level >= GFX10 && (binary[pos] & 0xfc000000) == 0xf4000000 && (binary[pos + 1] & 0xfe000000) != 0xfa000000) { /* SMEM non-NULL SOFFSET: LLVM ignores OFFSET */ uint32_t offset = binary[pos + 1] & 0x1fffff; @@ -344,7 +347,7 @@ print_asm_llvm(Program* program, std::vector<uint32_t>& binary, unsigned exec_si } const char* features = ""; - if (program->chip_class >= GFX10 && program->wave_size == 64) { + if (program->gfx_level >= GFX10 && program->wave_size == 64) { features = "+wavefrontsize64"; } @@ -376,7 +379,7 @@ print_asm_llvm(Program* program, std::vector<uint32_t>& binary, unsigned exec_si print_block_markers(output, program, referenced_blocks, &next_block, pos); char outline[1024]; - std::pair<bool, size_t> res = disasm_instr(program->chip_class, disasm, binary.data(), + std::pair<bool, size_t> res = disasm_instr(program->gfx_level, disasm, binary.data(), exec_size, pos, outline, sizeof(outline)); invalid |= res.first; @@ -402,7 +405,7 @@ bool check_print_asm_support(Program* program) { #ifdef LLVM_AVAILABLE - if (program->chip_class >= GFX8) { + if (program->gfx_level >= GFX8) { /* LLVM disassembler only supports GFX8+ */ return true; } @@ -410,7 +413,7 @@ check_print_asm_support(Program* program) #ifndef _WIN32 /* Check if CLRX disassembler binary is available and can disassemble the program */ - return to_clrx_device_name(program->chip_class, program->family) && + return to_clrx_device_name(program->gfx_level, program->family) && system("clrxdisasm --version") == 0; #else return false; @@ -422,7 +425,7 @@ bool print_asm(Program* program, std::vector<uint32_t>& binary, unsigned exec_size, FILE* output) { #ifdef LLVM_AVAILABLE - if (program->chip_class >= GFX8) { + if (program->gfx_level >= GFX8) { return print_asm_llvm(program, binary, exec_size, output); } #endif diff --git a/src/amd/compiler/aco_print_ir.cpp b/src/amd/compiler/aco_print_ir.cpp index 2b92eff8101..aec35c219ed 100644 --- a/src/amd/compiler/aco_print_ir.cpp +++ b/src/amd/compiler/aco_print_ir.cpp @@ -284,7 +284,7 @@ print_instr_format_specific(const Instruction* instr, FILE* output) uint16_t imm = instr->sopp().imm; switch (instr->opcode) { case aco_opcode::s_waitcnt: { - /* we usually should check the chip class for vmcnt/lgkm, but + /* we usually should check the gfx level for vmcnt/lgkm, but * insert_waitcnt() should fill it in regardless. */ unsigned vmcnt = (imm & 0xF) | ((imm & (0x3 << 14)) >> 10); if (vmcnt != 63) diff --git a/src/amd/compiler/aco_reduce_assign.cpp b/src/amd/compiler/aco_reduce_assign.cpp index ce99779327b..3bc63d83d4e 100644 --- a/src/amd/compiler/aco_reduce_assign.cpp +++ b/src/amd/compiler/aco_reduce_assign.cpp @@ -130,11 +130,11 @@ setup_reduce_temp(Program* program) op == imul16 || op == imax16 || op == imin16 || op == umin16 || op == iadd64; - if (program->chip_class >= GFX10 && cluster_size == 64) + if (program->gfx_level >= GFX10 && cluster_size == 64) need_vtmp = true; - if (program->chip_class >= GFX10 && gfx10_need_vtmp) + if (program->gfx_level >= GFX10 && gfx10_need_vtmp) need_vtmp = true; - if (program->chip_class <= GFX7) + if (program->gfx_level <= GFX7) need_vtmp = true; need_vtmp |= cluster_size == 32; diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index bd3f1cb525f..5cd29286e73 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -37,7 +37,7 @@ namespace { struct ra_ctx; -unsigned get_subdword_operand_stride(chip_class chip, const aco_ptr<Instruction>& instr, +unsigned get_subdword_operand_stride(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, unsigned idx, RegClass rc); void add_subdword_operand(ra_ctx& ctx, aco_ptr<Instruction>& instr, unsigned idx, unsigned byte, RegClass rc); @@ -214,7 +214,7 @@ struct DefInfo { if (rc.is_subdword() && operand >= 0) { /* stride in bytes */ - stride = get_subdword_operand_stride(ctx.program->chip_class, instr, operand, rc); + stride = get_subdword_operand_stride(ctx.program->gfx_level, instr, operand, rc); } else if (rc.is_subdword()) { std::pair<unsigned, unsigned> info = get_subdword_definition_info(ctx.program, instr, rc); stride = info.first; @@ -229,7 +229,7 @@ struct DefInfo { stride = DIV_ROUND_UP(stride, 4); } assert(stride > 0); - } else if (instr->isMIMG() && instr->mimg().d16 && ctx.program->chip_class <= GFX9) { + } else if (instr->isMIMG() && instr->mimg().d16 && ctx.program->gfx_level <= GFX9) { /* Workaround GFX9 hardware bug for D16 image instructions: FeatureImageGather4D16Bug * * The register use is not calculated correctly, and the hardware assumes a @@ -239,7 +239,7 @@ struct DefInfo { * https://reviews.llvm.org/D81172 */ bool imageGather4D16Bug = operand == -1 && rc == v2 && instr->mimg().dmask != 0xF; - assert(ctx.program->chip_class == GFX9 && "Image D16 on GFX8 not supported."); + assert(ctx.program->gfx_level == GFX9 && "Image D16 on GFX8 not supported."); if (imageGather4D16Bug) bounds.size -= rc.bytes() / 4; @@ -490,14 +490,14 @@ print_regs(ra_ctx& ctx, bool vgprs, RegisterFile& reg_file) } unsigned -get_subdword_operand_stride(chip_class chip, const aco_ptr<Instruction>& instr, unsigned idx, - RegClass rc) +get_subdword_operand_stride(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, + unsigned idx, RegClass rc) { if (instr->isPseudo()) { /* v_readfirstlane_b32 cannot use SDWA */ if (instr->opcode == aco_opcode::p_as_uniform) return 4; - else if (chip >= GFX8) + else if (gfx_level >= GFX8) return rc.bytes() % 2 == 0 ? 2 : 1; else return 4; @@ -505,9 +505,9 @@ get_subdword_operand_stride(chip_class chip, const aco_ptr<Instruction>& instr, assert(rc.bytes() <= 2); if (instr->isVALU()) { - if (can_use_SDWA(chip, instr, false)) + if (can_use_SDWA(gfx_level, instr, false)) return rc.bytes(); - if (can_use_opsel(chip, instr->opcode, idx)) + if (can_use_opsel(gfx_level, instr->opcode, idx)) return 2; if (instr->format == Format::VOP3P) return 2; @@ -516,7 +516,7 @@ get_subdword_operand_stride(chip_class chip, const aco_ptr<Instruction>& instr, switch (instr->opcode) { case aco_opcode::v_cvt_f32_ubyte0: return 1; case aco_opcode::ds_write_b8: - case aco_opcode::ds_write_b16: return chip >= GFX9 ? 2 : 4; + case aco_opcode::ds_write_b16: return gfx_level >= GFX9 ? 2 : 4; case aco_opcode::buffer_store_byte: case aco_opcode::buffer_store_short: case aco_opcode::buffer_store_format_d16_x: @@ -525,7 +525,7 @@ get_subdword_operand_stride(chip_class chip, const aco_ptr<Instruction>& instr, case aco_opcode::scratch_store_byte: case aco_opcode::scratch_store_short: case aco_opcode::global_store_byte: - case aco_opcode::global_store_short: return chip >= GFX9 ? 2 : 4; + case aco_opcode::global_store_short: return gfx_level >= GFX9 ? 2 : 4; default: return 4; } } @@ -534,7 +534,7 @@ void add_subdword_operand(ra_ctx& ctx, aco_ptr<Instruction>& instr, unsigned idx, unsigned byte, RegClass rc) { - chip_class chip = ctx.program->chip_class; + amd_gfx_level gfx_level = ctx.program->gfx_level; if (instr->isPseudo() || byte == 0) return; @@ -563,8 +563,8 @@ add_subdword_operand(ra_ctx& ctx, aco_ptr<Instruction>& instr, unsigned idx, uns } /* use SDWA */ - assert(can_use_SDWA(chip, instr, false)); - convert_to_SDWA(chip, instr); + assert(can_use_SDWA(gfx_level, instr, false)); + convert_to_SDWA(gfx_level, instr); return; } @@ -600,10 +600,10 @@ add_subdword_operand(ra_ctx& ctx, aco_ptr<Instruction>& instr, unsigned idx, uns std::pair<unsigned, unsigned> get_subdword_definition_info(Program* program, const aco_ptr<Instruction>& instr, RegClass rc) { - chip_class chip = program->chip_class; + amd_gfx_level gfx_level = program->gfx_level; if (instr->isPseudo()) { - if (chip >= GFX8) + if (gfx_level >= GFX8) return std::make_pair(rc.bytes() % 2 == 0 ? 2 : 1, rc.bytes()); else return std::make_pair(4, rc.size() * 4u); @@ -612,16 +612,16 @@ get_subdword_definition_info(Program* program, const aco_ptr<Instruction>& instr if (instr->isVALU() || instr->isVINTRP()) { assert(rc.bytes() <= 2); - if (can_use_SDWA(chip, instr, false)) + if (can_use_SDWA(gfx_level, instr, false)) return std::make_pair(rc.bytes(), rc.bytes()); unsigned bytes_written = 4u; - if (instr_is_16bit(chip, instr->opcode)) + if (instr_is_16bit(gfx_level, instr->opcode)) bytes_written = 2u; unsigned stride = 4u; if (instr->opcode == aco_opcode::v_fma_mixlo_f16 || - can_use_opsel(chip, instr->opcode, -1)) + can_use_opsel(gfx_level, instr->opcode, -1)) stride = 2u; return std::make_pair(stride, bytes_written); @@ -645,7 +645,7 @@ get_subdword_definition_info(Program* program, const aco_ptr<Instruction>& instr case aco_opcode::buffer_load_sbyte_d16: case aco_opcode::buffer_load_short_d16: case aco_opcode::buffer_load_format_d16_x: { - assert(chip >= GFX9); + assert(gfx_level >= GFX9); if (!program->dev.sram_ecc_enabled) return std::make_pair(2u, 2u); else @@ -654,7 +654,7 @@ get_subdword_definition_info(Program* program, const aco_ptr<Instruction>& instr /* 3-component D16 loads */ case aco_opcode::buffer_load_format_d16_xyz: case aco_opcode::tbuffer_load_format_d16_xyz: { - assert(chip >= GFX9); + assert(gfx_level >= GFX9); if (!program->dev.sram_ecc_enabled) return std::make_pair(4u, 6u); break; @@ -664,7 +664,7 @@ get_subdword_definition_info(Program* program, const aco_ptr<Instruction>& instr } if (instr->isMIMG() && instr->mimg().d16 && !program->dev.sram_ecc_enabled) { - assert(chip >= GFX9); + assert(gfx_level >= GFX9); return std::make_pair(4u, rc.bytes()); } @@ -678,16 +678,16 @@ add_subdword_definition(Program* program, aco_ptr<Instruction>& instr, PhysReg r return; if (instr->isVALU()) { - chip_class chip = program->chip_class; + amd_gfx_level gfx_level = program->gfx_level; assert(instr->definitions[0].bytes() <= 2); - if (reg.byte() == 0 && instr_is_16bit(chip, instr->opcode)) + if (reg.byte() == 0 && instr_is_16bit(gfx_level, instr->opcode)) return; /* check if we can use opsel */ if (instr->format == Format::VOP3) { assert(reg.byte() == 2); - assert(can_use_opsel(chip, instr->opcode, -1)); + assert(can_use_opsel(gfx_level, instr->opcode, -1)); instr->vop3().opsel |= (1 << 3); /* dst in high half */ return; } @@ -698,8 +698,8 @@ add_subdword_definition(Program* program, aco_ptr<Instruction>& instr, PhysReg r } /* use SDWA */ - assert(can_use_SDWA(chip, instr, false)); - convert_to_SDWA(chip, instr); + assert(can_use_SDWA(gfx_level, instr, false)); + convert_to_SDWA(gfx_level, instr); return; } @@ -1053,7 +1053,7 @@ get_reg_for_create_vector_copy(ra_ctx& ctx, RegisterFile& reg_file, reg.reg_b += instr->operands[i].bytes(); } - if (ctx.program->chip_class <= GFX8) + if (ctx.program->gfx_level <= GFX8) return {PhysReg(), false}; /* check if the previous position was in vector */ @@ -1886,7 +1886,7 @@ handle_pseudo(ra_ctx& ctx, const RegisterFile& reg_file, Instruction* instr) reads_subdword = true; } bool needs_scratch_reg = (writes_linear && reads_linear && reg_file[scc]) || - (ctx.program->chip_class <= GFX7 && reads_subdword); + (ctx.program->gfx_level <= GFX7 && reads_subdword); if (!needs_scratch_reg) return; @@ -1910,7 +1910,7 @@ handle_pseudo(ra_ctx& ctx, const RegisterFile& reg_file, Instruction* instr) } bool -operand_can_use_reg(chip_class chip, aco_ptr<Instruction>& instr, unsigned idx, PhysReg reg, +operand_can_use_reg(amd_gfx_level gfx_level, aco_ptr<Instruction>& instr, unsigned idx, PhysReg reg, RegClass rc) { if (instr->operands[idx].isFixed()) @@ -1918,7 +1918,7 @@ operand_can_use_reg(chip_class chip, aco_ptr<Instruction>& instr, unsigned idx, bool is_writelane = instr->opcode == aco_opcode::v_writelane_b32 || instr->opcode == aco_opcode::v_writelane_b32_e64; - if (chip <= GFX9 && is_writelane && idx <= 1) { + if (gfx_level <= GFX9 && is_writelane && idx <= 1) { /* v_writelane_b32 can take two sgprs but only if one is m0. */ bool is_other_sgpr = instr->operands[!idx].isTemp() && @@ -1930,7 +1930,7 @@ operand_can_use_reg(chip_class chip, aco_ptr<Instruction>& instr, unsigned idx, } if (reg.byte()) { - unsigned stride = get_subdword_operand_stride(chip, instr, idx, rc); + unsigned stride = get_subdword_operand_stride(gfx_level, instr, idx, rc); if (reg.byte() % stride) return false; } @@ -1940,7 +1940,7 @@ operand_can_use_reg(chip_class chip, aco_ptr<Instruction>& instr, unsigned idx, return reg != scc && reg != exec && (reg != m0 || idx == 1 || idx == 3) && /* offset can be m0 */ (reg != vcc || (instr->definitions.empty() && idx == 2) || - chip >= GFX10); /* sdata can be vcc */ + gfx_level >= GFX10); /* sdata can be vcc */ default: // TODO: there are more instructions with restrictions on registers return true; @@ -2389,7 +2389,7 @@ get_affinities(ra_ctx& ctx, std::vector<IDSet>& live_out_per_block) instr->operands[0].isFirstKillBeforeDef()) { ctx.split_vectors[instr->operands[0].tempId()] = instr.get(); } else if (instr->isVOPC() && !instr->isVOP3()) { - if (!instr->isSDWA() || ctx.program->chip_class == GFX8) + if (!instr->isSDWA() || ctx.program->gfx_level == GFX8) ctx.assignments[instr->definitions[0].tempId()].vcc = true; } else if (instr->isVOP2() && !instr->isVOP3()) { if (instr->operands.size() == 3 && instr->operands[2].isTemp() && @@ -2437,7 +2437,7 @@ get_affinities(ra_ctx& ctx, std::vector<IDSet>& live_out_per_block) case aco_opcode::v_fma_f32: case aco_opcode::v_fma_f16: case aco_opcode::v_pk_fma_f16: - if (ctx.program->chip_class < GFX10) + if (ctx.program->gfx_level < GFX10) continue; FALLTHROUGH; case aco_opcode::v_mad_f32: @@ -2642,12 +2642,12 @@ register_allocation(Program* program, std::vector<IDSet>& live_out_per_block, ra assert(ctx.assignments[operand.tempId()].assigned); PhysReg reg = ctx.assignments[operand.tempId()].reg; - if (operand_can_use_reg(program->chip_class, instr, i, reg, operand.regClass())) + if (operand_can_use_reg(program->gfx_level, instr, i, reg, operand.regClass())) operand.setFixed(reg); else get_reg_for_operand(ctx, register_file, parallelcopy, instr, operand, i); - if (instr->isEXP() || (instr->isVMEM() && i == 3 && ctx.program->chip_class == GFX6) || + if (instr->isEXP() || (instr->isVMEM() && i == 3 && ctx.program->gfx_level == GFX6) || (instr->isDS() && instr->ds().gds)) { for (unsigned j = 0; j < operand.size(); j++) ctx.war_hint.set(operand.physReg().reg() + j); @@ -2662,11 +2662,11 @@ register_allocation(Program* program, std::vector<IDSet>& live_out_per_block, ra /* try to optimize v_mad_f32 -> v_mac_f32 */ if ((instr->opcode == aco_opcode::v_mad_f32 || - (instr->opcode == aco_opcode::v_fma_f32 && program->chip_class >= GFX10) || + (instr->opcode == aco_opcode::v_fma_f32 && program->gfx_level >= GFX10) || instr->opcode == aco_opcode::v_mad_f16 || instr->opcode == aco_opcode::v_mad_legacy_f16 || - (instr->opcode == aco_opcode::v_fma_f16 && program->chip_class >= GFX10) || - (instr->opcode == aco_opcode::v_pk_fma_f16 && program->chip_class >= GFX10) || + (instr->opcode == aco_opcode::v_fma_f16 && program->gfx_level >= GFX10) || + (instr->opcode == aco_opcode::v_pk_fma_f16 && program->gfx_level >= GFX10) || (instr->opcode == aco_opcode::v_mad_legacy_f32 && program->dev.has_mac_legacy32) || (instr->opcode == aco_opcode::v_fma_legacy_f32 && program->dev.has_mac_legacy32) || (instr->opcode == aco_opcode::v_dot4_i32_i8 && program->family != CHIP_VEGA20)) && @@ -2953,7 +2953,7 @@ register_allocation(Program* program, std::vector<IDSet>& live_out_per_block, ra /* if the first operand is a literal, we have to move it to a reg */ if (instr->operands.size() && instr->operands[0].isLiteral() && - program->chip_class < GFX10) { + program->gfx_level < GFX10) { bool can_sgpr = true; /* check, if we have to move to vgpr */ for (const Operand& op : instr->operands) { diff --git a/src/amd/compiler/aco_spill.cpp b/src/amd/compiler/aco_spill.cpp index 37482685f93..1ef2b575f9f 100644 --- a/src/amd/compiler/aco_spill.cpp +++ b/src/amd/compiler/aco_spill.cpp @@ -1413,17 +1413,17 @@ load_scratch_resource(spill_ctx& ctx, Temp& scratch_offset, uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) | S_008F0C_INDEX_STRIDE(ctx.program->wave_size == 64 ? 3 : 2); - if (ctx.program->chip_class >= GFX10) { + if (ctx.program->gfx_level >= GFX10) { rsrc_conf |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | - S_008F0C_RESOURCE_LEVEL(ctx.program->chip_class < GFX11); - } else if (ctx.program->chip_class <= GFX7) { + S_008F0C_RESOURCE_LEVEL(ctx.program->gfx_level < GFX11); + } else if (ctx.program->gfx_level <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */ rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); } /* older generations need element size = 4 bytes. element size removed in GFX9 */ - if (ctx.program->chip_class <= GFX8) + if (ctx.program->gfx_level <= GFX8) rsrc_conf |= S_008F0C_ELEMENT_SIZE(1); return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, diff --git a/src/amd/compiler/aco_statistics.cpp b/src/amd/compiler/aco_statistics.cpp index db7f8b55785..9dd5aeb98ce 100644 --- a/src/amd/compiler/aco_statistics.cpp +++ b/src/amd/compiler/aco_statistics.cpp @@ -112,7 +112,7 @@ get_perf_info(Program* program, aco_ptr<Instruction>& instr) #define WAIT(res) BlockCycleEstimator::res, 0 #define WAIT_USE(res, cnt) BlockCycleEstimator::res, cnt - if (program->chip_class >= GFX10) { + if (program->gfx_level >= GFX10) { /* fp64 might be incorrect */ switch (cls) { case instr_class::valu32: @@ -265,9 +265,9 @@ get_wait_imm(Program* program, aco_ptr<Instruction>& instr) } else if (instr->opcode == aco_opcode::s_waitcnt_vscnt) { return wait_imm(0, 0, 0, instr->sopk().imm); } else { - unsigned max_lgkm_cnt = program->chip_class >= GFX10 ? 62 : 14; + unsigned max_lgkm_cnt = program->gfx_level >= GFX10 ? 62 : 14; unsigned max_exp_cnt = 6; - unsigned max_vm_cnt = program->chip_class >= GFX9 ? 62 : 14; + unsigned max_vm_cnt = program->gfx_level >= GFX9 ? 62 : 14; unsigned max_vs_cnt = 62; wait_counter_info wait_info = get_wait_counter_info(instr); @@ -306,7 +306,7 @@ BlockCycleEstimator::get_dependency_cost(aco_ptr<Instruction>& instr) if (instr->opcode == aco_opcode::s_endpgm) { for (unsigned i = 0; i < 512; i++) deps_available = MAX2(deps_available, reg_available[i]); - } else if (program->chip_class >= GFX10) { + } else if (program->gfx_level >= GFX10) { for (Operand& op : instr->operands) { if (op.isConstant() || op.isUndefined()) continue; @@ -315,7 +315,7 @@ BlockCycleEstimator::get_dependency_cost(aco_ptr<Instruction>& instr) } } - if (program->chip_class < GFX10) + if (program->gfx_level < GFX10) deps_available = align(deps_available, 4); return deps_available - cur_cycle; @@ -357,7 +357,7 @@ BlockCycleEstimator::add(aco_ptr<Instruction>& instr) cur_cycle += get_dependency_cost(instr); unsigned start; - bool dual_issue = program->chip_class >= GFX10 && program->wave_size == 64 && + bool dual_issue = program->gfx_level >= GFX10 && program->wave_size == 64 && is_vector(instr->opcode) && program->workgroup_size > 32; for (unsigned i = 0; i < (dual_issue ? 2 : 1); i++) { cur_cycle += cycles_until_res_available(instr); @@ -366,7 +366,7 @@ BlockCycleEstimator::add(aco_ptr<Instruction>& instr) use_resources(instr); /* GCN is in-order and doesn't begin the next instruction until the current one finishes */ - cur_cycle += program->chip_class >= GFX10 ? 1 : perf.latency; + cur_cycle += program->gfx_level >= GFX10 ? 1 : perf.latency; } wait_imm imm = get_wait_imm(program, instr); diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp index 6f76b42995d..098f12ace75 100644 --- a/src/amd/compiler/aco_validate.cpp +++ b/src/amd/compiler/aco_validate.cpp @@ -153,16 +153,16 @@ validate_ir(Program* program) base_format == Format::VOPC, "Format cannot have SDWA applied", instr.get()); - check(program->chip_class >= GFX8, "SDWA is GFX8+ only", instr.get()); + check(program->gfx_level >= GFX8, "SDWA is GFX8+ only", instr.get()); SDWA_instruction& sdwa = instr->sdwa(); - check(sdwa.omod == 0 || program->chip_class >= GFX9, - "SDWA omod only supported on GFX9+", instr.get()); + check(sdwa.omod == 0 || program->gfx_level >= GFX9, "SDWA omod only supported on GFX9+", + instr.get()); if (base_format == Format::VOPC) { - check(sdwa.clamp == false || program->chip_class == GFX8, + check(sdwa.clamp == false || program->gfx_level == GFX8, "SDWA VOPC clamp only supported on GFX8", instr.get()); check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) || - program->chip_class >= GFX9, + program->gfx_level >= GFX9, "SDWA+VOPC definition must be fixed to vcc on GFX8", instr.get()); } else { const Definition& def = instr->definitions[0]; @@ -215,7 +215,7 @@ validate_ir(Program* program) instr->opcode != aco_opcode::v_clrexcp && instr->opcode != aco_opcode::v_swap_b32; const bool feature_mac = - program->chip_class == GFX8 && + program->gfx_level == GFX8 && (instr->opcode == aco_opcode::v_mac_f32 && instr->opcode == aco_opcode::v_mac_f16); check(sdwa_opcodes || feature_mac, "SDWA can't be used with this opcode", instr.get()); @@ -224,8 +224,8 @@ validate_ir(Program* program) /* check opsel */ if (instr->isVOP3()) { VOP3_instruction& vop3 = instr->vop3(); - check(vop3.opsel == 0 || program->chip_class >= GFX9, - "Opsel is only supported on GFX9+", instr.get()); + check(vop3.opsel == 0 || program->gfx_level >= GFX9, "Opsel is only supported on GFX9+", + instr.get()); for (unsigned i = 0; i < 3; i++) { if (i >= instr->operands.size() || @@ -287,8 +287,8 @@ validate_ir(Program* program) continue; check(!instr->isDPP() && !instr->isSDWA() && - (!instr->isVOP3() || program->chip_class >= GFX10) && - (!instr->isVOP3P() || program->chip_class >= GFX10), + (!instr->isVOP3() || program->gfx_level >= GFX10) && + (!instr->isVOP3P() || program->gfx_level >= GFX10), "Literal applied on wrong instruction format", instr.get()); check(literal.isUndefined() || (literal.size() == op.size() && @@ -305,12 +305,12 @@ validate_ir(Program* program) instr->opcode == aco_opcode::v_lshrrev_b64 || instr->opcode == aco_opcode::v_ashrrev_i64; unsigned const_bus_limit = 1; - if (program->chip_class >= GFX10 && !is_shift64) + if (program->gfx_level >= GFX10 && !is_shift64) const_bus_limit = 2; uint32_t scalar_mask = instr->isVOP3() || instr->isVOP3P() ? 0x7 : 0x5; if (instr->isSDWA()) - scalar_mask = program->chip_class >= GFX9 ? 0x7 : 0x4; + scalar_mask = program->gfx_level >= GFX9 ? 0x7 : 0x4; else if (instr->isDPP()) scalar_mask = 0x4; @@ -412,7 +412,7 @@ validate_ir(Program* program) check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->operands[0].regClass().type() == RegType::sgpr, "Cannot extract SGPR value from VGPR vector", instr.get()); - check(program->chip_class >= GFX9 || + check(program->gfx_level >= GFX9 || !instr->definitions[0].regClass().is_subdword() || instr->operands[0].regClass().type() == RegType::vgpr, "Cannot extract subdword from SGPR before GFX9+", instr.get()); @@ -430,7 +430,7 @@ validate_ir(Program* program) "Wrong Definition type for VGPR split_vector", instr.get()); } else { for (const Definition& def : instr->definitions) - check(program->chip_class >= GFX9 || !def.regClass().is_subdword(), + check(program->gfx_level >= GFX9 || !def.regClass().is_subdword(), "Cannot split SGPR into subdword VGPRs before GFX9+", instr.get()); } } else if (instr->opcode == aco_opcode::p_parallelcopy) { @@ -610,7 +610,7 @@ validate_ir(Program* program) "TFE/LWE loads", instr.get()); } - check(instr->operands.size() == 4 || program->chip_class >= GFX10, + check(instr->operands.size() == 4 || program->gfx_level >= GFX10, "NSA is only supported on GFX10+", instr.get()); for (unsigned i = 3; i < instr->operands.size(); i++) { if (instr->operands.size() == 4) { @@ -762,14 +762,15 @@ ra_fail(Program* program, Location loc, Location loc2, const char* fmt, ...) } bool -validate_subdword_operand(chip_class chip, const aco_ptr<Instruction>& instr, unsigned index) +validate_subdword_operand(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, + unsigned index) { Operand op = instr->operands[index]; unsigned byte = op.physReg().byte(); if (instr->opcode == aco_opcode::p_as_uniform) return byte == 0; - if (instr->isPseudo() && chip >= GFX8) + if (instr->isPseudo() && gfx_level >= GFX8) return true; if (instr->isSDWA()) return byte + instr->sdwa().sel[index].offset() + instr->sdwa().sel[index].size() <= 4 && @@ -781,7 +782,7 @@ validate_subdword_operand(chip_class chip, const aco_ptr<Instruction>& instr, un return ((instr->vop3p().opsel_lo >> index) & 1) == (byte >> 1) && ((instr->vop3p().opsel_hi >> index) & 1) == (fma_mix || (byte >> 1)); } - if (byte == 2 && can_use_opsel(chip, instr->opcode, index)) + if (byte == 2 && can_use_opsel(gfx_level, instr->opcode, index)) return true; switch (instr->opcode) { @@ -824,17 +825,17 @@ validate_subdword_operand(chip_class chip, const aco_ptr<Instruction>& instr, un } bool -validate_subdword_definition(chip_class chip, const aco_ptr<Instruction>& instr) +validate_subdword_definition(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr) { Definition def = instr->definitions[0]; unsigned byte = def.physReg().byte(); - if (instr->isPseudo() && chip >= GFX8) + if (instr->isPseudo() && gfx_level >= GFX8) return true; if (instr->isSDWA()) return byte + instr->sdwa().dst_sel.offset() + instr->sdwa().dst_sel.size() <= 4 && byte % instr->sdwa().dst_sel.size() == 0; - if (byte == 2 && can_use_opsel(chip, instr->opcode, -1)) + if (byte == 2 && can_use_opsel(gfx_level, instr->opcode, -1)) return true; switch (instr->opcode) { @@ -859,17 +860,17 @@ validate_subdword_definition(chip_class chip, const aco_ptr<Instruction>& instr) unsigned get_subdword_bytes_written(Program* program, const aco_ptr<Instruction>& instr, unsigned index) { - chip_class chip = program->chip_class; + amd_gfx_level gfx_level = program->gfx_level; Definition def = instr->definitions[index]; if (instr->isPseudo()) - return chip >= GFX8 ? def.bytes() : def.size() * 4u; + return gfx_level >= GFX8 ? def.bytes() : def.size() * 4u; if (instr->isVALU()) { assert(def.bytes() <= 2); if (instr->isSDWA()) return instr->sdwa().dst_sel.size(); - if (instr_is_16bit(chip, instr->opcode)) + if (instr_is_16bit(gfx_level, instr->opcode)) return 2; return 4; @@ -1009,7 +1010,7 @@ validate_ra(Program* program) err |= ra_fail(program, loc, Location(), "Operand %d fixed to vcc but needs_vcc=false", i); if (op.regClass().is_subdword() && - !validate_subdword_operand(program->chip_class, instr, i)) + !validate_subdword_operand(program->gfx_level, instr, i)) err |= ra_fail(program, loc, Location(), "Operand %d not aligned correctly", i); if (!assignments[op.tempId()].firstloc.block) assignments[op.tempId()].firstloc = loc; @@ -1040,7 +1041,7 @@ validate_ra(Program* program) err |= ra_fail(program, loc, Location(), "Definition %d fixed to vcc but needs_vcc=false", i); if (def.regClass().is_subdword() && - !validate_subdword_definition(program->chip_class, instr)) + !validate_subdword_definition(program->gfx_level, instr)) err |= ra_fail(program, loc, Location(), "Definition %d not aligned correctly", i); if (!assignments[def.tempId()].firstloc.block) assignments[def.tempId()].firstloc = loc; diff --git a/src/amd/compiler/tests/framework.h b/src/amd/compiler/tests/framework.h index 097921f8df9..477120350a1 100644 --- a/src/amd/compiler/tests/framework.h +++ b/src/amd/compiler/tests/framework.h @@ -43,7 +43,7 @@ extern FILE *output; bool set_variant(const char *name); -inline bool set_variant(chip_class cls, const char *rest="") +inline bool set_variant(amd_gfx_level cls, const char *rest="") { char buf[8+strlen(rest)]; if (cls != GFX10_3) { diff --git a/src/amd/compiler/tests/helpers.cpp b/src/amd/compiler/tests/helpers.cpp index c0b08fb5579..ba53bf60dcd 100644 --- a/src/amd/compiler/tests/helpers.cpp +++ b/src/amd/compiler/tests/helpers.cpp @@ -72,13 +72,13 @@ static std::mutex create_device_mutex; FUNCTION_LIST #undef ITEM -void create_program(enum chip_class chip_class, Stage stage, unsigned wave_size, enum radeon_family family) +void create_program(enum amd_gfx_level gfx_level, Stage stage, unsigned wave_size, enum radeon_family family) { memset(&config, 0, sizeof(config)); info.wave_size = wave_size; program.reset(new Program); - aco::init_program(program.get(), stage, &info, chip_class, family, false, &config); + aco::init_program(program.get(), stage, &info, gfx_level, family, false, &config); program->workgroup_size = UINT_MAX; calc_min_waves(program.get()); @@ -98,15 +98,15 @@ void create_program(enum chip_class chip_class, Stage stage, unsigned wave_size, config.float_mode = program->blocks[0].fp_mode.val; } -bool setup_cs(const char *input_spec, enum chip_class chip_class, +bool setup_cs(const char *input_spec, enum amd_gfx_level gfx_level, enum radeon_family family, const char* subvariant, unsigned wave_size) { - if (!set_variant(chip_class, subvariant)) + if (!set_variant(gfx_level, subvariant)) return false; memset(&info, 0, sizeof(info)); - create_program(chip_class, compute_cs, wave_size, family); + create_program(gfx_level, compute_cs, wave_size, family); if (input_spec) { std::vector<RegClass> input_classes; @@ -236,7 +236,7 @@ void finish_assembler_test() /* we could use CLRX for disassembly but that would require it to be * installed */ - if (program->chip_class >= GFX8) { + if (program->gfx_level >= GFX8) { print_asm(program.get(), binary, exec_size / 4u, output); } else { //TODO: maybe we should use CLRX and skip this test if it's not available? @@ -350,10 +350,10 @@ Temp ext_ubyte(Temp src, unsigned idx, Builder b) Operand::c32(8u), Operand::c32(false)); } -VkDevice get_vk_device(enum chip_class chip_class) +VkDevice get_vk_device(enum amd_gfx_level gfx_level) { enum radeon_family family; - switch (chip_class) { + switch (gfx_level) { case GFX6: family = CHIP_TAHITI; break; diff --git a/src/amd/compiler/tests/helpers.h b/src/amd/compiler/tests/helpers.h index f6fe6695939..2151e99a80c 100644 --- a/src/amd/compiler/tests/helpers.h +++ b/src/amd/compiler/tests/helpers.h @@ -70,9 +70,9 @@ namespace aco { struct ra_test_policy; } -void create_program(enum chip_class chip_class, aco::Stage stage, +void create_program(enum amd_gfx_level gfx_level, aco::Stage stage, unsigned wave_size=64, enum radeon_family family=CHIP_UNKNOWN); -bool setup_cs(const char *input_spec, enum chip_class chip_class, +bool setup_cs(const char *input_spec, enum amd_gfx_level gfx_level, enum radeon_family family=CHIP_UNKNOWN, const char* subvariant = "", unsigned wave_size=64); @@ -104,7 +104,7 @@ aco::Temp ext_ushort(aco::Temp src, unsigned idx, aco::Builder b=bld); aco::Temp ext_ubyte(aco::Temp src, unsigned idx, aco::Builder b=bld); /* vulkan helpers */ -VkDevice get_vk_device(enum chip_class chip_class); +VkDevice get_vk_device(enum amd_gfx_level gfx_level); VkDevice get_vk_device(enum radeon_family family); void print_pipeline_ir(VkDevice device, VkPipeline pipeline, VkShaderStageFlagBits stages, diff --git a/src/amd/compiler/tests/test_assembler.cpp b/src/amd/compiler/tests/test_assembler.cpp index e068aca1aa3..5a1cde0787d 100644 --- a/src/amd/compiler/tests/test_assembler.cpp +++ b/src/amd/compiler/tests/test_assembler.cpp @@ -27,7 +27,7 @@ using namespace aco; BEGIN_TEST(assembler.s_memtime) for (unsigned i = GFX6; i <= GFX10; i++) { - if (!setup_cs(NULL, (chip_class)i)) + if (!setup_cs(NULL, (amd_gfx_level)i)) continue; //~gfx[6-7]>> c7800000 @@ -41,7 +41,7 @@ BEGIN_TEST(assembler.s_memtime) END_TEST BEGIN_TEST(assembler.branch_3f) - if (!setup_cs(NULL, (chip_class)GFX10)) + if (!setup_cs(NULL, (amd_gfx_level)GFX10)) return; //! BB0: @@ -60,7 +60,7 @@ BEGIN_TEST(assembler.branch_3f) END_TEST BEGIN_TEST(assembler.long_jump.unconditional_forwards) - if (!setup_cs(NULL, (chip_class)GFX10)) + if (!setup_cs(NULL, (amd_gfx_level)GFX10)) return; //!BB0: @@ -90,7 +90,7 @@ BEGIN_TEST(assembler.long_jump.unconditional_forwards) END_TEST BEGIN_TEST(assembler.long_jump.conditional_forwards) - if (!setup_cs(NULL, (chip_class)GFX10)) + if (!setup_cs(NULL, (amd_gfx_level)GFX10)) return; //! BB0: @@ -123,7 +123,7 @@ BEGIN_TEST(assembler.long_jump.conditional_forwards) END_TEST BEGIN_TEST(assembler.long_jump.unconditional_backwards) - if (!setup_cs(NULL, (chip_class)GFX10)) + if (!setup_cs(NULL, (amd_gfx_level)GFX10)) return; //!BB0: @@ -151,7 +151,7 @@ BEGIN_TEST(assembler.long_jump.unconditional_backwards) END_TEST BEGIN_TEST(assembler.long_jump.conditional_backwards) - if (!setup_cs(NULL, (chip_class)GFX10)) + if (!setup_cs(NULL, (amd_gfx_level)GFX10)) return; //!BB0: @@ -180,7 +180,7 @@ BEGIN_TEST(assembler.long_jump.conditional_backwards) END_TEST BEGIN_TEST(assembler.long_jump.3f) - if (!setup_cs(NULL, (chip_class)GFX10)) + if (!setup_cs(NULL, (amd_gfx_level)GFX10)) return; //! BB0: @@ -205,7 +205,7 @@ BEGIN_TEST(assembler.long_jump.3f) END_TEST BEGIN_TEST(assembler.long_jump.constaddr) - if (!setup_cs(NULL, (chip_class)GFX10)) + if (!setup_cs(NULL, (amd_gfx_level)GFX10)) return; //>> s_getpc_b64 s[0:1] ; be801f00 @@ -232,7 +232,7 @@ END_TEST BEGIN_TEST(assembler.v_add3) for (unsigned i = GFX9; i <= GFX10; i++) { - if (!setup_cs(NULL, (chip_class)i)) + if (!setup_cs(NULL, (amd_gfx_level)i)) continue; //~gfx9>> v_add3_u32 v0, 0, 0, 0 ; d1ff0000 02010080 @@ -250,7 +250,7 @@ END_TEST BEGIN_TEST(assembler.v_add3_clamp) for (unsigned i = GFX9; i <= GFX10; i++) { - if (!setup_cs(NULL, (chip_class)i)) + if (!setup_cs(NULL, (amd_gfx_level)i)) continue; //~gfx9>> integer addition + clamp ; d1ff8000 02010080 @@ -269,7 +269,7 @@ END_TEST BEGIN_TEST(assembler.smem_offset) for (unsigned i = GFX9; i <= GFX10; i++) { - if (!setup_cs(NULL, (chip_class)i)) + if (!setup_cs(NULL, (amd_gfx_level)i)) continue; Definition dst(PhysReg(7), s1); diff --git a/src/amd/compiler/tests/test_builder.cpp b/src/amd/compiler/tests/test_builder.cpp index ee481ecdb21..e7c0ace9a8b 100644 --- a/src/amd/compiler/tests/test_builder.cpp +++ b/src/amd/compiler/tests/test_builder.cpp @@ -28,7 +28,7 @@ using namespace aco; BEGIN_TEST(builder.v_mul_imm) for (unsigned i = GFX8; i <= GFX10; i++) { //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm - if (!setup_cs("v1 v1 s1 s1", (chip_class)i)) + if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) continue; /* simple optimizations */ diff --git a/src/amd/compiler/tests/test_hard_clause.cpp b/src/amd/compiler/tests/test_hard_clause.cpp index 9def23f06f9..5274c24a555 100644 --- a/src/amd/compiler/tests/test_hard_clause.cpp +++ b/src/amd/compiler/tests/test_hard_clause.cpp @@ -204,7 +204,7 @@ END_TEST BEGIN_TEST(form_hard_clauses.nsa) for (unsigned i = GFX10; i <= GFX10_3; i++) { - if (!setup_cs(NULL, (chip_class)i)) + if (!setup_cs(NULL, (amd_gfx_level)i)) continue; //>> p_unit_test 0 diff --git a/src/amd/compiler/tests/test_isel.cpp b/src/amd/compiler/tests/test_isel.cpp index d74822810bd..593d401b67a 100644 --- a/src/amd/compiler/tests/test_isel.cpp +++ b/src/amd/compiler/tests/test_isel.cpp @@ -60,7 +60,7 @@ END_TEST BEGIN_TEST(isel.compute.simple) for (unsigned i = GFX7; i <= GFX8; i++) { - if (!set_variant((chip_class)i)) + if (!set_variant((amd_gfx_level)i)) continue; QoShaderModuleCreateInfo cs = qoShaderModuleCreateInfoGLSL(COMPUTE, @@ -75,7 +75,7 @@ BEGIN_TEST(isel.compute.simple) } ); - PipelineBuilder pbld(get_vk_device((chip_class)i)); + PipelineBuilder pbld(get_vk_device((amd_gfx_level)i)); pbld.add_cs(cs); pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "ACO IR", true); } @@ -83,7 +83,7 @@ END_TEST BEGIN_TEST(isel.gs.no_outputs) for (unsigned i = GFX8; i <= GFX10; i++) { - if (!set_variant((chip_class)i)) + if (!set_variant((amd_gfx_level)i)) continue; QoShaderModuleCreateInfo vs = qoShaderModuleCreateInfoGLSL(VERTEX, @@ -100,7 +100,7 @@ BEGIN_TEST(isel.gs.no_outputs) } ); - PipelineBuilder pbld(get_vk_device((chip_class)i)); + PipelineBuilder pbld(get_vk_device((amd_gfx_level)i)); pbld.add_stage(VK_SHADER_STAGE_VERTEX_BIT, vs); pbld.add_stage(VK_SHADER_STAGE_GEOMETRY_BIT, gs); pbld.create_pipeline(); @@ -112,7 +112,7 @@ END_TEST BEGIN_TEST(isel.gs.no_verts) for (unsigned i = GFX8; i <= GFX10; i++) { - if (!set_variant((chip_class)i)) + if (!set_variant((amd_gfx_level)i)) continue; QoShaderModuleCreateInfo vs = qoShaderModuleCreateInfoGLSL(VERTEX, @@ -126,7 +126,7 @@ BEGIN_TEST(isel.gs.no_verts) void main() {} ); - PipelineBuilder pbld(get_vk_device((chip_class)i)); + PipelineBuilder pbld(get_vk_device((amd_gfx_level)i)); pbld.add_stage(VK_SHADER_STAGE_VERTEX_BIT, vs); pbld.add_stage(VK_SHADER_STAGE_GEOMETRY_BIT, gs); pbld.create_pipeline(); @@ -138,7 +138,7 @@ END_TEST BEGIN_TEST(isel.sparse.clause) for (unsigned i = GFX10_3; i <= GFX10_3; i++) { - if (!set_variant((chip_class)i)) + if (!set_variant((amd_gfx_level)i)) continue; QoShaderModuleCreateInfo cs = qoShaderModuleCreateInfoGLSL(COMPUTE, @@ -179,7 +179,7 @@ BEGIN_TEST(isel.sparse.clause) fprintf(output, "llvm_version: %u\n", LLVM_VERSION_MAJOR); - PipelineBuilder pbld(get_vk_device((chip_class)i)); + PipelineBuilder pbld(get_vk_device((amd_gfx_level)i)); pbld.add_cs(cs); pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "ACO IR", true); pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "Assembly", true); diff --git a/src/amd/compiler/tests/test_optimizer.cpp b/src/amd/compiler/tests/test_optimizer.cpp index f2cf02198e2..1684b9ad824 100644 --- a/src/amd/compiler/tests/test_optimizer.cpp +++ b/src/amd/compiler/tests/test_optimizer.cpp @@ -28,7 +28,7 @@ using namespace aco; BEGIN_TEST(optimize.neg) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm - if (!setup_cs("v1 v1 s1 s1", (chip_class)i)) + if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) continue; //! v1: %res0 = v_mul_f32 %a, -%b @@ -272,7 +272,7 @@ Temp create_subbrev_co(Operand op0, Operand op1, Operand op2) BEGIN_TEST(optimize.cndmask) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a, s1: %b, s2: %c = p_startpgm - if (!setup_cs("v1 s1 s2", (chip_class)i)) + if (!setup_cs("v1 s1 s2", (amd_gfx_level)i)) continue; Temp subbrev; @@ -316,7 +316,7 @@ END_TEST BEGIN_TEST(optimize.add_lshl) for (unsigned i = GFX8; i <= GFX10; i++) { //>> s1: %a, v1: %b = p_startpgm - if (!setup_cs("s1 v1", (chip_class)i)) + if (!setup_cs("s1 v1", (amd_gfx_level)i)) continue; Temp shift; @@ -398,7 +398,7 @@ END_TEST BEGIN_TEST(optimize.bcnt) for (unsigned i = GFX8; i <= GFX10; i++) { //>> v1: %a, s1: %b = p_startpgm - if (!setup_cs("v1 s1", (chip_class)i)) + if (!setup_cs("v1 s1", (amd_gfx_level)i)) continue; Temp bcnt; @@ -714,7 +714,7 @@ END_TEST BEGIN_TEST(optimize.minmax) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a = p_startpgm - if (!setup_cs("v1", (chip_class)i)) + if (!setup_cs("v1", (amd_gfx_level)i)) continue; //! v1: %res0 = v_max3_f32 0, -0, %a @@ -737,7 +737,7 @@ END_TEST BEGIN_TEST(optimize.mad_32_24) for (unsigned i = GFX8; i <= GFX9; i++) { //>> v1: %a, v1: %b, v1: %c = p_startpgm - if (!setup_cs("v1 v1 v1", (chip_class)i)) + if (!setup_cs("v1 v1 v1", (amd_gfx_level)i)) continue; //! v1: %res0 = v_mad_u32_u24 %b, %c, %a @@ -758,7 +758,7 @@ END_TEST BEGIN_TEST(optimize.add_lshlrev) for (unsigned i = GFX8; i <= GFX10; i++) { //>> v1: %a, v1: %b, s1: %c = p_startpgm - if (!setup_cs("v1 v1 s1", (chip_class)i)) + if (!setup_cs("v1 v1 s1", (amd_gfx_level)i)) continue; Temp lshl; @@ -886,7 +886,7 @@ BEGIN_TEST(optimize.denorm_propagation) sprintf(subvariant, "_%s_%s_%s_%s", cfg.flush ? "flush" : "keep", srcdest_op_name(cfg.src), denorm_op_names[(int)cfg.op], srcdest_op_name(cfg.dest)); - if (!setup_cs("v1 s2", (chip_class)i, CHIP_UNKNOWN, subvariant)) + if (!setup_cs("v1 s2", (amd_gfx_level)i, CHIP_UNKNOWN, subvariant)) continue; bool can_propagate = cfg.src == aco_opcode::v_rcp_f32 || (i >= GFX9 && cfg.src == aco_opcode::v_min_f32) || @@ -1161,7 +1161,7 @@ END_TEST BEGIN_TEST(optimize.mad_mix.input_conv.basic) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a, v2b: %a16 = p_startpgm - if (!setup_cs("v1 v2b", (chip_class)i)) + if (!setup_cs("v1 v2b", (amd_gfx_level)i)) continue; program->blocks[0].fp_mode.denorm16_64 = fp_denorm_flush; @@ -1196,7 +1196,7 @@ END_TEST BEGIN_TEST(optimize.mad_mix.input_conv.precision) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a, v2b: %a16 = p_startpgm - if (!setup_cs("v1 v2b", (chip_class)i)) + if (!setup_cs("v1 v2b", (amd_gfx_level)i)) continue; program->blocks[0].fp_mode.denorm16_64 = fp_denorm_flush; @@ -1249,7 +1249,7 @@ END_TEST BEGIN_TEST(optimize.mad_mix.input_conv.modifiers) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a, v2b: %a16 = p_startpgm - if (!setup_cs("v1 v2b", (chip_class)i)) + if (!setup_cs("v1 v2b", (amd_gfx_level)i)) continue; program->blocks[0].fp_mode.denorm16_64 = fp_denorm_flush; @@ -1344,7 +1344,7 @@ END_TEST BEGIN_TEST(optimize.mad_mix.output_conv.basic) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a, v1: %b, v1: %c, v2b: %a16, v2b: %b16 = p_startpgm - if (!setup_cs("v1 v1 v1 v2b v2b", (chip_class)i)) + if (!setup_cs("v1 v1 v1 v2b v2b", (amd_gfx_level)i)) continue; program->blocks[0].fp_mode.denorm16_64 = fp_denorm_flush; @@ -1386,7 +1386,7 @@ END_TEST BEGIN_TEST(optimize.mad_mix.output_conv.precision) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v2b: %a16 = p_startpgm - if (!setup_cs("v2b", (chip_class)i)) + if (!setup_cs("v2b", (amd_gfx_level)i)) continue; program->blocks[0].fp_mode.denorm16_64 = fp_denorm_flush; @@ -1410,7 +1410,7 @@ END_TEST BEGIN_TEST(optimize.mad_mix.output_conv.modifiers) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a, v1: %b, v2b: %a16, v2b: %b16 = p_startpgm - if (!setup_cs("v1 v1 v2b v2b", (chip_class)i)) + if (!setup_cs("v1 v1 v2b v2b", (amd_gfx_level)i)) continue; program->blocks[0].fp_mode.denorm16_64 = fp_denorm_flush; @@ -1459,7 +1459,7 @@ END_TEST BEGIN_TEST(optimize.mad_mix.fma.basic) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a, v1: %b, v1: %c, v2b: %a16, v2b: %c16 = p_startpgm - if (!setup_cs("v1 v1 v1 v2b v2b", (chip_class)i)) + if (!setup_cs("v1 v1 v1 v2b v2b", (amd_gfx_level)i)) continue; program->blocks[0].fp_mode.denorm16_64 = fp_denorm_flush; @@ -1513,7 +1513,7 @@ END_TEST BEGIN_TEST(optimize.mad_mix.fma.precision) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a, v1: %b, v1: %c, v2b: %a16, v2b: %b16 = p_startpgm - if (!setup_cs("v1 v1 v1 v2b v2b", (chip_class)i)) + if (!setup_cs("v1 v1 v1 v2b v2b", (amd_gfx_level)i)) continue; program->blocks[0].fp_mode.denorm16_64 = fp_denorm_flush; @@ -1575,7 +1575,7 @@ END_TEST BEGIN_TEST(optimize.mad_mix.clamp) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a, v2b: %a16 = p_startpgm - if (!setup_cs("v1 v2b", (chip_class)i)) + if (!setup_cs("v1 v2b", (amd_gfx_level)i)) continue; program->blocks[0].fp_mode.denorm16_64 = fp_denorm_flush; @@ -1602,7 +1602,7 @@ END_TEST BEGIN_TEST(optimize.mad_mix.cast) for (unsigned i = GFX9; i <= GFX10; i++) { //>> v1: %a, v2b: %a16 = p_startpgm - if (!setup_cs("v1 v2b", (chip_class)i)) + if (!setup_cs("v1 v2b", (amd_gfx_level)i)) continue; program->blocks[0].fp_mode.denorm16_64 = fp_denorm_flush; diff --git a/src/amd/compiler/tests/test_regalloc.cpp b/src/amd/compiler/tests/test_regalloc.cpp index a63ca2bdfbd..d7c99aa2983 100644 --- a/src/amd/compiler/tests/test_regalloc.cpp +++ b/src/amd/compiler/tests/test_regalloc.cpp @@ -35,12 +35,12 @@ BEGIN_TEST(regalloc.subdword_alloc.reuse_16bit_operands) * result in v0. */ - for (chip_class cc = GFX8; cc < NUM_GFX_VERSIONS; cc = (chip_class)((unsigned)cc + 1)) { + for (amd_gfx_level cc = GFX8; cc < NUM_GFX_VERSIONS; cc = (amd_gfx_level)((unsigned)cc + 1)) { for (bool pessimistic : { false, true }) { const char* subvariant = pessimistic ? "/pessimistic" : "/optimistic"; //>> v1: %_:v[#a] = p_startpgm - if (!setup_cs("v1", (chip_class)cc, CHIP_UNKNOWN, subvariant)) + if (!setup_cs("v1", (amd_gfx_level)cc, CHIP_UNKNOWN, subvariant)) return; //! v2b: %_:v[#a][0:16], v2b: %res1:v[#a][16:32] = p_split_vector %_:v[#a] diff --git a/src/amd/compiler/tests/test_sdwa.cpp b/src/amd/compiler/tests/test_sdwa.cpp index 8a8d8b64fe7..8ed5bbb517b 100644 --- a/src/amd/compiler/tests/test_sdwa.cpp +++ b/src/amd/compiler/tests/test_sdwa.cpp @@ -29,7 +29,7 @@ using namespace aco; BEGIN_TEST(validate.sdwa.allow) for (unsigned i = GFX8; i <= GFX10; i++) { //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm - if (!setup_cs("v1 v1 s1 s1", (chip_class)i)) + if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) continue; //>> Validation results: //! Validation passed @@ -50,7 +50,7 @@ END_TEST BEGIN_TEST(validate.sdwa.support) for (unsigned i = GFX7; i <= GFX10; i++) { //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm - if (!setup_cs("v1 v1 s1 s1", (chip_class)i)) + if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) continue; //>> Validation results: @@ -66,7 +66,7 @@ END_TEST BEGIN_TEST(validate.sdwa.operands) for (unsigned i = GFX8; i <= GFX10; i++) { //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm - if (!setup_cs("v1 v1 s1 s1", (chip_class)i)) + if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) continue; //>> Validation results: @@ -95,7 +95,7 @@ END_TEST BEGIN_TEST(validate.sdwa.vopc) for (unsigned i = GFX8; i <= GFX10; i++) { //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm - if (!setup_cs("v1 v1 s1 s1", (chip_class)i)) + if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) continue; //>> Validation results: @@ -116,7 +116,7 @@ END_TEST BEGIN_TEST(validate.sdwa.omod) for (unsigned i = GFX8; i <= GFX10; i++) { //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm - if (!setup_cs("v1 v1 s1 s1", (chip_class)i)) + if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) continue; //>> Validation results: @@ -132,7 +132,7 @@ END_TEST BEGIN_TEST(validate.sdwa.vcc) for (unsigned i = GFX8; i <= GFX10; i++) { //>> v1: %vgpr0, v1: %vgpr1, s2: %sgpr0 = p_startpgm - if (!setup_cs("v1 v1 s2", (chip_class)i)) + if (!setup_cs("v1 v1 s2", (amd_gfx_level)i)) continue; //>> Validation results: @@ -154,7 +154,7 @@ BEGIN_TEST(optimize.sdwa.extract) for (unsigned i = GFX7; i <= GFX10; i++) { for (unsigned is_signed = 0; is_signed <= 1; is_signed++) { //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm - if (!setup_cs("v1 v1 s1 s1", (chip_class)i, CHIP_UNKNOWN, is_signed ? "_signed" : "_unsigned")) + if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i, CHIP_UNKNOWN, is_signed ? "_signed" : "_unsigned")) continue; //; def standard_test(index, sel): @@ -277,7 +277,7 @@ END_TEST BEGIN_TEST(optimize.sdwa.extract_modifiers) for (unsigned i = GFX8; i <= GFX10; i++) { //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm - if (!setup_cs("v1 v1 s1 s1", (chip_class)i)) + if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) continue; aco_opcode ext = aco_opcode::p_extract; @@ -334,7 +334,7 @@ END_TEST BEGIN_TEST(optimize.sdwa.extract.sgpr) for (unsigned i = GFX8; i <= GFX10; i++) { //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm - if (!setup_cs("v1 v1 s1 s1", (chip_class)i)) + if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) continue; aco_opcode ext = aco_opcode::p_extract; @@ -378,7 +378,7 @@ END_TEST BEGIN_TEST(optimize.sdwa.from_vop3) for (unsigned i = GFX8; i <= GFX10; i++) { //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm - if (!setup_cs("v1 v1 s1 s1", (chip_class)i)) + if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) continue; //! v1: %res0 = v_mul_f32 -|%a|, %b dst_sel:dword src0_sel:dword src1_sel:ubyte0 @@ -425,7 +425,7 @@ END_TEST BEGIN_TEST(optimize.sdwa.insert) for (unsigned i = GFX7; i <= GFX10; i++) { //>> v1: %a, v1: %b = p_startpgm - if (!setup_cs("v1 v1", (chip_class)i)) + if (!setup_cs("v1 v1", (amd_gfx_level)i)) continue; aco_opcode ext = aco_opcode::p_extract; @@ -523,7 +523,7 @@ END_TEST BEGIN_TEST(optimize.sdwa.insert_modifiers) for (unsigned i = GFX8; i <= GFX9; i++) { //>> v1: %a = p_startpgm - if (!setup_cs("v1", (chip_class)i)) + if (!setup_cs("v1", (amd_gfx_level)i)) continue; aco_opcode ins = aco_opcode::p_insert; diff --git a/src/amd/compiler/tests/test_tests.cpp b/src/amd/compiler/tests/test_tests.cpp index 88b33ab8440..cb9c511165c 100644 --- a/src/amd/compiler/tests/test_tests.cpp +++ b/src/amd/compiler/tests/test_tests.cpp @@ -54,7 +54,7 @@ BEGIN_TEST(simple.2) //~gfx9! test gfx9 //! test all for (int cls = GFX6; cls <= GFX7; cls++) { - if (!set_variant((enum chip_class)cls)) + if (!set_variant((enum amd_gfx_level)cls)) continue; fprintf(output, "test gfx67\n"); fprintf(output, "test all\n"); diff --git a/src/amd/compiler/tests/test_to_hw_instr.cpp b/src/amd/compiler/tests/test_to_hw_instr.cpp index 0914bdc14cb..22587d4edea 100644 --- a/src/amd/compiler/tests/test_to_hw_instr.cpp +++ b/src/amd/compiler/tests/test_to_hw_instr.cpp @@ -44,7 +44,7 @@ BEGIN_TEST(to_hw_instr.swap_subdword) v1_b3.reg_b += 3; for (unsigned i = GFX6; i <= GFX7; i++) { - if (!setup_cs(NULL, (chip_class)i)) + if (!setup_cs(NULL, (amd_gfx_level)i)) continue; //~gfx[67]>> p_unit_test 0 @@ -224,7 +224,7 @@ BEGIN_TEST(to_hw_instr.swap_subdword) } for (unsigned i = GFX8; i <= GFX9; i++) { - if (!setup_cs(NULL, (chip_class)i)) + if (!setup_cs(NULL, (amd_gfx_level)i)) continue; //~gfx[89]>> p_unit_test 0 @@ -374,7 +374,7 @@ BEGIN_TEST(to_hw_instr.subdword_constant) v1_hi.reg_b += 2; for (unsigned i = GFX9; i <= GFX10; i++) { - if (!setup_cs(NULL, (chip_class)i)) + if (!setup_cs(NULL, (amd_gfx_level)i)) continue; /* 16-bit pack */ @@ -503,7 +503,7 @@ BEGIN_TEST(to_hw_instr.extract) for (unsigned i = GFX7; i <= GFX9; i++) { for (unsigned is_signed = 0; is_signed <= 1; is_signed++) { - if (!setup_cs(NULL, (chip_class)i, CHIP_UNKNOWN, is_signed ? "_signed" : "_unsigned")) + if (!setup_cs(NULL, (amd_gfx_level)i, CHIP_UNKNOWN, is_signed ? "_signed" : "_unsigned")) continue; #define EXT(idx, size) \ @@ -591,7 +591,7 @@ BEGIN_TEST(to_hw_instr.insert) PhysReg v1_lo{257}; for (unsigned i = GFX7; i <= GFX9; i++) { - if (!setup_cs(NULL, (chip_class)i)) + if (!setup_cs(NULL, (amd_gfx_level)i)) continue; #define INS(idx, size) \ diff --git a/src/amd/llvm/ac_llvm_build.c b/src/amd/llvm/ac_llvm_build.c index c03aaf4c5e8..57194a93ce1 100644 --- a/src/amd/llvm/ac_llvm_build.c +++ b/src/amd/llvm/ac_llvm_build.c @@ -56,14 +56,14 @@ struct ac_llvm_flow { * The caller is responsible for initializing ctx::module and ctx::builder. */ void ac_llvm_context_init(struct ac_llvm_context *ctx, struct ac_llvm_compiler *compiler, - enum chip_class chip_class, enum radeon_family family, + enum amd_gfx_level gfx_level, enum radeon_family family, const struct radeon_info *info, enum ac_float_mode float_mode, unsigned wave_size, unsigned ballot_mask_bits) { ctx->context = LLVMContextCreate(); - ctx->chip_class = chip_class; + ctx->gfx_level = gfx_level; ctx->family = family; ctx->info = info; ctx->wave_size = wave_size; @@ -393,7 +393,7 @@ void ac_build_s_barrier(struct ac_llvm_context *ctx, gl_shader_stage stage) /* GFX6 only: s_barrier isn’t needed in TCS because an entire patch always fits into * a single wave due to a bug workaround disallowing multi-wave HS workgroups. */ - if (ctx->chip_class == GFX6 && stage == MESA_SHADER_TESS_CTRL) + if (ctx->gfx_level == GFX6 && stage == MESA_SHADER_TESS_CTRL) return; ac_build_intrinsic(ctx, "llvm.amdgcn.s.barrier", ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT); @@ -865,7 +865,7 @@ void ac_prepare_cube_coords(struct ac_llvm_context *ctx, bool is_deriv, bool is_ * * Clamp the layer earlier to work around the issue. */ - if (ctx->chip_class <= GFX8) { + if (ctx->gfx_level <= GFX8) { LLVMValueRef ge0; ge0 = LLVMBuildFCmp(builder, LLVMRealOGE, tmp, ctx->f32_0, ""); tmp = LLVMBuildSelect(builder, ge0, tmp, ctx->f32_0, ""); @@ -949,7 +949,7 @@ LLVMValueRef ac_build_fs_interp(struct ac_llvm_context *ctx, LLVMValueRef llvm_c { LLVMValueRef args[5]; - if (ctx->chip_class >= GFX11) { + if (ctx->gfx_level >= GFX11) { LLVMValueRef p; LLVMValueRef p10; @@ -1002,7 +1002,7 @@ LLVMValueRef ac_build_fs_interp_f16(struct ac_llvm_context *ctx, LLVMValueRef ll { LLVMValueRef args[6]; - if (ctx->chip_class >= GFX11) { + if (ctx->gfx_level >= GFX11) { LLVMValueRef p; LLVMValueRef p10; @@ -1059,7 +1059,7 @@ LLVMValueRef ac_build_fs_interp_mov(struct ac_llvm_context *ctx, LLVMValueRef pa { LLVMValueRef args[4]; - if (ctx->chip_class >= GFX11) { + if (ctx->gfx_level >= GFX11) { LLVMValueRef p; args[0] = llvm_chan; @@ -1186,12 +1186,12 @@ LLVMValueRef ac_build_load_to_sgpr_uint_wraparound(struct ac_llvm_context *ctx, static unsigned get_load_cache_policy(struct ac_llvm_context *ctx, unsigned cache_policy) { return cache_policy | - (ctx->chip_class >= GFX10 && ctx->chip_class < GFX11 && cache_policy & ac_glc ? ac_dlc : 0); + (ctx->gfx_level >= GFX10 && ctx->gfx_level < GFX11 && cache_policy & ac_glc ? ac_dlc : 0); } static unsigned get_store_cache_policy(struct ac_llvm_context *ctx, unsigned cache_policy) { - if (ctx->chip_class >= GFX11) + if (ctx->gfx_level >= GFX11) cache_policy &= ~ac_glc; /* GLC has no effect on stores */ return cache_policy; } @@ -1239,7 +1239,7 @@ void ac_build_buffer_store_dword(struct ac_llvm_context *ctx, LLVMValueRef rsrc, unsigned num_channels = ac_get_llvm_num_components(vdata); /* Split 3 channel stores if unsupported. */ - if (num_channels == 3 && !ac_has_vec3_support(ctx->chip_class, false)) { + if (num_channels == 3 && !ac_has_vec3_support(ctx->gfx_level, false)) { LLVMValueRef v[3], v01, voffset2; for (int i = 0; i < 3; i++) { @@ -1275,13 +1275,13 @@ static LLVMValueRef ac_build_buffer_load_common(struct ac_llvm_context *ctx, LLV args[idx++] = soffset ? soffset : ctx->i32_0; args[idx++] = LLVMConstInt(ctx->i32, get_load_cache_policy(ctx, cache_policy), 0); unsigned func = - !ac_has_vec3_support(ctx->chip_class, use_format) && num_channels == 3 ? 4 : num_channels; + !ac_has_vec3_support(ctx->gfx_level, use_format) && num_channels == 3 ? 4 : num_channels; const char *indexing_kind = structurized ? "struct" : "raw"; char name[256], type_name[8]; /* D16 is only supported on gfx8+ */ assert(!use_format || (channel_type != ctx->f16 && channel_type != ctx->i16) || - ctx->chip_class >= GFX8); + ctx->gfx_level >= GFX8); LLVMTypeRef type = func > 1 ? LLVMVectorType(channel_type, func) : channel_type; ac_build_type_name_for_intr(type, type_name, sizeof(type_name)); @@ -1302,7 +1302,7 @@ LLVMValueRef ac_build_buffer_load(struct ac_llvm_context *ctx, LLVMValueRef rsrc bool can_speculate, bool allow_smem) { if (allow_smem && !(cache_policy & ac_slc) && - (!(cache_policy & ac_glc) || ctx->chip_class >= GFX8)) { + (!(cache_policy & ac_glc) || ctx->gfx_level >= GFX8)) { assert(vindex == NULL); LLVMValueRef result[8]; @@ -1326,7 +1326,7 @@ LLVMValueRef ac_build_buffer_load(struct ac_llvm_context *ctx, LLVMValueRef rsrc if (num_channels == 1) return result[0]; - if (num_channels == 3 && !ac_has_vec3_support(ctx->chip_class, false)) + if (num_channels == 3 && !ac_has_vec3_support(ctx->gfx_level, false)) result[num_channels++] = LLVMGetUndef(ctx->f32); return ac_build_gather_values(ctx, result, num_channels); } @@ -1394,10 +1394,10 @@ static LLVMValueRef ac_build_tbuffer_load(struct ac_llvm_context *ctx, LLVMValue args[idx++] = vindex ? vindex : ctx->i32_0; args[idx++] = voffset ? voffset : ctx->i32_0; args[idx++] = soffset ? soffset : ctx->i32_0; - args[idx++] = LLVMConstInt(ctx->i32, ac_get_tbuffer_format(ctx->chip_class, dfmt, nfmt), 0); + args[idx++] = LLVMConstInt(ctx->i32, ac_get_tbuffer_format(ctx->gfx_level, dfmt, nfmt), 0); args[idx++] = LLVMConstInt(ctx->i32, get_load_cache_policy(ctx, cache_policy), 0); unsigned func = - !ac_has_vec3_support(ctx->chip_class, true) && num_channels == 3 ? 4 : num_channels; + !ac_has_vec3_support(ctx->gfx_level, true) && num_channels == 3 ? 4 : num_channels; const char *indexing_kind = structurized ? "struct" : "raw"; char name[256], type_name[8]; @@ -1538,7 +1538,7 @@ LLVMValueRef ac_build_opencoded_load_format(struct ac_llvm_context *ctx, unsigne } int log_recombine = 0; - if ((ctx->chip_class == GFX6 || ctx->chip_class >= GFX10) && !known_aligned) { + if ((ctx->gfx_level == GFX6 || ctx->gfx_level >= GFX10) && !known_aligned) { /* Avoid alignment restrictions by loading one byte at a time. */ load_num_channels <<= load_log_size; log_recombine = load_log_size; @@ -1976,7 +1976,7 @@ void ac_build_export(struct ac_llvm_context *ctx, struct ac_export_args *a) args[1] = LLVMConstInt(ctx->i32, a->enabled_channels, 0); if (a->compr) { - assert(ctx->chip_class < GFX11); + assert(ctx->gfx_level < GFX11); args[2] = LLVMBuildBitCast(ctx->builder, a->out[0], ctx->v2i16, ""); args[3] = LLVMBuildBitCast(ctx->builder, a->out[1], ctx->v2i16, ""); @@ -2004,7 +2004,7 @@ void ac_build_export_null(struct ac_llvm_context *ctx) args.valid_mask = 1; /* whether the EXEC mask is valid */ args.done = 1; /* DONE bit */ /* Gfx11 doesn't support null exports, and mrt0 should be exported instead. */ - args.target = ctx->chip_class >= GFX11 ? V_008DFC_SQ_EXP_MRT : V_008DFC_SQ_EXP_NULL; + args.target = ctx->gfx_level >= GFX11 ? V_008DFC_SQ_EXP_MRT : V_008DFC_SQ_EXP_NULL; args.compr = 0; /* COMPR flag (0 = 32-bit export) */ args.out[0] = LLVMGetUndef(ctx->f32); /* R */ args.out[1] = LLVMGetUndef(ctx->f32); /* G */ @@ -2108,11 +2108,11 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx, struct ac_image_ assert((a->bias ? 1 : 0) + (a->lod ? 1 : 0) + (a->level_zero ? 1 : 0) + (a->derivs[0] ? 1 : 0) <= 1); assert((a->min_lod ? 1 : 0) + (a->lod ? 1 : 0) + (a->level_zero ? 1 : 0) <= 1); - assert(!a->d16 || (ctx->chip_class >= GFX8 && a->opcode != ac_image_atomic && + assert(!a->d16 || (ctx->gfx_level >= GFX8 && a->opcode != ac_image_atomic && a->opcode != ac_image_atomic_cmpswap && a->opcode != ac_image_get_lod && a->opcode != ac_image_get_resinfo)); - assert(!a->a16 || ctx->chip_class >= GFX9); - assert(a->g16 == a->a16 || ctx->chip_class >= GFX10); + assert(!a->a16 || ctx->gfx_level >= GFX9); + assert(a->g16 == a->a16 || ctx->gfx_level >= GFX10); assert(!a->offset || ac_get_elem_bits(ctx, LLVMTypeOf(a->offset)) == 32); @@ -2358,7 +2358,7 @@ LLVMValueRef ac_build_cvt_pknorm_i16_f16(struct ac_llvm_context *ctx, LLVMTypeRef param_types[] = {ctx->f16, ctx->f16}; LLVMTypeRef calltype = LLVMFunctionType(ctx->i32, param_types, 2, false); LLVMValueRef code = LLVMConstInlineAsm(calltype, - ctx->chip_class >= GFX11 ? + ctx->gfx_level >= GFX11 ? "v_cvt_pk_norm_i16_f16 $0, $1, $2" : "v_cvt_pknorm_i16_f16 $0, $1, $2", "=v,v,v", false, false); @@ -2371,7 +2371,7 @@ LLVMValueRef ac_build_cvt_pknorm_u16_f16(struct ac_llvm_context *ctx, LLVMTypeRef param_types[] = {ctx->f16, ctx->f16}; LLVMTypeRef calltype = LLVMFunctionType(ctx->i32, param_types, 2, false); LLVMValueRef code = LLVMConstInlineAsm(calltype, - ctx->chip_class >= GFX11 ? + ctx->gfx_level >= GFX11 ? "v_cvt_pk_norm_u16_f16 $0, $1, $2" : "v_cvt_pknorm_u16_f16 $0, $1, $2", "=v,v,v", false, false); @@ -2458,7 +2458,7 @@ LLVMValueRef ac_build_fmad(struct ac_llvm_context *ctx, LLVMValueRef s0, LLVMVal LLVMValueRef s2) { /* FMA is better on GFX10, because it has FMA units instead of MUL-ADD units. */ - if (ctx->chip_class >= GFX10) { + if (ctx->gfx_level >= GFX10) { return ac_build_intrinsic(ctx, "llvm.fma.f32", ctx->f32, (LLVMValueRef[]){s0, s1, s2}, 3, AC_FUNC_ATTR_READNONE); } @@ -2473,7 +2473,7 @@ void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned wait_flags) unsigned expcnt = 7; unsigned lgkmcnt = 63; - unsigned vmcnt = ctx->chip_class >= GFX9 ? 63 : 15; + unsigned vmcnt = ctx->gfx_level >= GFX9 ? 63 : 15; unsigned vscnt = 63; if (wait_flags & AC_WAIT_EXP) @@ -2484,7 +2484,7 @@ void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned wait_flags) vmcnt = 0; if (wait_flags & AC_WAIT_VSTORE) { - if (ctx->chip_class >= GFX10) + if (ctx->gfx_level >= GFX10) vscnt = 0; else vmcnt = 0; @@ -2500,7 +2500,7 @@ void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned wait_flags) unsigned simm16; - if (ctx->chip_class >= GFX11) + if (ctx->gfx_level >= GFX11) simm16 = expcnt | (lgkmcnt << 4) | (vmcnt << 10); else simm16 = (lgkmcnt << 8) | (expcnt << 4) | (vmcnt & 0xf) | ((vmcnt >> 4) << 14); @@ -2519,7 +2519,7 @@ LLVMValueRef ac_build_fsat(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef one = LLVMConstReal(type, 1.0); LLVMValueRef result; - if (bitsize == 64 || (bitsize == 16 && ctx->chip_class <= GFX8) || type == ctx->v2f16) { + if (bitsize == 64 || (bitsize == 16 && ctx->gfx_level <= GFX8) || type == ctx->v2f16) { /* Use fmin/fmax for 64-bit fsat or 16-bit on GFX6-GFX8 because LLVM * doesn't expose an intrinsic. */ @@ -2547,7 +2547,7 @@ LLVMValueRef ac_build_fsat(struct ac_llvm_context *ctx, LLVMValueRef src, AC_FUNC_ATTR_READNONE); } - if (ctx->chip_class < GFX9 && bitsize == 32) { + if (ctx->gfx_level < GFX9 && bitsize == 32) { /* Only pre-GFX9 chips do not flush denorms. */ result = ac_build_canonicalize(ctx, result, bitsize); } @@ -2741,7 +2741,7 @@ void ac_init_exec_full_mask(struct ac_llvm_context *ctx) void ac_declare_lds_as_pointer(struct ac_llvm_context *ctx) { - unsigned lds_size = ctx->chip_class >= GFX7 ? 65536 : 32768; + unsigned lds_size = ctx->gfx_level >= GFX7 ? 65536 : 32768; ctx->lds = LLVMBuildIntToPtr( ctx->builder, ctx->i32_0, LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), AC_ADDR_SPACE_LDS), "lds"); @@ -3642,7 +3642,7 @@ static LLVMValueRef ac_build_alu_op(struct ac_llvm_context *ctx, LLVMValueRef lh static LLVMValueRef ac_wavefront_shift_right_1(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef identity, unsigned maxprefix) { - if (ctx->chip_class >= GFX10) { + if (ctx->gfx_level >= GFX10) { /* wavefront shift_right by 1 on GFX10 (emulate dpp_wf_sr1) */ LLVMValueRef active, tmp1, tmp2; LLVMValueRef tid = ac_get_thread_id(ctx); @@ -3672,7 +3672,7 @@ static LLVMValueRef ac_wavefront_shift_right_1(struct ac_llvm_context *ctx, LLVM return LLVMBuildSelect(ctx->builder, active, tmp2, tmp1, ""); } - } else if (ctx->chip_class >= GFX8) { + } else if (ctx->gfx_level >= GFX8) { return ac_build_dpp(ctx, identity, src, dpp_wf_sr1, 0xf, 0xf, false); } @@ -3716,7 +3716,7 @@ static LLVMValueRef ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMVa result = src; - if (ctx->chip_class <= GFX7) { + if (ctx->gfx_level <= GFX7) { assert(maxprefix == 64); LLVMValueRef tid = ac_get_thread_id(ctx); LLVMValueRef active; @@ -3781,7 +3781,7 @@ static LLVMValueRef ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMVa if (maxprefix <= 16) return result; - if (ctx->chip_class >= GFX10) { + if (ctx->gfx_level >= GFX10) { LLVMValueRef tid = ac_get_thread_id(ctx); LLVMValueRef active; @@ -3882,7 +3882,7 @@ LLVMValueRef ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_ if (cluster_size == 4) return ac_build_wwm(ctx, result); - if (ctx->chip_class >= GFX8) + if (ctx->gfx_level >= GFX8) swap = ac_build_dpp(ctx, identity, result, dpp_row_half_mirror, 0xf, 0xf, false); else swap = ac_build_ds_swizzle(ctx, result, ds_pattern_bitmode(0x1f, 0, 0x04)); @@ -3890,7 +3890,7 @@ LLVMValueRef ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_ if (cluster_size == 8) return ac_build_wwm(ctx, result); - if (ctx->chip_class >= GFX8) + if (ctx->gfx_level >= GFX8) swap = ac_build_dpp(ctx, identity, result, dpp_row_mirror, 0xf, 0xf, false); else swap = ac_build_ds_swizzle(ctx, result, ds_pattern_bitmode(0x1f, 0, 0x08)); @@ -3898,9 +3898,9 @@ LLVMValueRef ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_ if (cluster_size == 16) return ac_build_wwm(ctx, result); - if (ctx->chip_class >= GFX10) + if (ctx->gfx_level >= GFX10) swap = ac_build_permlane16(ctx, result, 0, true, false); - else if (ctx->chip_class >= GFX8 && cluster_size != 32) + else if (ctx->gfx_level >= GFX8 && cluster_size != 32) swap = ac_build_dpp(ctx, identity, result, dpp_row_bcast15, 0xa, 0xf, false); else swap = ac_build_ds_swizzle(ctx, result, ds_pattern_bitmode(0x1f, 0, 0x10)); @@ -3908,9 +3908,9 @@ LLVMValueRef ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_ if (cluster_size == 32) return ac_build_wwm(ctx, result); - if (ctx->chip_class >= GFX8) { + if (ctx->gfx_level >= GFX8) { if (ctx->wave_size == 64) { - if (ctx->chip_class >= GFX10) + if (ctx->gfx_level >= GFX10) swap = ac_build_readlane(ctx, result, LLVMConstInt(ctx->i32, 31, false)); else swap = ac_build_dpp(ctx, identity, result, dpp_row_bcast31, 0xc, 0xf, false); @@ -4134,7 +4134,7 @@ void ac_build_dual_src_blend_swizzle(struct ac_llvm_context *ctx, struct ac_export_args *mrt0, struct ac_export_args *mrt1) { - assert(ctx->chip_class >= GFX11); + assert(ctx->gfx_level >= GFX11); assert(mrt0->enabled_channels == mrt1->enabled_channels); for (int i = 0; i < 4; i++) { @@ -4147,7 +4147,7 @@ LLVMValueRef ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src unsigned lane1, unsigned lane2, unsigned lane3) { unsigned mask = dpp_quad_perm(lane0, lane1, lane2, lane3); - if (ctx->chip_class >= GFX8) { + if (ctx->gfx_level >= GFX8) { return ac_build_dpp(ctx, src, src, mask, 0xf, 0xf, false); } else { return ac_build_ds_swizzle(ctx, src, (1 << 15) | mask); @@ -4316,23 +4316,23 @@ void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueR if (format == V_028710_SPI_SHADER_UINT16_ABGR) { assert(!depth); - args->compr = ctx->chip_class < GFX11; /* COMPR flag */ + args->compr = ctx->gfx_level < GFX11; /* COMPR flag */ if (stencil) { /* Stencil should be in X[23:16]. */ stencil = ac_to_integer(ctx, stencil); stencil = LLVMBuildShl(ctx->builder, stencil, LLVMConstInt(ctx->i32, 16, 0), ""); args->out[0] = ac_to_float(ctx, stencil); - mask |= ctx->chip_class >= GFX11 ? 0x1 : 0x3; + mask |= ctx->gfx_level >= GFX11 ? 0x1 : 0x3; } if (samplemask) { /* SampleMask should be in Y[15:0]. */ args->out[1] = samplemask; - mask |= ctx->chip_class >= GFX11 ? 0x2 : 0xc; + mask |= ctx->gfx_level >= GFX11 ? 0x2 : 0xc; } if (mrtz_alpha) { /* MRT0 alpha should be in Y[31:16] if alpha-to-coverage is enabled and MRTZ is present. */ - assert(ctx->chip_class >= GFX11); + assert(ctx->gfx_level >= GFX11); mrtz_alpha = LLVMBuildFPTrunc(ctx->builder, mrtz_alpha, ctx->f16, ""); mrtz_alpha = ac_to_integer(ctx, mrtz_alpha); mrtz_alpha = LLVMBuildZExt(ctx->builder, mrtz_alpha, ctx->i32, ""); @@ -4362,7 +4362,7 @@ void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueR /* GFX6 (except OLAND and HAINAN) has a bug that it only looks * at the X writemask component. */ - if (ctx->chip_class == GFX6 && ctx->family != CHIP_OLAND && ctx->family != CHIP_HAINAN) + if (ctx->gfx_level == GFX6 && ctx->family != CHIP_OLAND && ctx->family != CHIP_HAINAN) mask |= 0x1; /* Specify which components to enable */ @@ -4385,7 +4385,7 @@ void ac_build_sendmsg_gs_alloc_req(struct ac_llvm_context *ctx, LLVMValueRef wav * We always have to export at least 1 primitive. * Export a degenerate triangle using vertex 0 for all 3 vertices. */ - if (prim_cnt == ctx->i32_0 && ctx->chip_class == GFX10) { + if (prim_cnt == ctx->i32_0 && ctx->gfx_level == GFX10) { assert(vtx_cnt == ctx->i32_0); prim_cnt = ctx->i32_1; vtx_cnt = ctx->i32_1; diff --git a/src/amd/llvm/ac_llvm_build.h b/src/amd/llvm/ac_llvm_build.h index 94f4e75b30c..d5ca14a8d1c 100644 --- a/src/amd/llvm/ac_llvm_build.h +++ b/src/amd/llvm/ac_llvm_build.h @@ -132,7 +132,7 @@ struct ac_llvm_context { unsigned uniform_md_kind; LLVMValueRef empty_md; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; enum radeon_family family; const struct radeon_info *info; @@ -145,7 +145,7 @@ struct ac_llvm_context { }; void ac_llvm_context_init(struct ac_llvm_context *ctx, struct ac_llvm_compiler *compiler, - enum chip_class chip_class, enum radeon_family family, + enum amd_gfx_level gfx_level, enum radeon_family family, const struct radeon_info *info, enum ac_float_mode float_mode, unsigned wave_size, unsigned ballot_mask_bits); diff --git a/src/amd/llvm/ac_llvm_util.c b/src/amd/llvm/ac_llvm_util.c index c8ed0b09c2f..d83d82beba5 100644 --- a/src/amd/llvm/ac_llvm_util.c +++ b/src/amd/llvm/ac_llvm_util.c @@ -328,9 +328,9 @@ void ac_llvm_set_target_features(LLVMValueRef F, struct ac_llvm_context *ctx) snprintf(features, sizeof(features), "+DumpCode%s%s", /* GFX9 has broken VGPR indexing, so always promote alloca to scratch. */ - ctx->chip_class == GFX9 ? ",-promote-alloca" : "", + ctx->gfx_level == GFX9 ? ",-promote-alloca" : "", /* Wave32 is the default. */ - ctx->chip_class >= GFX10 && ctx->wave_size == 64 ? + ctx->gfx_level >= GFX10 && ctx->wave_size == 64 ? ",+wavefrontsize64,-wavefrontsize32" : ""); LLVMAddTargetDependentFunctionAttr(F, "target-features", features); diff --git a/src/amd/llvm/ac_llvm_util.h b/src/amd/llvm/ac_llvm_util.h index 3c76c716a15..79bab0211c4 100644 --- a/src/amd/llvm/ac_llvm_util.h +++ b/src/amd/llvm/ac_llvm_util.h @@ -129,7 +129,7 @@ bool ac_compile_module_to_elf(struct ac_compiler_passes *p, LLVMModuleRef module char **pelf_buffer, size_t *pelf_size); void ac_llvm_add_barrier_noop_pass(LLVMPassManagerRef passmgr); -static inline bool ac_has_vec3_support(enum chip_class chip, bool use_format) +static inline bool ac_has_vec3_support(enum amd_gfx_level chip, bool use_format) { /* GFX6 only supports vec3 with load/store format. */ return chip != GFX6 || use_format; diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 379c88f2b2d..61e8e8fa7ad 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -339,7 +339,7 @@ static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx, LLVMValueRef src0) src0 = ac_to_float(ctx, src0); result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, ""); - if (ctx->chip_class >= GFX8) { + if (ctx->gfx_level >= GFX8) { LLVMValueRef args[2]; /* Check if the result is a denormal - and flush to 0 if so. */ args[0] = result; @@ -351,7 +351,7 @@ static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx, LLVMValueRef src0) /* need to convert back up to f32 */ result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, ""); - if (ctx->chip_class >= GFX8) + if (ctx->gfx_level >= GFX8) result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, ""); else { /* for GFX6-GFX7 */ @@ -901,7 +901,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) case nir_op_fmax: result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum", ac_to_float_type(&ctx->ac, def_type), src[0], src[1]); - if (ctx->ac.chip_class < GFX9 && instr->dest.dest.ssa.bit_size == 32) { + if (ctx->ac.gfx_level < GFX9 && instr->dest.dest.ssa.bit_size == 32) { /* Only pre-GFX9 chips do not flush denorms. */ result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size); } @@ -909,19 +909,19 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) case nir_op_fmin: result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum", ac_to_float_type(&ctx->ac, def_type), src[0], src[1]); - if (ctx->ac.chip_class < GFX9 && instr->dest.dest.ssa.bit_size == 32) { + if (ctx->ac.gfx_level < GFX9 && instr->dest.dest.ssa.bit_size == 32) { /* Only pre-GFX9 chips do not flush denorms. */ result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size); } break; case nir_op_ffma: /* FMA is slow on gfx6-8, so it shouldn't be used. */ - assert(instr->dest.dest.ssa.bit_size != 32 || ctx->ac.chip_class >= GFX9); + assert(instr->dest.dest.ssa.bit_size != 32 || ctx->ac.gfx_level >= GFX9); result = emit_intrin_3f_param(&ctx->ac, "llvm.fma", ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]); break; case nir_op_ffmaz: - assert(LLVM_VERSION_MAJOR >= 12 && ctx->ac.chip_class >= GFX10_3); + assert(LLVM_VERSION_MAJOR >= 12 && ctx->ac.gfx_level >= GFX10_3); src[0] = ac_to_float(&ctx->ac, src[0]); src[1] = ac_to_float(&ctx->ac, src[1]); src[2] = ac_to_float(&ctx->ac, src[2]); @@ -1386,7 +1386,7 @@ static LLVMValueRef get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef des LLVMBuildExtractElement(ctx->ac.builder, descriptor, LLVMConstInt(ctx->ac.i32, 2, false), ""); /* GFX8 only */ - if (ctx->ac.chip_class == GFX8 && in_elements) { + if (ctx->ac.gfx_level == GFX8 && in_elements) { /* On GFX8, the descriptor contains the size in bytes, * but TXQ must return the size in elements. * The stride is always non-zero for resources using TXQ. @@ -1486,7 +1486,7 @@ static LLVMValueRef lower_gather4_integer(struct ac_llvm_context *ctx, struct ac } /* Query the texture size. */ - resinfo.dim = ac_get_sampler_dim(ctx->chip_class, instr->sampler_dim, instr->is_array); + resinfo.dim = ac_get_sampler_dim(ctx->gfx_level, instr->sampler_dim, instr->is_array); resinfo.opcode = ac_image_get_resinfo; resinfo.dmask = 0xf; resinfo.lod = ctx->i32_0; @@ -1611,13 +1611,13 @@ static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx, const nir_te if (!ctx->ac.info->has_3d_cube_border_color_mipmap) args->level_zero = false; - if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= GFX8 && + if (instr->op == nir_texop_tg4 && ctx->ac.gfx_level <= GFX8 && (instr->dest_type & (nir_type_int | nir_type_uint))) { return lower_gather4_integer(&ctx->ac, args, instr); } /* Fixup for GFX9 which allocates 1D textures as 2D. */ - if (instr->op == nir_texop_lod && ctx->ac.chip_class == GFX9) { + if (instr->op == nir_texop_lod && ctx->ac.gfx_level == GFX9) { if ((args->dim == ac_image_2darray || args->dim == ac_image_2d) && !args->coords[1]) { args->coords[1] = ctx->ac.i32_0; } @@ -1777,7 +1777,7 @@ static unsigned get_cache_policy(struct ac_nir_context *ctx, enum gl_access_qual * store opcodes not aligned to a dword are affected. The only way to * get unaligned stores is through shader images. */ - if (((may_store_unaligned && ctx->ac.chip_class == GFX6) || + if (((may_store_unaligned && ctx->ac.gfx_level == GFX6) || /* If this is write-only, don't keep data in L1 to prevent * evicting L1 cache lines that may be needed by other * instructions. @@ -1852,7 +1852,7 @@ static void visit_store_ssbo(struct ac_nir_context *ctx, nir_intrinsic_instr *in /* Due to alignment issues, split stores of 8-bit/16-bit * vectors. */ - if (ctx->ac.chip_class == GFX6 && count > 1 && elem_size_bytes < 4) { + if (ctx->ac.gfx_level == GFX6 && count > 1 && elem_size_bytes < 4) { writemask |= ((1u << (count - 1)) - 1u) << (start + 1); count = 1; num_bytes = elem_size_bytes; @@ -2486,11 +2486,11 @@ static void get_image_coords(struct ac_nir_context *ctx, const nir_intrinsic_ins ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS); bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS); - bool gfx9_1d = ctx->ac.chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D; + bool gfx9_1d = ctx->ac.gfx_level == GFX9 && dim == GLSL_SAMPLER_DIM_1D; assert(!add_frag_pos && "Input attachments should be lowered by this point."); count = image_type_to_components_count(dim, is_array); - if (ctx->ac.chip_class < GFX11 && + if (ctx->ac.gfx_level < GFX11 && is_ms && (instr->intrinsic == nir_intrinsic_image_deref_load || instr->intrinsic == nir_intrinsic_bindless_image_load || instr->intrinsic == nir_intrinsic_image_deref_sparse_load || @@ -2529,7 +2529,7 @@ static void get_image_coords(struct ac_nir_context *ctx, const nir_intrinsic_ins args->coords[1] = ctx->ac.i32_0; count++; } - if (ctx->ac.chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_2D && !is_array) { + if (ctx->ac.gfx_level == GFX9 && dim == GLSL_SAMPLER_DIM_2D && !is_array) { /* The hw can't bind a slice of a 3D image as a 2D * image, because it ignores BASE_ARRAY if the target * is 3D. The workaround is to read BASE_ARRAY and set @@ -2621,7 +2621,7 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx, const nir_intri args.opcode = level_zero ? ac_image_load : ac_image_load_mip; args.resource = get_image_descriptor(ctx, instr, dynamic_index, AC_DESC_IMAGE, false); get_image_coords(ctx, instr, dynamic_index, &args, dim, is_array); - args.dim = ac_get_image_dim(ctx->ac.chip_class, dim, is_array); + args.dim = ac_get_image_dim(ctx->ac.gfx_level, dim, is_array); if (!level_zero) args.lod = get_src(ctx, instr->src[3]); args.dmask = 15; @@ -2713,7 +2713,7 @@ static void visit_image_store(struct ac_nir_context *ctx, const nir_intrinsic_in args.data[0] = src; args.resource = get_image_descriptor(ctx, instr, dynamic_index, AC_DESC_IMAGE, true); get_image_coords(ctx, instr, dynamic_index, &args, dim, is_array); - args.dim = ac_get_image_dim(ctx->ac.chip_class, dim, is_array); + args.dim = ac_get_image_dim(ctx->ac.gfx_level, dim, is_array); if (!level_zero) args.lod = get_src(ctx, instr->src[4]); args.dmask = 15; @@ -2872,7 +2872,7 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx, const nir_int args.data[1] = params[1]; args.resource = get_image_descriptor(ctx, instr, dynamic_index, AC_DESC_IMAGE, true); get_image_coords(ctx, instr, dynamic_index, &args, dim, is_array); - args.dim = ac_get_image_dim(ctx->ac.chip_class, dim, is_array); + args.dim = ac_get_image_dim(ctx->ac.gfx_level, dim, is_array); result = ac_build_image_opcode(&ctx->ac, &args); } @@ -2932,7 +2932,7 @@ static LLVMValueRef visit_image_size(struct ac_nir_context *ctx, const nir_intri struct ac_image_args args = {0}; - args.dim = ac_get_image_dim(ctx->ac.chip_class, dim, is_array); + args.dim = ac_get_image_dim(ctx->ac.gfx_level, dim, is_array); args.dmask = 0xf; args.resource = get_image_descriptor(ctx, instr, dynamic_index, AC_DESC_IMAGE, false); args.opcode = ac_image_get_resinfo; @@ -2942,7 +2942,7 @@ static LLVMValueRef visit_image_size(struct ac_nir_context *ctx, const nir_intri res = ac_build_image_opcode(&ctx->ac, &args); - if (ctx->ac.chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D && is_array) { + if (ctx->ac.gfx_level == GFX9 && dim == GLSL_SAMPLER_DIM_1D && is_array) { LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false); LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, ""); res = LLVMBuildInsertElement(ctx->ac.builder, res, layers, ctx->ac.i32_1, ""); @@ -3664,7 +3664,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins if (ctx->stage == MESA_SHADER_TESS_CTRL) { result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->tcs_rel_ids), 8, 5); } else { - if (ctx->ac.chip_class >= GFX10) { + if (ctx->ac.gfx_level >= GFX10) { result = LLVMBuildAnd(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args->gs_invocation_id), LLVMConstInt(ctx->ac.i32, 127, 0), ""); @@ -4040,8 +4040,8 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins break; } case nir_intrinsic_shuffle: - if (ctx->ac.chip_class == GFX8 || ctx->ac.chip_class == GFX9 || - (ctx->ac.chip_class >= GFX10 && ctx->ac.wave_size == 32)) { + if (ctx->ac.gfx_level == GFX8 || ctx->ac.gfx_level == GFX9 || + (ctx->ac.gfx_level >= GFX10 && ctx->ac.wave_size == 32)) { result = ac_build_shuffle(&ctx->ac, get_src(ctx, instr->src[0]), get_src(ctx, instr->src[1])); } else { @@ -4477,7 +4477,7 @@ static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx, LLVMValue LLVMBuilderRef builder = ctx->ac.builder; LLVMValueRef img7, samp0; - if (ctx->ac.chip_class >= GFX8) + if (ctx->ac.gfx_level >= GFX8) return samp; img7 = LLVMBuildExtractElement(builder, res, LLVMConstInt(ctx->ac.i32, 7, 0), ""); @@ -4550,7 +4550,7 @@ static void tex_fetch_ptrs(struct ac_nir_context *ctx, nir_tex_instr *instr, /* The fragment mask is fetched from the compressed * multisampled surface. */ - assert(ctx->ac.chip_class < GFX11); + assert(ctx->ac.gfx_level < GFX11); main_descriptor = AC_DESC_FMASK; } @@ -4593,7 +4593,7 @@ static void tex_fetch_ptrs(struct ac_nir_context *ctx, nir_tex_instr *instr, if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT) *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr); } - if (ctx->ac.chip_class < GFX11 && + if (ctx->ac.gfx_level < GFX11 && fmask_ptr && (instr->op == nir_texop_txf_ms || instr->op == nir_texop_samples_identical)) *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, AC_DESC_FMASK, &instr->instr, texture_dynamic_index, false, false); @@ -4747,7 +4747,7 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr) * Z24 anymore. Do it manually here for GFX8-9; GFX10 has * an explicitly clamped 32-bit float format. */ - if (args.compare && ctx->ac.chip_class >= GFX8 && ctx->ac.chip_class <= GFX9 && + if (args.compare && ctx->ac.gfx_level >= GFX8 && ctx->ac.gfx_level <= GFX9 && ctx->abi->clamp_shadow_reference) { LLVMValueRef upgraded, clamped; @@ -4775,7 +4775,7 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr) break; case GLSL_SAMPLER_DIM_1D: num_src_deriv_channels = 1; - if (ctx->ac.chip_class == GFX9) { + if (ctx->ac.gfx_level == GFX9) { num_dest_deriv_channels = 2; } else { num_dest_deriv_channels = 1; @@ -4819,7 +4819,7 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr) args.coords[2] = apply_round_slice(&ctx->ac, args.coords[2]); } - if (ctx->ac.chip_class == GFX9 && instr->sampler_dim == GLSL_SAMPLER_DIM_1D && + if (ctx->ac.gfx_level == GFX9 && instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->op != nir_texop_lod) { LLVMValueRef filler; if (instr->op == nir_texop_txf) @@ -4837,7 +4837,7 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr) args.coords[instr->coord_components] = sample_index; if (instr->op == nir_texop_samples_identical) { - assert(ctx->ac.chip_class < GFX11); + assert(ctx->ac.gfx_level < GFX11); struct ac_image_args txf_args = {0}; memcpy(txf_args.coords, args.coords, sizeof(txf_args.coords)); @@ -4851,7 +4851,7 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr) goto write_result; } - if (ctx->ac.chip_class < GFX11 && + if (ctx->ac.gfx_level < GFX11 && (instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS || instr->sampler_dim == GLSL_SAMPLER_DIM_MS) && instr->op != nir_texop_txs && instr->op != nir_texop_fragment_fetch_amd && @@ -4890,7 +4890,7 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr) } if (instr->sampler_dim != GLSL_SAMPLER_DIM_BUF) { - args.dim = ac_get_sampler_dim(ctx->ac.chip_class, instr->sampler_dim, instr->is_array); + args.dim = ac_get_sampler_dim(ctx->ac.gfx_level, instr->sampler_dim, instr->is_array); args.unorm = instr->sampler_dim == GLSL_SAMPLER_DIM_RECT; } @@ -4932,7 +4932,7 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr) else if (instr->is_shadow && instr->is_new_style_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4) result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, ""); - else if (ctx->ac.chip_class == GFX9 && instr->op == nir_texop_txs && + else if (ctx->ac.gfx_level == GFX9 && instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array) { LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false); LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, ""); diff --git a/src/amd/registers/parse_kernel_headers.py b/src/amd/registers/parse_kernel_headers.py index b5e40a6eef3..4bae19597ff 100644 --- a/src/amd/registers/parse_kernel_headers.py +++ b/src/amd/registers/parse_kernel_headers.py @@ -5,7 +5,7 @@ from canonicalize import json_canonicalize ######### BEGIN HARDCODED CONFIGURATION -gfx_versions = { +gfx_levels = { 'gfx6': [ [], 'asic_reg/gca/gfx_6_0_d.h', @@ -68,7 +68,7 @@ re_shift = re.compile(r'^#define (?P<name>\w+)__(?P<field>\w+)__SHIFT\s+(?P<valu # match: #define SDMA0_DEC_START__START_MASK 0xFFFFFFFF re_mask = re.compile(r'^#define (?P<name>\w+)__(?P<field>\w+)_MASK\s+(?P<value>[0-9a-fA-Fx]+)L?\n') -def register_filter(gfx_version, name, offset, already_added): +def register_filter(gfx_level, name, offset, already_added): # Only accept writeable registers and debug registers return ((offset // 0x1000 in [0xB, 0x28, 0x30, 0x31, 0x34, 0x35, 0x36, 0x37] or # Add SQ_WAVE registers for trap handlers @@ -81,7 +81,7 @@ def register_filter(gfx_version, name, offset, already_added): name.startswith('GRBM_STATUS') or name.startswith('CP_CP'))) or # Add all registers in the 0x8000 range for gfx6 - (gfx_version == 'gfx6' and offset // 0x1000 == 0x8) or + (gfx_level == 'gfx6' and offset // 0x1000 == 0x8) or # Add registers in the 0x9000 range (offset // 0x1000 == 0x9 and (name in ['TA_CS_BC_BASE_ADDR', 'GB_ADDR_CONFIG', 'SPI_CONFIG_CNTL'] or @@ -689,11 +689,11 @@ fields_missing = { def bitcount(n): return bin(n).count('1') -def generate_json(gfx_version, amd_headers_path): - gc_base_offsets = gfx_versions[gfx_version][0] +def generate_json(gfx_level, amd_headers_path): + gc_base_offsets = gfx_levels[gfx_level][0] # Add the path to the filenames - filenames = [amd_headers_path + '/' + a for a in gfx_versions[gfx_version][1:]] + filenames = [amd_headers_path + '/' + a for a in gfx_levels[gfx_level][1:]] # Open the files files = [open(a, 'r').readlines() if a is not None else None for a in filenames] @@ -726,9 +726,9 @@ def generate_json(gfx_version, amd_headers_path): name = name[:-4] # Only accept writeable registers and debug registers - if register_filter(gfx_version, name, offset, offset in added_offsets): + if register_filter(gfx_level, name, offset, offset in added_offsets): regs[name] = { - 'chips': [gfx_version], + 'chips': [gfx_level], 'map': {'at': offset, 'to': 'mm'}, 'name': name, } @@ -765,7 +765,7 @@ def generate_json(gfx_version, amd_headers_path): re_enum_end = re.compile(r'^} \w+;\n') inside_enum = False name = None - enums = enums_missing[gfx_version] if gfx_version in enums_missing else {} + enums = enums_missing[gfx_level] if gfx_level in enums_missing else {} for line in files[2]: r = re_enum_begin.match(line) @@ -795,7 +795,7 @@ def generate_json(gfx_version, amd_headers_path): # Assemble everything reg_types = {} reg_mappings = [] - missing_fields = fields_missing[gfx_version] if gfx_version in fields_missing else {} + missing_fields = fields_missing[gfx_level] if gfx_level in fields_missing else {} for (name, reg) in regs.items(): type = {'fields': []} @@ -823,7 +823,7 @@ def generate_json(gfx_version, amd_headers_path): if type_name is not None: if type_name not in enums: print('{0}: {1} type not found for {2}.{3}' - .format(gfx_version, type_name, name, field), file=sys.stderr) + .format(gfx_level, type_name, name, field), file=sys.stderr) else: new['enum_ref'] = type_name @@ -868,8 +868,8 @@ def generate_json(gfx_version, amd_headers_path): if __name__ == '__main__': - if len(sys.argv) <= 1 or (sys.argv[1] not in gfx_versions and sys.argv[1] != 'all'): - print('First parameter should be one of: all, ' + ', '.join(gfx_versions.keys()), file=sys.stderr) + if len(sys.argv) <= 1 or (sys.argv[1] not in gfx_levels and sys.argv[1] != 'all'): + print('First parameter should be one of: all, ' + ', '.join(gfx_levels.keys()), file=sys.stderr) sys.exit(1) if len(sys.argv) <= 2: @@ -877,8 +877,8 @@ if __name__ == '__main__': sys.exit(1) if sys.argv[1] == 'all': - for gfx_version in gfx_versions.keys(): - print(generate_json(gfx_version, sys.argv[2]), file=open(gfx_version + '.json', 'w')) + for gfx_level in gfx_levels.keys(): + print(generate_json(gfx_level, sys.argv[2]), file=open(gfx_level + '.json', 'w')) sys.exit(0) print(generate_json(sys.argv[1], sys.argv[2])) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index ecc1c39f3cc..2ee40db7191 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -353,7 +353,7 @@ bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer) { return cmd_buffer->qf == RADV_QUEUE_COMPUTE && - cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7; + cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7; } enum amd_ip_type @@ -527,7 +527,7 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->descriptors[i].push_dirty = false; } - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 && + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9 && cmd_buffer->qf == RADV_QUEUE_GENERAL) { unsigned num_db = cmd_buffer->device->physical_device->rad_info.max_render_backends; unsigned fence_offset, eop_bug_offset; @@ -541,7 +541,7 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer) radv_emit_clear_data(cmd_buffer, V_370_PFP, cmd_buffer->gfx9_fence_va, 8); - if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) { /* Allocate a buffer for the EOP bug on GFX9. */ radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, &eop_bug_offset, &fence_ptr); memset(fence_ptr, 0, 16 * num_db); @@ -618,7 +618,7 @@ radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer, unsigned size, * being placed in less of them. */ unsigned offset = cmd_buffer->upload.offset; - unsigned line_size = rad_info->chip_class >= GFX10 ? 64 : 32; + unsigned line_size = rad_info->gfx_level >= GFX10 ? 64 : 32; unsigned gap = align(offset, line_size) - offset; if ((size & (line_size - 1)) > gap) offset = align(offset, line_size); @@ -686,7 +686,7 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, enum radv_cmd_flu /* Force wait for graphics or compute engines to be idle. */ si_cs_emit_cache_flush(cmd_buffer->cs, - cmd_buffer->device->physical_device->rad_info.chip_class, + cmd_buffer->device->physical_device->rad_info.gfx_level, &cmd_buffer->gfx9_fence_idx, cmd_buffer->gfx9_fence_va, radv_cmd_buffer_uses_mec(cmd_buffer), flags, &sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va); @@ -1058,7 +1058,7 @@ radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeli { const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline; - if (pipeline->device->physical_device->rad_info.chip_class < GFX9) + if (pipeline->device->physical_device->rad_info.gfx_level < GFX9) return; if (old_pipeline && @@ -1070,7 +1070,7 @@ radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeli if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 || cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 || cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 || - cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) { + cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) { binning_flush = !old_pipeline || G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) != G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0); @@ -1586,7 +1586,7 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer) assert(!cmd_buffer->state.mesh_shading); - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) { radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, d->primitive_topology); } else { @@ -1648,7 +1648,7 @@ radv_emit_fragment_shading_rate(struct radv_cmd_buffer *cmd_buffer) uint32_t pipeline_comb_mode = d->fragment_shading_rate.combiner_ops[0]; uint32_t htile_comb_mode = d->fragment_shading_rate.combiner_ops[1]; - assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3); + assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10_3); if (subpass && !subpass->vrs_attachment) { /* When the current subpass has no VRS attachment, the VRS rates are expected to be 1x1, so we @@ -1706,7 +1706,7 @@ radv_emit_primitive_restart_enable(struct radv_cmd_buffer *cmd_buffer) { struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, d->primitive_restart_enable); } else { @@ -1754,7 +1754,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, struct radv_color_buffer_info *cb, struct radv_image_view *iview, VkImageLayout layout, bool in_render_loop) { - bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8; + bool is_vi = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX8; uint32_t cb_color_info = cb->cb_color_info; struct radv_image *image = iview->image; @@ -1780,7 +1780,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY; } - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) { radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); radeon_emit(cmd_buffer->cs, cb->cb_color_base); radeon_emit(cmd_buffer->cs, 0); @@ -1808,7 +1808,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, cb->cb_color_attrib2); radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4, cb->cb_color_attrib3); - } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { + } else if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) { radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); radeon_emit(cmd_buffer->cs, cb->cb_color_base); radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32)); @@ -1884,7 +1884,7 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_ db_z_info &= C_028040_ZRANGE_PRECISION; - if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) { db_z_info_reg = R_028038_DB_Z_INFO; } else { db_z_info_reg = R_028040_DB_Z_INFO; @@ -1924,7 +1924,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_ db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1); } - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 && + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10_3 && !cmd_buffer->state.subpass->vrs_attachment) { db_htile_surface &= C_028ABC_VRS_HTILE_ENCODING; } @@ -1932,7 +1932,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_ radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view); radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, db_htile_surface); - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) { radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base); radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size); @@ -1951,7 +1951,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_ radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32); - } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { + } else if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) { radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3); radeon_emit(cmd_buffer->cs, ds->db_htile_data_base); radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32)); @@ -2420,7 +2420,7 @@ radv_emit_fb_mip_change_flush(struct radv_cmd_buffer *cmd_buffer) bool color_mip_changed = false; /* Entire workaround is not applicable before GFX9 */ - if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9) + if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX9) return; if (!framebuffer) @@ -2456,7 +2456,7 @@ static void radv_emit_mip_change_flush_default(struct radv_cmd_buffer *cmd_buffer) { /* Entire workaround is not applicable before GFX9 */ - if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9) + if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX9) return; bool need_color_mip_flush = false; @@ -2523,7 +2523,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) radv_load_color_clear_metadata(cmd_buffer, iview, i); - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 && + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9 && iview->image->dcc_sign_reinterpret) { /* Disable constant encoding with the clear value of "1" with different DCC signedness * because the hardware will fill "1" instead of the clear value. @@ -2592,7 +2592,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) radv_image_view_finish(&iview); } else { - if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) + if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2); else radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2); @@ -2603,17 +2603,18 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR, S_028208_BR_X(framebuffer->width) | S_028208_BR_Y(framebuffer->height)); - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX8) { bool disable_constant_encode = cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode; - enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class; - uint8_t watermark = chip_class >= GFX10 ? 6 : 4; + enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level; + uint8_t watermark = gfx_level >= GFX10 ? 6 : 4; - radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL, - S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) | - S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) | - S_028424_DISABLE_CONSTANT_ENCODE_AC01(disable_constant_encode_ac01) | - S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode)); + radeon_set_context_reg( + cmd_buffer->cs, R_028424_CB_DCC_CONTROL, + S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(gfx_level <= GFX9) | + S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) | + S_028424_DISABLE_CONSTANT_ENCODE_AC01(disable_constant_encode_ac01) | + S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode)); } cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER; @@ -2649,7 +2650,7 @@ radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer, bool enable_occlus uint32_t db_count_control; if (!enable_occlusion_queries) { - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) { if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) && pipeline->graphics.disable_out_of_order_rast_for_occlusion && has_perfect_queries) { /* Re-enable out-of-order rasterization if the @@ -2665,9 +2666,9 @@ radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer, bool enable_occlus const struct radv_subpass *subpass = cmd_buffer->state.subpass; uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0; bool gfx10_perfect = - cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries; + cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10 && has_perfect_queries; - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) { /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially * covered tiles, discards, and early depth testing. For more details, * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */ @@ -2786,7 +2787,7 @@ lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *vs_shad uint32_t instance_rate_inputs = state->instance_rate_inputs & attribute_mask; uint32_t zero_divisors = state->zero_divisors & attribute_mask; *nontrivial_divisors = state->nontrivial_divisors & attribute_mask; - enum chip_class chip = device->physical_device->rad_info.chip_class; + enum amd_gfx_level chip = device->physical_device->rad_info.gfx_level; const uint32_t misaligned_mask = chip == GFX6 || chip >= GFX10 ? cmd_buffer->state.vbo_misaligned_mask : 0; /* try to use a pre-compiled prolog first */ @@ -2914,7 +2915,7 @@ emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *vs_shad if (cmd_buffer->state.emitted_vs_prolog == prolog && !pipeline_is_dirty) return; - enum chip_class chip = cmd_buffer->device->physical_device->rad_info.chip_class; + enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level; struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; uint64_t prolog_va = radv_buffer_get_va(prolog->bo) + prolog->alloc->offset; @@ -3369,7 +3370,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_ struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; struct radv_shader *vs_shader = radv_get_shader(pipeline, MESA_SHADER_VERTEX); - enum chip_class chip = cmd_buffer->device->physical_device->rad_info.chip_class; + enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level; unsigned vb_offset; void *vb_ptr; unsigned desc_index = 0; @@ -3598,7 +3599,7 @@ radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer) S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) { rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -3779,10 +3780,10 @@ si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dr draw_vertex_count, topology, prim_restart_enable); if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) { - if (info->chip_class == GFX9) { + if (info->gfx_level == GFX9) { radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param); - } else if (info->chip_class >= GFX7) { + } else if (info->gfx_level >= GFX7) { radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param); } else { radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param); @@ -3801,7 +3802,7 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, const struct radv_d bool disable_instance_packing = false; /* Draw state. */ - if (info->chip_class < GFX10) { + if (info->gfx_level < GFX10) { si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1, draw_info->indirect, !!draw_info->strmout_buffer, draw_info->indirect ? 0 : draw_info->count); @@ -3838,21 +3839,20 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, const struct radv_d * topologies and instance_count > 1, pipeline stats generated by GE are incorrect. It needs to * be applied for indexed and non-indexed draws. */ - if (info->chip_class == GFX10_3 && state->active_pipeline_queries > 0 && + if (info->gfx_level == GFX10_3 && state->active_pipeline_queries > 0 && (draw_info->instance_count > 1 || draw_info->indirect) && - (topology == V_008958_DI_PT_LINELIST_ADJ || - topology == V_008958_DI_PT_LINESTRIP_ADJ || - topology == V_008958_DI_PT_TRILIST_ADJ || - topology == V_008958_DI_PT_TRISTRIP_ADJ)) { + (topology == V_008958_DI_PT_LINELIST_ADJ || topology == V_008958_DI_PT_LINESTRIP_ADJ || + topology == V_008958_DI_PT_TRILIST_ADJ || topology == V_008958_DI_PT_TRISTRIP_ADJ)) { disable_instance_packing = true; } if ((draw_info->indexed && state->index_type != state->last_index_type) || - (info->chip_class == GFX10_3 && (state->last_index_type == -1 || + (info->gfx_level == GFX10_3 && + (state->last_index_type == -1 || disable_instance_packing != G_028A7C_DISABLE_INSTANCE_PACKING(state->last_index_type)))) { uint32_t index_type = state->index_type | S_028A7C_DISABLE_INSTANCE_PACKING(disable_instance_packing); - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cs, R_03090C_VGT_INDEX_TYPE, 2, index_type); } else { @@ -3905,8 +3905,8 @@ radv_stage_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 src_s static bool can_skip_buffer_l2_flushes(struct radv_device *device) { - return device->physical_device->rad_info.chip_class == GFX9 || - (device->physical_device->rad_info.chip_class >= GFX10 && + return device->physical_device->rad_info.gfx_level == GFX9 || + (device->physical_device->rad_info.gfx_level >= GFX10 && !device->physical_device->rad_info.tcc_rb_non_coherent); } @@ -4085,7 +4085,7 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2 dst_fla break; case VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR: flush_bits |= RADV_CMD_FLAG_INV_VCACHE; - if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9) + if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX9) flush_bits |= RADV_CMD_FLAG_INV_L2; break; case VK_ACCESS_2_SHADER_WRITE_BIT: @@ -4713,7 +4713,7 @@ radv_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer, uint32_t firstBinding, assert(firstBinding + bindingCount <= MAX_VBS); cmd_buffer->state.vbo_misaligned_mask = state->misaligned_mask; - enum chip_class chip = cmd_buffer->device->physical_device->rad_info.chip_class; + enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level; if (firstBinding + bindingCount > cmd_buffer->used_vertex_bindings) cmd_buffer->used_vertex_bindings = firstBinding + bindingCount; @@ -4885,7 +4885,7 @@ radv_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pi dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) { dst[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -5044,7 +5044,7 @@ radv_EndCommandBuffer(VkCommandBuffer commandBuffer) radv_emit_mip_change_flush_default(cmd_buffer); if (cmd_buffer->qf != RADV_QUEUE_TRANSFER) { - if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6) + if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX6) cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2; @@ -5631,7 +5631,7 @@ radv_CmdSetVertexInputEXT(VkCommandBuffer commandBuffer, uint32_t vertexBindingD memset(state, 0, sizeof(*state)); - enum chip_class chip = cmd_buffer->device->physical_device->rad_info.chip_class; + enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level; for (unsigned i = 0; i < vertexAttributeDescriptionCount; i++) { const VkVertexInputAttributeDescription2EXT *attrib = &pVertexAttributeDescriptions[i]; const VkVertexInputBindingDescription2EXT *binding = bindings[attrib->binding]; @@ -5712,7 +5712,7 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]); bool allow_ib2 = true; - if (secondary->device->physical_device->rad_info.chip_class == GFX7 && + if (secondary->device->physical_device->rad_info.gfx_level == GFX7 && secondary->state.uses_draw_indirect_multi) { /* Do not launch an IB2 for secondary command buffers that contain * DRAW_{INDEX}_INDIRECT_MULTI on GFX7 because it's illegal and hang the GPU. @@ -6270,7 +6270,8 @@ radv_emit_draw_packets_indexed(struct radv_cmd_buffer *cmd_buffer, const int index_size = radv_get_vgt_index_size(state->index_type); unsigned i = 0; const bool uses_drawid = state->pipeline->graphics.uses_drawid; - const bool can_eop = !uses_drawid && cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10; + const bool can_eop = + !uses_drawid && cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10; if (uses_drawid) { if (vertexOffset) { @@ -6333,7 +6334,7 @@ radv_emit_draw_packets_indexed(struct radv_cmd_buffer *cmd_buffer, } } else { if (vertexOffset) { - if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX10) { /* GFX10 has a bug that consecutive draw packets with NOT_EOP must not have * count == 0 for the last draw that doesn't have NOT_EOP. */ @@ -6756,7 +6757,7 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r * so the state must be re-emitted before the next indexed * draw. */ - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) { cmd_buffer->state.last_index_type = -1; cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER; } @@ -6791,7 +6792,7 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r ALWAYS_INLINE static bool radv_before_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info, uint32_t drawCount) { - const bool has_prefetch = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7; + const bool has_prefetch = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7; const bool pipeline_is_dirty = (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) && cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline; @@ -6871,7 +6872,7 @@ static void radv_after_draw(struct radv_cmd_buffer *cmd_buffer) { const struct radeon_info *rad_info = &cmd_buffer->device->physical_device->rad_info; - bool has_prefetch = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7; + bool has_prefetch = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7; /* Start prefetches after the draw has been started. Both will * run in parallel, but starting the draw first is more * important. @@ -7311,7 +7312,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, struct radv_pipel ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25); if (compute_shader->info.wave_size == 32) { - assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10); + assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10); dispatch_initiator |= S_00B800_CS_W32_EN(1); } @@ -7332,7 +7333,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, struct radv_pipel unsigned reg = R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4; if (cmd_buffer->device->load_grid_size_from_user_sgpr) { - assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3); + assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10_3); radeon_emit(cs, PKT3(PKT3_LOAD_SH_REG_INDEX, 3, 0)); radeon_emit(cs, info->va); radeon_emit(cs, info->va >> 32); @@ -7452,7 +7453,7 @@ static void radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info, struct radv_pipeline *pipeline, VkPipelineBindPoint bind_point) { - bool has_prefetch = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7; + bool has_prefetch = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7; bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline; if (pipeline->compute.cs_regalloc_hang_bug) @@ -8194,7 +8195,7 @@ radv_init_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value); - if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX8) { /* When DCC is enabled with mipmaps, some levels might not * support fast clears and we have to initialize them as "fully * expanded". @@ -8243,7 +8244,7 @@ radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i if (radv_image_has_cmask(image)) { uint32_t value; - if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) { /* TODO: Fix clearing CMASK layers on GFX9. */ if (radv_image_is_tc_compat_cmask(image) || (radv_image_has_fmask(image) && @@ -8622,7 +8623,7 @@ write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *event, event_type = V_028A90_BOTTOM_OF_PIPE_TS; } - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class, + si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, radv_cmd_buffer_uses_mec(cmd_buffer), event_type, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, va, value, cmd_buffer->gfx9_eop_bug_va); @@ -8869,14 +8870,14 @@ radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer) unsigned reg_strmout_cntl; /* The register is at different places on different ASICs. */ - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL; radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); radeon_emit(cs, S_370_DST_SEL(V_370_MEM_MAPPED_REGISTER) | S_370_ENGINE_SEL(V_370_ME)); radeon_emit(cs, R_0300FC_CP_STRMOUT_CNTL >> 2); radeon_emit(cs, 0); radeon_emit(cs, 0); - } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) { + } else if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) { reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL; radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0); } else { @@ -8973,7 +8974,7 @@ gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCou unsigned last_target = util_last_bit(so->enabled_mask) - 1; struct radeon_cmdbuf *cs = cmd_buffer->cs; - assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10); + assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10); assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS); /* Sync because the next streamout operation will overwrite GDS and we @@ -9097,7 +9098,7 @@ gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCount struct radv_streamout_state *so = &cmd_buffer->state.streamout; struct radeon_cmdbuf *cs = cmd_buffer->cs; - assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10); + assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10); assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS); u_foreach_bit(i, so->enabled_mask) @@ -9117,7 +9118,7 @@ gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCount va += buffer->offset + counter_buffer_offset; - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class, + si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, radv_cmd_buffer_uses_mec(cmd_buffer), V_028A90_PS_DONE, 0, EOP_DST_SEL_TC_L2, EOP_DATA_SEL_GDS, va, EOP_DATA_GDS(i, 1), 0); @@ -9193,7 +9194,7 @@ radv_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, VkPipelineStageFlag radeon_emit(cs, va); radeon_emit(cs, va >> 32); } else { - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class, + si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, radv_cmd_buffer_uses_mec(cmd_buffer), V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, va, marker, cmd_buffer->gfx9_eop_bug_va); diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index 3a027eb9648..7ecb13cbdae 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -120,7 +120,7 @@ radeon_set_sh_reg_idx(const struct radv_physical_device *pdevice, struct radeon_ assert(idx); unsigned opcode = PKT3_SET_SH_REG_INDEX; - if (pdevice->rad_info.chip_class < GFX10) + if (pdevice->rad_info.gfx_level < GFX10) opcode = PKT3_SET_SH_REG; radeon_emit(cs, PKT3(opcode, 1, 0)); @@ -175,8 +175,8 @@ radeon_set_uconfig_reg_idx(const struct radv_physical_device *pdevice, struct ra assert(idx); unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX; - if (pdevice->rad_info.chip_class < GFX9 || - (pdevice->rad_info.chip_class == GFX9 && pdevice->rad_info.me_fw_version < 26)) + if (pdevice->rad_info.gfx_level < GFX9 || + (pdevice->rad_info.gfx_level == GFX9 && pdevice->rad_info.me_fw_version < 26)) opcode = PKT3_SET_UCONFIG_REG; radeon_emit(cs, PKT3(opcode, 1, 0)); diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c index 3fb66749671..20505b5e185 100644 --- a/src/amd/vulkan/radv_debug.c +++ b/src/amd/vulkan/radv_debug.c @@ -83,8 +83,7 @@ radv_init_trace(struct radv_device *device) if (!device->trace_id_ptr) return false; - ac_vm_fault_occured(device->physical_device->rad_info.chip_class, &device->dmesg_timestamp, - NULL); + ac_vm_fault_occured(device->physical_device->rad_info.gfx_level, &device->dmesg_timestamp, NULL); return true; } @@ -114,7 +113,7 @@ radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset) uint32_t value; if (ws->read_registers(ws, offset, 1, &value)) - ac_dump_reg(f, device->physical_device->rad_info.chip_class, offset, value, ~0); + ac_dump_reg(f, device->physical_device->rad_info.gfx_level, offset, value, ~0); } static void @@ -132,7 +131,7 @@ radv_dump_debug_registers(struct radv_device *device, FILE *f) radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3); radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG); radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG); - if (info->chip_class <= GFX8) { + if (info->gfx_level <= GFX8) { radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS); radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2); radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3); @@ -151,50 +150,50 @@ radv_dump_debug_registers(struct radv_device *device, FILE *f) } static void -radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc, FILE *f) +radv_dump_buffer_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f) { fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n"); for (unsigned j = 0; j < 4; j++) - ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, desc[j], 0xffffffff); + ac_dump_reg(f, gfx_level, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, desc[j], 0xffffffff); } static void -radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc, FILE *f) +radv_dump_image_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f) { unsigned sq_img_rsrc_word0 = - chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0 : R_008F10_SQ_IMG_RSRC_WORD0; + gfx_level >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0 : R_008F10_SQ_IMG_RSRC_WORD0; fprintf(f, COLOR_CYAN " Image:" COLOR_RESET "\n"); for (unsigned j = 0; j < 8; j++) - ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4, desc[j], 0xffffffff); + ac_dump_reg(f, gfx_level, sq_img_rsrc_word0 + j * 4, desc[j], 0xffffffff); fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n"); for (unsigned j = 0; j < 8; j++) - ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4, desc[8 + j], 0xffffffff); + ac_dump_reg(f, gfx_level, sq_img_rsrc_word0 + j * 4, desc[8 + j], 0xffffffff); } static void -radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc, FILE *f) +radv_dump_sampler_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f) { fprintf(f, COLOR_CYAN " Sampler state:" COLOR_RESET "\n"); for (unsigned j = 0; j < 4; j++) { - ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4, desc[j], 0xffffffff); + ac_dump_reg(f, gfx_level, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4, desc[j], 0xffffffff); } } static void -radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc, +radv_dump_combined_image_sampler_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f) { - radv_dump_image_descriptor(chip_class, desc, f); - radv_dump_sampler_descriptor(chip_class, desc + 16, f); + radv_dump_image_descriptor(gfx_level, desc, f); + radv_dump_sampler_descriptor(gfx_level, desc + 16, f); } static void radv_dump_descriptor_set(struct radv_device *device, struct radv_descriptor_set *set, unsigned id, FILE *f) { - enum chip_class chip_class = device->physical_device->rad_info.chip_class; + enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; const struct radv_descriptor_set_layout *layout; int i; @@ -210,18 +209,18 @@ radv_dump_descriptor_set(struct radv_device *device, struct radv_descriptor_set case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER: case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER: - radv_dump_buffer_descriptor(chip_class, desc, f); + radv_dump_buffer_descriptor(gfx_level, desc, f); break; case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE: case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT: - radv_dump_image_descriptor(chip_class, desc, f); + radv_dump_image_descriptor(gfx_level, desc, f); break; case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: - radv_dump_combined_image_sampler_descriptor(chip_class, desc, f); + radv_dump_combined_image_sampler_descriptor(gfx_level, desc, f); break; case VK_DESCRIPTOR_TYPE_SAMPLER: - radv_dump_sampler_descriptor(chip_class, desc, f); + radv_dump_sampler_descriptor(gfx_level, desc, f); break; case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: @@ -369,8 +368,8 @@ radv_dump_annotated_shaders(struct radv_pipeline *pipeline, VkShaderStageFlagBit FILE *f) { struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP]; - enum chip_class chip_class = pipeline->device->physical_device->rad_info.chip_class; - unsigned num_waves = ac_get_wave_info(chip_class, waves); + enum amd_gfx_level gfx_level = pipeline->device->physical_device->rad_info.gfx_level; + unsigned num_waves = ac_get_wave_info(gfx_level, waves); fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET "\n\n", num_waves); @@ -640,7 +639,7 @@ radv_dump_umr_ring(struct radv_queue *queue, FILE *f) return; sprintf(cmd, "umr -R %s 2>&1", - device->physical_device->rad_info.chip_class >= GFX10 ? "gfx_0.0.0" : "gfx"); + device->physical_device->rad_info.gfx_level >= GFX10 ? "gfx_0.0.0" : "gfx"); fprintf(f, "\nUMR GFX ring:\n\n"); radv_dump_cmd(cmd, f); @@ -658,7 +657,7 @@ radv_dump_umr_waves(struct radv_queue *queue, FILE *f) return; sprintf(cmd, "umr -O bits,halt_waves -wa %s 2>&1", - device->physical_device->rad_info.chip_class >= GFX10 ? "gfx_0.0.0" : "gfx"); + device->physical_device->rad_info.gfx_level >= GFX10 ? "gfx_0.0.0" : "gfx"); fprintf(f, "\nUMR GFX waves:\n\n"); radv_dump_cmd(cmd, f); @@ -687,7 +686,7 @@ radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs) bool hang_occurred = radv_gpu_hang_occured(queue, ring); bool vm_fault_occurred = false; if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS) - vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class, + vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.gfx_level, &device->dmesg_timestamp, &addr); if (!hang_occurred && !vm_fault_occurred) return; @@ -964,23 +963,23 @@ radv_dump_sq_hw_regs(struct radv_device *device) struct radv_sq_hw_reg *regs = (struct radv_sq_hw_reg *)&device->tma_ptr[6]; fprintf(stderr, "\nHardware registers:\n"); - if (device->physical_device->rad_info.chip_class >= GFX10) { - ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_000408_SQ_WAVE_STATUS, + if (device->physical_device->rad_info.gfx_level >= GFX10) { + ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_000408_SQ_WAVE_STATUS, regs->status, ~0); - ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_00040C_SQ_WAVE_TRAPSTS, + ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_00040C_SQ_WAVE_TRAPSTS, regs->trap_sts, ~0); - ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_00045C_SQ_WAVE_HW_ID1, + ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_00045C_SQ_WAVE_HW_ID1, regs->hw_id, ~0); - ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_00041C_SQ_WAVE_IB_STS, + ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_00041C_SQ_WAVE_IB_STS, regs->ib_sts, ~0); } else { - ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_000048_SQ_WAVE_STATUS, + ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_000048_SQ_WAVE_STATUS, regs->status, ~0); - ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_00004C_SQ_WAVE_TRAPSTS, + ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_00004C_SQ_WAVE_TRAPSTS, regs->trap_sts, ~0); - ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_000050_SQ_WAVE_HW_ID, + ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_000050_SQ_WAVE_HW_ID, regs->hw_id, ~0); - ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_00005C_SQ_WAVE_IB_STS, + ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_00005C_SQ_WAVE_IB_STS, regs->ib_sts, ~0); } fprintf(stderr, "\n\n"); diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index 6c167d81797..4636043973a 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++ b/src/amd/vulkan/radv_descriptor_set.c @@ -1080,7 +1080,7 @@ write_buffer_descriptor(struct radv_device *device, struct radv_cmd_buffer *cmd_ S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { rsrc_word3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 4f0f8e14533..6fdb53fb090 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -420,7 +420,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device .KHR_external_semaphore = true, .KHR_external_semaphore_fd = true, .KHR_format_feature_flags2 = true, - .KHR_fragment_shading_rate = device->rad_info.chip_class >= GFX10_3, + .KHR_fragment_shading_rate = device->rad_info.gfx_level >= GFX10_3, .KHR_get_memory_requirements2 = true, .KHR_image_format_list = true, .KHR_imageless_framebuffer = true, @@ -469,7 +469,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device .EXT_calibrated_timestamps = RADV_SUPPORT_CALIBRATED_TIMESTAMPS, .EXT_color_write_enable = true, .EXT_conditional_rendering = true, - .EXT_conservative_rasterization = device->rad_info.chip_class >= GFX9, + .EXT_conservative_rasterization = device->rad_info.gfx_level >= GFX9, .EXT_custom_border_color = true, .EXT_debug_marker = radv_thread_trace_enabled(), .EXT_depth_clip_control = true, @@ -488,10 +488,10 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device .EXT_global_priority_query = true, .EXT_host_query_reset = true, .EXT_image_2d_view_of_3d = true, - .EXT_image_drm_format_modifier = device->rad_info.chip_class >= GFX9, + .EXT_image_drm_format_modifier = device->rad_info.gfx_level >= GFX9, .EXT_image_robustness = true, .EXT_image_view_min_lod = true, - .EXT_index_type_uint8 = device->rad_info.chip_class >= GFX8, + .EXT_index_type_uint8 = device->rad_info.gfx_level >= GFX8, .EXT_inline_uniform_block = true, .EXT_line_rasterization = true, .EXT_memory_budget = true, @@ -503,15 +503,15 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device #endif .EXT_pipeline_creation_cache_control = true, .EXT_pipeline_creation_feedback = true, - .EXT_post_depth_coverage = device->rad_info.chip_class >= GFX10, + .EXT_post_depth_coverage = device->rad_info.gfx_level >= GFX10, .EXT_primitive_topology_list_restart = true, .EXT_private_data = true, .EXT_provoking_vertex = true, .EXT_queue_family_foreign = true, .EXT_robustness2 = true, - .EXT_sample_locations = device->rad_info.chip_class < GFX10, + .EXT_sample_locations = device->rad_info.gfx_level < GFX10, .EXT_sampler_filter_minmax = true, - .EXT_scalar_block_layout = device->rad_info.chip_class >= GFX7, + .EXT_scalar_block_layout = device->rad_info.gfx_level >= GFX7, .EXT_separate_stencil_usage = true, .EXT_shader_atomic_float = true, #ifdef LLVM_AVAILABLE @@ -556,7 +556,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device .GOOGLE_hlsl_functionality1 = true, .GOOGLE_user_type = true, .NV_compute_shader_derivatives = true, - .NV_mesh_shader = device->use_ngg && device->rad_info.chip_class >= GFX10_3 && + .NV_mesh_shader = device->use_ngg && device->rad_info.gfx_level >= GFX10_3 && device->instance->perftest_flags & RADV_PERFTEST_NV_MS && !device->use_llvm, /* Undocumented extension purely for vkd3d-proton. This check is to prevent anyone else from * using it. @@ -571,7 +571,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device static bool radv_is_conformant(const struct radv_physical_device *pdevice) { - return pdevice->rad_info.chip_class >= GFX8; + return pdevice->rad_info.gfx_level >= GFX8; } static void @@ -743,16 +743,14 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm device->dcc_msaa_allowed = (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA); - device->use_ngg = device->rad_info.chip_class >= GFX10 && + device->use_ngg = device->rad_info.gfx_level >= GFX10 && device->rad_info.family != CHIP_NAVI14 && !(device->instance->debug_flags & RADV_DEBUG_NO_NGG); - device->use_ngg_culling = - device->use_ngg && - device->rad_info.max_render_backends > 1 && - (device->rad_info.chip_class >= GFX10_3 || - (device->instance->perftest_flags & RADV_PERFTEST_NGGC)) && - !(device->instance->debug_flags & RADV_DEBUG_NO_NGGC); + device->use_ngg_culling = device->use_ngg && device->rad_info.max_render_backends > 1 && + (device->rad_info.gfx_level >= GFX10_3 || + (device->instance->perftest_flags & RADV_PERFTEST_NGGC)) && + !(device->instance->debug_flags & RADV_DEBUG_NO_NGGC); device->use_ngg_streamout = false; @@ -762,7 +760,7 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm device->ge_wave_size = 64; device->rt_wave_size = 64; - if (device->rad_info.chip_class >= GFX10) { + if (device->rad_info.gfx_level >= GFX10) { if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32) device->cs_wave_size = 32; @@ -1314,7 +1312,7 @@ radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice, f->runtimeDescriptorArray = true; f->samplerFilterMinmax = true; - f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7; + f->scalarBlockLayout = pdevice->rad_info.gfx_level >= GFX7; f->imagelessFramebuffer = true; f->uniformBufferStandardLayout = true; f->shaderSubgroupExtendedTypes = true; @@ -1451,7 +1449,7 @@ radv_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice, case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: { VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features = (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext; - features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8; + features->indexTypeUint8 = pdevice->rad_info.gfx_level >= GFX8; break; } case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: { @@ -1464,7 +1462,7 @@ radv_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice, VkPhysicalDeviceShaderClockFeaturesKHR *features = (VkPhysicalDeviceShaderClockFeaturesKHR *)ext; features->shaderSubgroupClock = true; - features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8; + features->shaderDeviceClock = pdevice->rad_info.gfx_level >= GFX8; break; } case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: { @@ -1489,7 +1487,7 @@ radv_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice, /* FIXME: Some stippled Bresenham CTS fails on Vega10 * but work on Raven. */ - features->stippledBresenhamLines = pdevice->rad_info.chip_class != GFX9; + features->stippledBresenhamLines = pdevice->rad_info.gfx_level != GFX9; features->stippledSmoothLines = false; break; } @@ -1528,7 +1526,7 @@ radv_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice, features->shaderBufferFloat64Atomics = true; features->shaderBufferFloat64AtomicAdd = false; features->shaderSharedFloat32Atomics = true; - features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8; + features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.gfx_level >= GFX8; features->shaderSharedFloat64Atomics = true; features->shaderSharedFloat64AtomicAdd = false; features->shaderImageFloat32Atomics = true; @@ -1626,8 +1624,8 @@ radv_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice, VkPhysicalDeviceShaderAtomicFloat2FeaturesEXT *features = (VkPhysicalDeviceShaderAtomicFloat2FeaturesEXT *)ext; bool has_shader_buffer_float_minmax = radv_has_shader_buffer_float_minmax(pdevice); - bool has_shader_image_float_minmax = pdevice->rad_info.chip_class != GFX8 && - pdevice->rad_info.chip_class != GFX9; + bool has_shader_image_float_minmax = + pdevice->rad_info.gfx_level != GFX8 && pdevice->rad_info.gfx_level != GFX9; features->shaderBufferFloat16Atomics = false; features->shaderBufferFloat16AtomicAdd = false; features->shaderBufferFloat16AtomicMinMax = false; @@ -1828,7 +1826,7 @@ radv_GetPhysicalDeviceProperties(VkPhysicalDevice physicalDevice, .maxFragmentOutputAttachments = 8, .maxFragmentDualSrcAttachments = 1, .maxFragmentCombinedOutputResources = max_descriptor_set_size, - .maxComputeSharedMemorySize = pdevice->rad_info.chip_class >= GFX7 ? 65536 : 32768, + .maxComputeSharedMemorySize = pdevice->rad_info.gfx_level >= GFX7 ? 65536 : 32768, .maxComputeWorkGroupCount = {65535, 65535, 65535}, .maxComputeWorkGroupInvocations = 1024, .maxComputeWorkGroupSize = {1024, 1024, 1024}, @@ -1953,7 +1951,7 @@ radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice, radv_get_compiler_string(pdevice)); if (radv_is_conformant(pdevice)) { - if (pdevice->rad_info.chip_class >= GFX10_3) { + if (pdevice->rad_info.gfx_level >= GFX10_3) { p->conformanceVersion = (VkConformanceVersion){ .major = 1, .minor = 3, @@ -2008,11 +2006,11 @@ radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice, p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm; p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit; - p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm; - p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8; - p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8; - p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm; - p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8; + p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.gfx_level >= GFX8 && !pdevice->use_llvm; + p->shaderDenormPreserveFloat64 = pdevice->rad_info.gfx_level >= GFX8; + p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.gfx_level >= GFX8; + p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.gfx_level >= GFX8 && !pdevice->use_llvm; + p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.gfx_level >= GFX8; p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64; p->shaderUniformBufferArrayNonUniformIndexingNative = false; @@ -2059,7 +2057,7 @@ radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice, p->independentResolve = true; /* GFX6-8 only support single channel min/max filter. */ - p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9; + p->filterMinmaxImageComponentMapping = pdevice->rad_info.gfx_level >= GFX9; p->filterMinmaxSingleComponentFormats = true; p->maxTimelineSemaphoreValueDifference = UINT64_MAX; @@ -2077,7 +2075,7 @@ radv_get_physical_device_properties_1_3(struct radv_physical_device *pdevice, p->maxSubgroupSize = 64; p->maxComputeWorkgroupSubgroups = UINT32_MAX; p->requiredSubgroupSizeStages = 0; - if (pdevice->rad_info.chip_class >= GFX10) { + if (pdevice->rad_info.gfx_level >= GFX10) { /* Only GFX10+ supports wave32. */ p->minSubgroupSize = 32; p->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT; @@ -2739,7 +2737,7 @@ radv_queue_finish(struct radv_queue *queue) static void radv_device_init_gs_info(struct radv_device *device) { - device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class, + device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.gfx_level, device->physical_device->rad_info.family); } @@ -3315,7 +3313,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr } device->private_sdma_queue = VK_NULL_HANDLE; - device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 && + device->pbb_allowed = device->physical_device->rad_info.gfx_level >= GFX9 && !(device->instance->debug_flags & RADV_DEBUG_NOBINNING); /* The maximum number of scratch waves. Scratch space isn't divided @@ -3336,7 +3334,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1); - if (device->physical_device->rad_info.chip_class >= GFX7) { + if (device->physical_device->rad_info.gfx_level >= GFX7) { /* If the KMD allows it (there is a KMD hw register for it), * allow launching waves out-of-order. */ @@ -3391,8 +3389,8 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr } if (radv_thread_trace_enabled()) { - if (device->physical_device->rad_info.chip_class < GFX8 || - device->physical_device->rad_info.chip_class > GFX10_3) { + if (device->physical_device->rad_info.gfx_level < GFX8 || + device->physical_device->rad_info.gfx_level > GFX10_3) { fprintf(stderr, "GPU hardware not supported: refer to " "the RGP documentation for the list of " "supported GPUs!\n"); @@ -3409,7 +3407,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr radv_spm_trace_enabled() ? "enabled" : "disabled"); if (radv_spm_trace_enabled()) { - if (device->physical_device->rad_info.chip_class < GFX10) { + if (device->physical_device->rad_info.gfx_level < GFX10) { fprintf(stderr, "SPM isn't supported for this GPU!\n"); abort(); } @@ -3421,7 +3419,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr if (getenv("RADV_TRAP_HANDLER")) { /* TODO: Add support for more hardware. */ - assert(device->physical_device->rad_info.chip_class == GFX8); + assert(device->physical_device->rad_info.gfx_level == GFX8); fprintf(stderr, "**********************************************************************\n"); fprintf(stderr, "* WARNING: RADV_TRAP_HANDLER is experimental and only for debugging! *\n"); @@ -3436,7 +3434,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr goto fail; } - if (device->physical_device->rad_info.chip_class >= GFX10_3) { + if (device->physical_device->rad_info.gfx_level >= GFX10_3) { if (getenv("RADV_FORCE_VRS_CONFIG_FILE")) { const char *file = radv_get_force_vrs_config_file(); @@ -3456,7 +3454,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr } /* PKT3_LOAD_SH_REG_INDEX is supported on GFX8+, but it hangs with compute queues until GFX10.3. */ - device->load_grid_size_from_user_sgpr = device->physical_device->rad_info.chip_class >= GFX10_3; + device->load_grid_size_from_user_sgpr = device->physical_device->rad_info.gfx_level >= GFX10_3; device->keep_shader_info = keep_shader_info; result = radv_device_init_meta(device); @@ -3478,7 +3476,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr goto fail; } - if (device->physical_device->rad_info.chip_class >= GFX7) + if (device->physical_device->rad_info.gfx_level >= GFX7) cik_create_gfx_config(device); VkPipelineCacheCreateInfo ci; @@ -3638,7 +3636,7 @@ radv_fill_shader_rings(struct radv_queue *queue, uint32_t *map, bool add_sample_ S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | S_008F0C_INDEX_STRIDE(3) | S_008F0C_ADD_TID_ENABLE(1); - if (queue->device->physical_device->rad_info.chip_class >= GFX10) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX10) { desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -3655,7 +3653,7 @@ radv_fill_shader_rings(struct radv_queue *queue, uint32_t *map, bool add_sample_ desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (queue->device->physical_device->rad_info.chip_class >= GFX10) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX10) { desc[7] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -3678,7 +3676,7 @@ radv_fill_shader_rings(struct radv_queue *queue, uint32_t *map, bool add_sample_ desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (queue->device->physical_device->rad_info.chip_class >= GFX10) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX10) { desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -3696,7 +3694,7 @@ radv_fill_shader_rings(struct radv_queue *queue, uint32_t *map, bool add_sample_ S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | S_008F0C_INDEX_STRIDE(1) | S_008F0C_ADD_TID_ENABLE(true); - if (queue->device->physical_device->rad_info.chip_class >= GFX10) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX10) { desc[7] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -3717,7 +3715,7 @@ radv_fill_shader_rings(struct radv_queue *queue, uint32_t *map, bool add_sample_ desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (queue->device->physical_device->rad_info.chip_class >= GFX10) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX10) { desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -3731,7 +3729,7 @@ radv_fill_shader_rings(struct radv_queue *queue, uint32_t *map, bool add_sample_ desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (queue->device->physical_device->rad_info.chip_class >= GFX10) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX10) { desc[7] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -3772,7 +3770,7 @@ radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs, if (gsvs_ring_bo) radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo); - if (queue->device->physical_device->rad_info.chip_class >= GFX7) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX7) { radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2); radeon_emit(cs, esgs_ring_size >> 8); radeon_emit(cs, gsvs_ring_size >> 8); @@ -3797,14 +3795,14 @@ radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs, radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo); - if (queue->device->physical_device->rad_info.chip_class >= GFX7) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX7) { radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE, S_030938_SIZE(tf_ring_size)); radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, tf_va >> 8); - if (queue->device->physical_device->rad_info.chip_class >= GFX10) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX10) { radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI, S_030984_BASE_HI(tf_va >> 40)); - } else if (queue->device->physical_device->rad_info.chip_class == GFX9) { + } else if (queue->device->physical_device->rad_info.gfx_level == GFX9) { radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI, S_030944_BASE_HI(tf_va >> 40)); } radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, queue->device->hs.hs_offchip_param); @@ -3868,7 +3866,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue, struct radeon_cmdbuf radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo); - if (queue->device->physical_device->rad_info.chip_class >= GFX10) { + if (queue->device->physical_device->rad_info.gfx_level >= GFX10) { uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0, R_00B130_SPI_SHADER_USER_DATA_VS_0, R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS, R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS}; @@ -3876,7 +3874,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue, struct radeon_cmdbuf for (int i = 0; i < ARRAY_SIZE(regs); ++i) { radv_emit_shader_pointer(queue->device, cs, regs[i], va, true); } - } else if (queue->device->physical_device->rad_info.chip_class == GFX9) { + } else if (queue->device->physical_device->rad_info.gfx_level == GFX9) { uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0, R_00B130_SPI_SHADER_USER_DATA_VS_0, R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS, R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS}; @@ -4016,7 +4014,7 @@ radv_update_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave } if (add_gds) { - assert(queue->device->physical_device->rad_info.chip_class >= GFX10); + assert(queue->device->physical_device->rad_info.gfx_level >= GFX10); /* 4 streamout GDS counters. * We need 256B (64 dw) of GDS, otherwise streamout hangs. @@ -4029,7 +4027,7 @@ radv_update_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave } if (add_gds_oa) { - assert(queue->device->physical_device->rad_info.chip_class >= GFX10); + assert(queue->device->physical_device->rad_info.gfx_level >= GFX10); result = queue->device->ws->buffer_create(queue->device->ws, 4, 1, RADEON_DOMAIN_OA, ring_bo_flags, @@ -4082,7 +4080,7 @@ radv_update_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave if (i == 2) { /* We only need the continue preamble when we can't use indirect buffers. */ if (!(queue->device->instance->debug_flags & RADV_DEBUG_NO_IBS) && - queue->device->physical_device->rad_info.chip_class >= GFX7) + queue->device->physical_device->rad_info.gfx_level >= GFX7) continue; /* Continue preamble is unnecessary when no shader rings are used. */ if (!scratch_size_per_wave && !compute_scratch_size_per_wave && !esgs_ring_size && @@ -4143,8 +4141,8 @@ radv_update_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave if (i < 2) { /* The two initial preambles have a cache flush at the beginning. */ - const enum chip_class chip_class = queue->device->physical_device->rad_info.chip_class; - const bool is_mec = queue->qf == RADV_QUEUE_COMPUTE && chip_class >= GFX7; + const enum amd_gfx_level gfx_level = queue->device->physical_device->rad_info.gfx_level; + const bool is_mec = queue->qf == RADV_QUEUE_COMPUTE && gfx_level >= GFX7; enum radv_cmd_flush_bits flush_bits = RADV_CMD_FLAG_INV_ICACHE | RADV_CMD_FLAG_INV_SCACHE | RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_START_PIPELINE_STATS; @@ -4156,7 +4154,7 @@ radv_update_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH; } - si_cs_emit_cache_flush(cs, chip_class, NULL, 0, is_mec, flush_bits, &sqtt_flush_bits, 0); + si_cs_emit_cache_flush(cs, gfx_level, NULL, 0, is_mec, flush_bits, &sqtt_flush_bits, 0); } result = queue->device->ws->cs_finalize(cs); @@ -4330,7 +4328,7 @@ radv_sparse_image_bind_memory(struct radv_device *device, const VkSparseImageMem if (bind->pBinds[i].memory != VK_NULL_HANDLE) mem = radv_device_memory_from_handle(bind->pBinds[i].memory); - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { offset = surface->u.gfx9.surf_slice_size * layer + surface->u.gfx9.prt_level_offset[level]; pitch = surface->u.gfx9.prt_level_pitch[level]; } else { @@ -5421,7 +5419,7 @@ static unsigned get_dcc_max_uncompressed_block_size(const struct radv_device *device, const struct radv_image_view *iview) { - if (device->physical_device->rad_info.chip_class < GFX10 && iview->image->info.samples > 1) { + if (device->physical_device->rad_info.gfx_level < GFX10 && iview->image->info.samples > 1) { if (iview->image->planes[0].surface.bpe == 1) return V_028C78_MAX_BLOCK_SIZE_64B; else if (iview->image->planes[0].surface.bpe == 2) @@ -5460,7 +5458,7 @@ radv_init_dcc_control_reg(struct radv_device *device, struct radv_image_view *iv /* For GFX9+ ac_surface computes values for us (except min_compressed * and max_uncompressed) */ - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { max_compressed_block_size = iview->image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size; independent_128b_blocks = iview->image->planes[0].surface.u.gfx9.color.dcc.independent_128B_blocks; @@ -5514,8 +5512,8 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff cb->cb_color_base = va >> 8; - if (device->physical_device->rad_info.chip_class >= GFX9) { - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) | S_028EE0_FMASK_SW_MODE(surf->u.gfx9.color.fmask_swizzle_mode) | S_028EE0_CMASK_PIPE_ALIGNED(1) | @@ -5557,14 +5555,14 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index); if (radv_image_has_fmask(iview->image)) { - if (device->physical_device->rad_info.chip_class >= GFX7) + if (device->physical_device->rad_info.gfx_level >= GFX7) cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.color.fmask.pitch_in_pixels / 8 - 1); cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.color.fmask.tiling_index); cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.color.fmask.slice_tile_max); } else { /* This must be set for fast clear to work without FMASK. */ - if (device->physical_device->rad_info.chip_class >= GFX7) + if (device->physical_device->rad_info.gfx_level >= GFX7) cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max); cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index); cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max); @@ -5580,7 +5578,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff va += surf->meta_offset; if (radv_dcc_enabled(iview->image, iview->base_mip) && - device->physical_device->rad_info.chip_class <= GFX8) + device->physical_device->rad_info.gfx_level <= GFX8) va += plane->surface.u.legacy.color.dcc_level[iview->base_mip].dcc_offset; unsigned dcc_tile_swizzle = surf->tile_swizzle; @@ -5646,7 +5644,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff S_028C70_NUMBER_TYPE(ntype) | S_028C70_ENDIAN(endian); if (radv_image_has_fmask(iview->image)) { cb->cb_color_info |= S_028C70_COMPRESSION(1); - if (device->physical_device->rad_info.chip_class == GFX6) { + if (device->physical_device->rad_info.gfx_level == GFX6) { unsigned fmask_bankh = util_logbase2(surf->u.legacy.color.fmask.bankh); cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); } @@ -5659,7 +5657,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff */ cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1); - if (device->physical_device->rad_info.chip_class == GFX8) { + if (device->physical_device->rad_info.gfx_level == GFX8) { /* Set CMASK into a tiling format that allows * the texture block to read it. */ @@ -5678,13 +5676,12 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview); /* This must be set for fast clear to work without FMASK. */ - if (!radv_image_has_fmask(iview->image) && - device->physical_device->rad_info.chip_class == GFX6) { + if (!radv_image_has_fmask(iview->image) && device->physical_device->rad_info.gfx_level == GFX6) { unsigned bankh = util_logbase2(surf->u.legacy.bankh); cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh); } - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ? (iview->extent.depth - 1) : (iview->image->info.array_size - 1); @@ -5693,7 +5690,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff unsigned height = vk_format_get_plane_height(iview->image->vk_format, iview->plane_id, iview->extent.height); - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip); cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) | @@ -5717,7 +5714,7 @@ radv_calc_decompress_on_z_planes(struct radv_device *device, struct radv_image_v assert(radv_image_is_tc_compat_htile(iview->image)); - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { /* Default value for 32-bit depth surfaces. */ max_zplanes = 4; @@ -5819,7 +5816,7 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf uint32_t max_slice = radv_surface_max_layer_count(iview) - 1; ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) | S_028008_SLICE_MAX(max_slice); - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) | S_028008_SLICE_MAX_HI(max_slice >> 11); } @@ -5830,7 +5827,7 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf va = radv_buffer_get_va(iview->image->bo) + iview->image->offset; s_offs = z_offs = va; - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { assert(surf->u.gfx9.surf_offset == 0); s_offs += surf->u.gfx9.zs.stencil_offset; @@ -5841,7 +5838,7 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf ds->db_stencil_info = S_02803C_FORMAT(stencil_format) | S_02803C_SW_MODE(surf->u.gfx9.zs.stencil_swizzle_mode); - if (device->physical_device->rad_info.chip_class == GFX9) { + if (device->physical_device->rad_info.gfx_level == GFX9) { ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.epitch); ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.zs.stencil_epitch); } @@ -5858,7 +5855,7 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes); - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { bool iterate256 = radv_image_get_iterate256(device, iview->image); ds->db_z_info |= S_028040_ITERATE_FLUSH(1); @@ -5879,7 +5876,7 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf ds->db_htile_data_base = va >> 8; ds->db_htile_surface = S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1); - if (device->physical_device->rad_info.chip_class == GFX9) { + if (device->physical_device->rad_info.gfx_level == GFX9) { ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1); } @@ -5903,7 +5900,7 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf if (iview->image->info.samples > 1) ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples)); - if (device->physical_device->rad_info.chip_class >= GFX7) { + if (device->physical_device->rad_info.gfx_level >= GFX7) { struct radeon_info *info = &device->physical_device->rad_info; unsigned tiling_index = surf->u.legacy.tiling_index[level]; unsigned stencil_index = surf->u.legacy.zs.stencil_tiling_index[level]; @@ -6132,8 +6129,8 @@ radv_init_sampler(struct radv_device *device, struct radv_sampler *sampler, { uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo); uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso); - bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 || - device->physical_device->rad_info.chip_class == GFX9; + bool compat_mode = device->physical_device->rad_info.gfx_level == GFX8 || + device->physical_device->rad_info.gfx_level == GFX9; unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND; unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; bool trunc_coord = @@ -6196,15 +6193,15 @@ radv_init_sampler(struct radv_device *device, struct radv_sampler *sampler, sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR_GFX6(border_color_ptr) | S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color))); - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(device->instance->disable_aniso_single_level); } else { sampler->state[2] |= - S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) | + S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.gfx_level <= GFX8) | S_008F38_FILTER_PREC_FIX(1) | S_008F38_ANISO_OVERRIDE_GFX8(device->instance->disable_aniso_single_level && - device->physical_device->rad_info.chip_class >= GFX8); + device->physical_device->rad_info.gfx_level >= GFX8); } } diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c index 6971bb713bf..5daa8f23113 100644 --- a/src/amd/vulkan/radv_formats.c +++ b/src/amd/vulkan/radv_formats.c @@ -158,7 +158,7 @@ radv_translate_vertex_format(const struct radv_physical_device *pdevice, VkForma *dfmt = radv_translate_buffer_dataformat(desc, 0); *alpha_adjust = ALPHA_ADJUST_NONE; - if (pdevice->rad_info.chip_class <= GFX8 && pdevice->rad_info.family != CHIP_STONEY) { + if (pdevice->rad_info.gfx_level <= GFX8 && pdevice->rad_info.family != CHIP_STONEY) { switch (format) { case VK_FORMAT_A2R10G10B10_SNORM_PACK32: case VK_FORMAT_A2B10G10R10_SNORM_PACK32: @@ -599,7 +599,7 @@ radv_is_storage_image_format_supported(struct radv_physical_device *physical_dev /* TODO: FMASK formats. */ return true; case V_008F14_IMG_DATA_FORMAT_5_9_9_9: - return physical_device->rad_info.chip_class >= GFX10_3; + return physical_device->rad_info.gfx_level >= GFX10_3; default: return false; } @@ -640,7 +640,7 @@ radv_is_colorbuffer_format_supported(const struct radv_physical_device *pdevice, } else *blendable = true; - if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32 && pdevice->rad_info.chip_class < GFX10_3) + if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32 && pdevice->rad_info.gfx_level < GFX10_3) return false; return color_format != V_028C70_COLOR_INVALID && color_swap != ~0U && color_num_format != ~0; @@ -1471,7 +1471,7 @@ radv_get_image_format_properties(struct radv_physical_device *physical_device, uint32_t maxArraySize; VkSampleCountFlags sampleCounts = VK_SAMPLE_COUNT_1_BIT; const struct util_format_description *desc = vk_format_description(format); - enum chip_class chip_class = physical_device->rad_info.chip_class; + enum amd_gfx_level gfx_level = physical_device->rad_info.gfx_level; VkImageTiling tiling = info->tiling; const VkPhysicalDeviceImageDrmFormatModifierInfoEXT *mod_info = vk_find_struct_const(info->pNext, PHYSICAL_DEVICE_IMAGE_DRM_FORMAT_MODIFIER_INFO_EXT); @@ -1503,17 +1503,17 @@ radv_get_image_format_properties(struct radv_physical_device *physical_device, maxExtent.height = 1; maxExtent.depth = 1; maxMipLevels = 15; /* log2(maxWidth) + 1 */ - maxArraySize = chip_class >= GFX10 ? 8192 : 2048; + maxArraySize = gfx_level >= GFX10 ? 8192 : 2048; break; case VK_IMAGE_TYPE_2D: maxExtent.width = 16384; maxExtent.height = 16384; maxExtent.depth = 1; maxMipLevels = 15; /* log2(maxWidth) + 1 */ - maxArraySize = chip_class >= GFX10 ? 8192 : 2048; + maxArraySize = gfx_level >= GFX10 ? 8192 : 2048; break; case VK_IMAGE_TYPE_3D: - if (chip_class >= GFX10) { + if (gfx_level >= GFX10) { maxExtent.width = 8192; maxExtent.height = 8192; maxExtent.depth = 8192; @@ -1555,7 +1555,7 @@ radv_get_image_format_properties(struct radv_physical_device *physical_device, } /* We can't create 3d compressed 128bpp images that can be rendered to on GFX9 */ - if (physical_device->rad_info.chip_class >= GFX9 && info->type == VK_IMAGE_TYPE_3D && + if (physical_device->rad_info.gfx_level >= GFX9 && info->type == VK_IMAGE_TYPE_3D && vk_format_get_blocksizebits(format) == 128 && vk_format_is_compressed(format) && (info->flags & VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT) && ((info->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT) || @@ -1624,7 +1624,7 @@ radv_get_image_format_properties(struct radv_physical_device *physical_device, if (info->flags & VK_IMAGE_CREATE_SPARSE_RESIDENCY_BIT) { /* Sparse textures are only supported on GFX8+. */ - if (physical_device->rad_info.chip_class < GFX8) + if (physical_device->rad_info.gfx_level < GFX8) goto unsupported; if (vk_format_get_plane_count(format) > 1 || info->type != VK_IMAGE_TYPE_2D || @@ -1851,7 +1851,7 @@ radv_GetPhysicalDeviceImageFormatProperties2(VkPhysicalDevice physicalDevice, } if (texture_lod_props) { - if (physical_device->rad_info.chip_class >= GFX9) { + if (physical_device->rad_info.gfx_level >= GFX9) { texture_lod_props->supportsTextureGatherLODBiasAMD = true; } else { texture_lod_props->supportsTextureGatherLODBiasAMD = !vk_format_is_int(format); @@ -1885,7 +1885,7 @@ fill_sparse_image_format_properties(struct radv_physical_device *pdev, VkFormat /* On GFX8 we first subdivide by level and then layer, leading to a single * miptail. On GFX9+ we first subdivide by layer and then level which results * in a miptail per layer. */ - if (pdev->rad_info.chip_class < GFX9) + if (pdev->rad_info.gfx_level < GFX9) prop->flags |= VK_SPARSE_IMAGE_FORMAT_SINGLE_MIPTAIL_BIT; /* This assumes the sparse image tile size is always 64 KiB (1 << 16) */ @@ -1956,7 +1956,7 @@ radv_GetImageSparseMemoryRequirements2(VkDevice _device, req->memoryRequirements.imageMipTailFirstLod = image->planes[0].surface.first_mip_tail_level; if (req->memoryRequirements.imageMipTailFirstLod < image->info.levels) { - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { /* The tail is always a single tile per layer. */ req->memoryRequirements.imageMipTailSize = 65536; req->memoryRequirements.imageMipTailOffset = diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 499262531b8..e3ac129abfd 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -52,7 +52,7 @@ radv_choose_tiling(struct radv_device *device, const VkImageCreateInfo *pCreateI return RADEON_SURF_MODE_2D; if (!vk_format_is_compressed(format) && !vk_format_is_depth_or_stencil(format) && - device->physical_device->rad_info.chip_class <= GFX8) { + device->physical_device->rad_info.gfx_level <= GFX8) { /* this causes hangs in some VK CTS tests on GFX9. */ /* Textures with a very small height are recommended to be linear. */ if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D || @@ -70,7 +70,7 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device, const VkImageCrea VkFormat format) { /* TC-compat HTILE is only available for GFX8+. */ - if (device->physical_device->rad_info.chip_class < GFX8) + if (device->physical_device->rad_info.gfx_level < GFX8) return false; if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT)) @@ -86,7 +86,7 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device, const VkImageCrea VK_IMAGE_USAGE_TRANSFER_SRC_BIT))) return false; - if (device->physical_device->rad_info.chip_class < GFX9) { + if (device->physical_device->rad_info.gfx_level < GFX9) { /* TC-compat HTILE for MSAA depth/stencil images is broken * on GFX8 because the tiling doesn't match. */ @@ -110,7 +110,7 @@ static bool radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info) { if (info->bo_metadata) { - if (device->physical_device->rad_info.chip_class >= GFX9) + if (device->physical_device->rad_info.gfx_level >= GFX9) return info->bo_metadata->u.gfx9.scanout; else return info->bo_metadata->u.legacy.scanout; @@ -230,7 +230,7 @@ radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *imag bool *sign_reinterpret) { /* DCC (Delta Color Compression) is only available for GFX8+. */ - if (device->physical_device->rad_info.chip_class < GFX8) + if (device->physical_device->rad_info.gfx_level < GFX8) return false; if (device->instance->debug_flags & RADV_DEBUG_NO_DCC) @@ -247,7 +247,7 @@ radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *imag * decompressing a lot anyway we might as well not have DCC. */ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) && - (device->physical_device->rad_info.chip_class < GFX10 || + (device->physical_device->rad_info.gfx_level < GFX10 || radv_formats_is_atomic_allowed(device, pCreateInfo->pNext, format, pCreateInfo->flags))) return false; @@ -269,14 +269,14 @@ radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *imag if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1) return false; - if (device->physical_device->rad_info.chip_class < GFX10) { + if (device->physical_device->rad_info.gfx_level < GFX10) { /* TODO: Add support for DCC MSAA on GFX8-9. */ if (pCreateInfo->samples > 1 && !device->physical_device->dcc_msaa_allowed) return false; /* TODO: Add support for DCC layers/mipmaps on GFX9. */ if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) && - device->physical_device->rad_info.chip_class == GFX9) + device->physical_device->rad_info.gfx_level == GFX9) return false; } @@ -317,7 +317,7 @@ radv_use_dcc_for_image_late(struct radv_device *device, struct radv_image *image bool radv_image_use_dcc_image_stores(const struct radv_device *device, const struct radv_image *image) { - return ac_surface_supports_dcc_image_stores(device->physical_device->rad_info.chip_class, + return ac_surface_supports_dcc_image_stores(device->physical_device->rad_info.gfx_level, &image->planes[0].surface); } @@ -346,10 +346,10 @@ radv_use_htile_for_image(const struct radv_device *device, const struct radv_ima * - Enable on other gens. */ bool use_htile_for_mips = - image->info.array_size == 1 && device->physical_device->rad_info.chip_class >= GFX10; + image->info.array_size == 1 && device->physical_device->rad_info.gfx_level >= GFX10; /* Stencil texturing with HTILE doesn't work with mipmapping on Navi10-14. */ - if (device->physical_device->rad_info.chip_class == GFX10 && + if (device->physical_device->rad_info.gfx_level == GFX10 && image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT && image->info.levels > 1) return false; @@ -371,7 +371,7 @@ static bool radv_use_tc_compat_cmask_for_image(struct radv_device *device, struct radv_image *image) { /* TC-compat CMASK is only available for GFX8+. */ - if (device->physical_device->rad_info.chip_class < GFX8) + if (device->physical_device->rad_info.gfx_level < GFX8) return false; if (device->instance->debug_flags & RADV_DEBUG_NO_TC_COMPAT_CMASK) @@ -379,7 +379,7 @@ radv_use_tc_compat_cmask_for_image(struct radv_device *device, struct radv_image /* TC-compat CMASK with storage images is supported on GFX10+. */ if ((image->usage & VK_IMAGE_USAGE_STORAGE_BIT) && - device->physical_device->rad_info.chip_class < GFX10) + device->physical_device->rad_info.gfx_level < GFX10) return false; /* Do not enable TC-compatible if the image isn't readable by a shader @@ -420,7 +420,7 @@ radv_patch_surface_from_metadata(struct radv_device *device, struct radeon_surf { surface->flags = RADEON_SURF_CLR(surface->flags, MODE); - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { if (md->u.gfx9.swizzle_mode > 0) surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); else @@ -463,7 +463,7 @@ radv_patch_image_dimensions(struct radv_device *device, struct radv_image *image radv_is_valid_opaque_metadata(device, create_info->bo_metadata)) { const struct radeon_bo_metadata *md = create_info->bo_metadata; - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { width = G_00A004_WIDTH_LO(md->metadata[3]) + (G_00A008_WIDTH_HI(md->metadata[4]) << 2) + 1; height = G_00A008_HEIGHT(md->metadata[4]) + 1; } else { @@ -483,7 +483,7 @@ radv_patch_image_dimensions(struct radv_device *device, struct radv_image *image "(internal dimensions: %d x %d, external dimensions: %d x %d)\n", image->info.width, image->info.height, width, height); return VK_ERROR_INVALID_EXTERNAL_HANDLE; - } else if (device->physical_device->rad_info.chip_class >= GFX10) { + } else if (device->physical_device->rad_info.gfx_level >= GFX10) { fprintf(stderr, "Tried to import an image with inconsistent width on GFX10.\n" "As GFX10 has no separate stride fields we cannot cope with\n" @@ -528,7 +528,7 @@ radv_patch_image_from_extra_info(struct radv_device *device, struct radv_image * image->info.surf_index = NULL; } - if (create_info->prime_blit_src && device->physical_device->rad_info.chip_class == GFX9) { + if (create_info->prime_blit_src && device->physical_device->rad_info.gfx_level == GFX9) { /* Older SDMA hw can't handle DCC */ image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC; } @@ -627,7 +627,7 @@ radv_get_surface_flags(struct radv_device *device, struct radv_image *image, uns if (is_stencil) flags |= RADEON_SURF_SBUFFER; - if (device->physical_device->rad_info.chip_class >= GFX9 && + if (device->physical_device->rad_info.gfx_level >= GFX9 && pCreateInfo->imageType == VK_IMAGE_TYPE_3D && vk_format_get_blocksizebits(image_format) == 128 && vk_format_is_compressed(image_format)) flags |= RADEON_SURF_NO_RENDER_TARGET; @@ -726,7 +726,7 @@ radv_make_buffer_descriptor(struct radv_device *device, struct radv_buffer *buff state[0] = va; state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride); - if (device->physical_device->rad_info.chip_class != GFX8 && stride) { + if (device->physical_device->rad_info.gfx_level != GFX8 && stride) { range /= stride; } @@ -736,7 +736,7 @@ radv_make_buffer_descriptor(struct radv_device *device, struct radv_buffer *buff S_008F0C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) | S_008F0C_DST_SEL_W(radv_map_swizzle(swizzle[3])); - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { const struct gfx10_format *fmt = &gfx10_format_table[vk_format_to_pipe_format(vk_format)]; /* OOB_SELECT chooses the out-of-bounds check: @@ -770,9 +770,9 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im struct radv_image_plane *plane = &image->planes[plane_id]; uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0; uint64_t va = gpu_address; - enum chip_class chip_class = device->physical_device->rad_info.chip_class; + enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; uint64_t meta_va = 0; - if (chip_class >= GFX9) { + if (gfx_level >= GFX9) { if (is_stencil) va += plane->surface.u.gfx9.zs.stencil_offset; else @@ -781,17 +781,17 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im va += (uint64_t)base_level_info->offset_256B * 256; state[0] = va >> 8; - if (chip_class >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D) + if (gfx_level >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D) state[0] |= plane->surface.tile_swizzle; state[1] &= C_008F14_BASE_ADDRESS_HI; state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40); - if (chip_class >= GFX8) { + if (gfx_level >= GFX8) { state[6] &= C_008F28_COMPRESSION_EN; state[7] = 0; if (!disable_compression && radv_dcc_enabled(image, first_level)) { meta_va = gpu_address + plane->surface.meta_offset; - if (chip_class <= GFX8) + if (gfx_level <= GFX8) meta_va += plane->surface.u.legacy.color.dcc_level[base_level].dcc_offset; unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8; @@ -803,12 +803,12 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im if (meta_va) { state[6] |= S_008F28_COMPRESSION_EN(1); - if (chip_class <= GFX9) + if (gfx_level <= GFX9) state[7] = meta_va >> 8; } } - if (chip_class >= GFX10) { + if (gfx_level >= GFX10) { state[3] &= C_00A00C_SW_MODE; if (is_stencil) { @@ -836,7 +836,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im } state[7] = meta_va >> 16; - } else if (chip_class == GFX9) { + } else if (gfx_level == GFX9) { state[3] &= C_008F1C_SW_MODE; state[4] &= C_008F20_PITCH; @@ -938,7 +938,7 @@ vi_alpha_is_on_msb(struct radv_device *device, VkFormat format) { const struct util_format_description *desc = vk_format_description(format); - if (device->physical_device->rad_info.chip_class >= GFX10 && desc->nr_channels == 1) + if (device->physical_device->rad_info.gfx_level >= GFX10 && desc->nr_channels == 1) return desc->swizzle[3] == PIPE_SWIZZLE_X; return radv_translate_colorswap(format, false) <= 1; @@ -982,7 +982,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima type = V_008F1C_SQ_RSRC_IMG_3D; } else { type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples, - is_storage_image, device->physical_device->rad_info.chip_class == GFX9); + is_storage_image, device->physical_device->rad_info.gfx_level == GFX9); } if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) { @@ -1141,7 +1141,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, } /* S8 with either Z16 or Z32 HTILE need a special format. */ - if (device->physical_device->rad_info.chip_class == GFX9 && vk_format == VK_FORMAT_S8_UINT && + if (device->physical_device->rad_info.gfx_level == GFX9 && vk_format == VK_FORMAT_S8_UINT && radv_image_is_tc_compat_htile(image)) { if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT) data_format = V_008F14_IMG_DATA_FORMAT_S8_32; @@ -1149,13 +1149,13 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, data_format = V_008F14_IMG_DATA_FORMAT_S8_16; } - if (device->physical_device->rad_info.chip_class == GFX9 && + if (device->physical_device->rad_info.gfx_level == GFX9 && img_create_flags & VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT) { assert(image->type == VK_IMAGE_TYPE_3D); type = V_008F1C_SQ_RSRC_IMG_3D; } else { type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples, - is_storage_image, device->physical_device->rad_info.chip_class == GFX9); + is_storage_image, device->physical_device->rad_info.gfx_level == GFX9); } if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) { @@ -1185,7 +1185,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, state[6] = 0; state[7] = 0; - if (device->physical_device->rad_info.chip_class == GFX9) { + if (device->physical_device->rad_info.gfx_level == GFX9) { unsigned bc_swizzle = gfx9_border_color_swizzle(desc); /* Depth is the last accessible layer on Gfx9. @@ -1212,7 +1212,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, /* The last dword is unused by hw. The shader uses it to clear * bits in the first dword of sampler state. */ - if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) { + if (device->physical_device->rad_info.gfx_level <= GFX7 && image->info.samples <= 1) { if (first_level == last_level) state[7] = C_008F30_MAX_ANISO_RATIO; else @@ -1232,7 +1232,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, va = gpu_address + image->offset + image->planes[0].surface.fmask_offset; - if (device->physical_device->rad_info.chip_class == GFX9) { + if (device->physical_device->rad_info.gfx_level == GFX9) { fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK; switch (image->info.samples) { case 2: @@ -1280,7 +1280,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, fmask_state[6] = 0; fmask_state[7] = 0; - if (device->physical_device->rad_info.chip_class == GFX9) { + if (device->physical_device->rad_info.gfx_level == GFX9) { fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode); fmask_state[4] |= S_008F20_DEPTH(last_layer) | S_008F20_PITCH(image->planes[0].surface.u.gfx9.color.fmask_epitch); @@ -1321,7 +1321,7 @@ radv_make_texture_descriptor(struct radv_device *device, struct radv_image *imag unsigned width, unsigned height, unsigned depth, float min_lod, uint32_t *state, uint32_t *fmask_state, VkImageCreateFlags img_create_flags) { - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { gfx10_make_texture_descriptor(device, image, is_storage_image, view_type, vk_format, mapping, first_level, last_level, first_layer, last_layer, width, height, depth, min_lod, state, fmask_state, img_create_flags); @@ -1362,7 +1362,7 @@ radv_init_metadata(struct radv_device *device, struct radv_image *image, memset(metadata, 0, sizeof(*metadata)); - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { uint64_t dcc_offset = image->offset + (surface->display_dcc_offset ? surface->display_dcc_offset : surface->meta_offset); @@ -1461,14 +1461,14 @@ radv_image_is_pipe_misaligned(const struct radv_device *device, const struct rad struct radeon_info *rad_info = &device->physical_device->rad_info; int log2_samples = util_logbase2(image->info.samples); - assert(rad_info->chip_class >= GFX10); + assert(rad_info->gfx_level >= GFX10); for (unsigned i = 0; i < image->plane_count; ++i) { VkFormat fmt = radv_image_get_plane_format(device->physical_device, image, i); int log2_bpp = util_logbase2(vk_format_get_blocksize(fmt)); int log2_bpp_and_samples; - if (rad_info->chip_class >= GFX10_3) { + if (rad_info->gfx_level >= GFX10_3) { log2_bpp_and_samples = log2_bpp + log2_samples; } else { if (vk_format_has_depth(image->vk_format) && image->info.array_size >= 8) { @@ -1506,10 +1506,10 @@ radv_image_is_pipe_misaligned(const struct radv_device *device, const struct rad static bool radv_image_is_l2_coherent(const struct radv_device *device, const struct radv_image *image) { - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { return !device->physical_device->rad_info.tcc_rb_non_coherent && !radv_image_is_pipe_misaligned(device, image); - } else if (device->physical_device->rad_info.chip_class == GFX9) { + } else if (device->physical_device->rad_info.gfx_level == GFX9) { if (image->info.samples == 1 && (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT | VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) && @@ -1560,7 +1560,7 @@ static bool radv_image_use_comp_to_single(const struct radv_device *device, const struct radv_image *image) { /* comp-to-single is only available for GFX10+. */ - if (device->physical_device->rad_info.chip_class < GFX10) + if (device->physical_device->rad_info.gfx_level < GFX10) return false; /* If the image can't be fast cleared, comp-to-single can't be used. */ @@ -1694,7 +1694,7 @@ radv_image_create_layout(struct radv_device *device, struct radv_image_create_in return VK_ERROR_INVALID_DRM_FORMAT_MODIFIER_PLANE_LAYOUT_EXT; for (unsigned i = 1; i < mem_planes; ++i) { - if (ac_surface_get_plane_offset(device->physical_device->rad_info.chip_class, + if (ac_surface_get_plane_offset(device->physical_device->rad_info.gfx_level, &image->planes[plane].surface, i, 0) != mod_info->pPlaneLayouts[i].offset) return VK_ERROR_INVALID_DRM_FORMAT_MODIFIER_PLANE_LAYOUT_EXT; @@ -1753,7 +1753,7 @@ radv_image_print_info(struct radv_device *device, struct radv_image *image) const struct radv_image_plane *plane = &image->planes[i]; const struct radeon_surf *surf = &plane->surface; const struct util_format_description *desc = vk_format_description(plane->format); - uint64_t offset = ac_surface_get_plane_offset(device->physical_device->rad_info.chip_class, + uint64_t offset = ac_surface_get_plane_offset(device->physical_device->rad_info.gfx_level, &plane->surface, 0, 0); fprintf(stderr, " Plane[%u]: vkformat=%s, offset=%" PRIu64 "\n", i, desc->name, offset); @@ -1947,7 +1947,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format); - if (device->physical_device->rad_info.chip_class >= GFX9) + if (device->physical_device->rad_info.gfx_level >= GFX9) hw_level = iview->base_mip; radv_make_texture_descriptor( device, image, is_storage_image, iview->type, vk_format, components, hw_level, @@ -1960,7 +1960,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic img_create_flags); const struct legacy_surf_level *base_level_info = NULL; - if (device->physical_device->rad_info.chip_class <= GFX9) { + if (device->physical_device->rad_info.gfx_level <= GFX9) { if (is_stencil) base_level_info = &plane->surface.u.legacy.zs.stencil_level[iview->base_mip]; else @@ -2118,7 +2118,7 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, plane_count = 1; } - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { iview->extent = (VkExtent3D){ .width = image->info.width, .height = image->info.height, @@ -2167,7 +2167,7 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, * block compatible format and the compressed format, so even if we take * the plain converted dimensions the physical layout is correct. */ - if (device->physical_device->rad_info.chip_class >= GFX9 && + if (device->physical_device->rad_info.gfx_level >= GFX9 && vk_format_is_compressed(image->vk_format) && !vk_format_is_compressed(iview->vk_format)) { /* If we have multiple levels in the view we should ideally take the last level, * but the mip calculation has a max(..., 1) so walking back to the base mip in an @@ -2306,7 +2306,7 @@ radv_layout_dcc_compressed(const struct radv_device *device, const struct radv_i (queue_mask & (1u << RADV_QUEUE_COMPUTE)) && !radv_image_use_dcc_image_stores(device, image)) return false; - return device->physical_device->rad_info.chip_class >= GFX10 || layout != VK_IMAGE_LAYOUT_GENERAL; + return device->physical_device->rad_info.gfx_level >= GFX10 || layout != VK_IMAGE_LAYOUT_GENERAL; } bool @@ -2402,17 +2402,17 @@ radv_GetImageSubresourceLayout(VkDevice _device, VkImage _image, assert(level == 0); assert(layer == 0); - pLayout->offset = ac_surface_get_plane_offset(device->physical_device->rad_info.chip_class, + pLayout->offset = ac_surface_get_plane_offset(device->physical_device->rad_info.gfx_level, surface, mem_plane_id, 0); - pLayout->rowPitch = ac_surface_get_plane_stride(device->physical_device->rad_info.chip_class, + pLayout->rowPitch = ac_surface_get_plane_stride(device->physical_device->rad_info.gfx_level, surface, mem_plane_id, level); pLayout->arrayPitch = 0; pLayout->depthPitch = 0; pLayout->size = ac_surface_get_plane_size(surface, mem_plane_id); - } else if (device->physical_device->rad_info.chip_class >= GFX9) { + } else if (device->physical_device->rad_info.gfx_level >= GFX9) { uint64_t level_offset = surface->is_linear ? surface->u.gfx9.offset[level] : 0; - pLayout->offset = ac_surface_get_plane_offset(device->physical_device->rad_info.chip_class, + pLayout->offset = ac_surface_get_plane_offset(device->physical_device->rad_info.gfx_level, &plane->surface, 0, layer) + level_offset; if (image->vk_format == VK_FORMAT_R32G32B32_UINT || diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c index f60baf80519..306cb6c249a 100644 --- a/src/amd/vulkan/radv_meta_buffer.c +++ b/src/amd/vulkan/radv_meta_buffer.c @@ -235,7 +235,7 @@ radv_prefer_compute_dma(const struct radv_device *device, uint64_t size, { bool use_compute = size >= RADV_BUFFER_OPS_CS_THRESHOLD; - if (device->physical_device->rad_info.chip_class >= GFX10 && + if (device->physical_device->rad_info.gfx_level >= GFX10 && device->physical_device->rad_info.has_dedicated_vram) { if ((src_bo && !(src_bo->initial_domain & RADEON_DOMAIN_VRAM)) || !(dst_bo->initial_domain & RADEON_DOMAIN_VRAM)) { diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index 594ddc17b80..8c389a79b75 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -1324,7 +1324,7 @@ get_image_stride_for_r32g32b32(struct radv_cmd_buffer *cmd_buffer, { unsigned stride; -if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { stride = surf->image->planes[0].surface.u.gfx9.surf_pitch; } else { stride = surf->image->planes[0].surface.u.legacy.level[0].nblk_x * 3; diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index c61c4862c44..be9b522a2db 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1268,7 +1268,7 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, uint64_t offset = image->offset + image->planes[0].surface.cmask_offset; uint64_t size; - if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) { /* TODO: clear layers. */ size = image->planes[0].surface.cmask_size; } else { @@ -1314,12 +1314,12 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, uint32_t level = range->baseMipLevel + l; uint64_t size; - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) { /* DCC for mipmaps+layers is currently disabled. */ offset += image->planes[0].surface.meta_slice_size * range->baseArrayLayer + image->planes[0].surface.u.gfx9.meta_levels[level].offset; size = image->planes[0].surface.u.gfx9.meta_levels[level].size * layer_count; - } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { + } else if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) { /* Mipmap levels and layers aren't implemented. */ assert(level == 0); size = image->planes[0].surface.meta_size; @@ -1472,7 +1472,7 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im htile_mask = radv_get_htile_mask(cmd_buffer->device, image, range->aspectMask); if (level_count != image->info.levels) { - assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10); + assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10); /* Clear individuals levels separately. */ for (uint32_t l = 0; l < level_count; l++) { @@ -1667,7 +1667,7 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_ &can_avoid_fast_clear_elim); if (iview->image->info.levels > 1) { - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { uint32_t last_level = iview->base_mip + iview->level_count - 1; if (last_level >= iview->image->planes[0].surface.num_meta_levels) { /* Do not fast clears if one level can't be fast cleard. */ diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c index fb672e3e2c3..464cda90e23 100644 --- a/src/amd/vulkan/radv_meta_copy.c +++ b/src/amd/vulkan/radv_meta_copy.c @@ -115,7 +115,7 @@ radv_image_is_renderable(struct radv_device *device, struct radv_image *image) image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) return false; - if (device->physical_device->rad_info.chip_class >= GFX9 && image->type == VK_IMAGE_TYPE_3D && + if (device->physical_device->rad_info.gfx_level >= GFX9 && image->type == VK_IMAGE_TYPE_3D && vk_format_get_blocksizebits(image->vk_format) == 128 && vk_format_is_compressed(image->vk_format)) return false; diff --git a/src/amd/vulkan/radv_meta_fmask_copy.c b/src/amd/vulkan/radv_meta_fmask_copy.c index 38855f1267a..e61bca1c2ec 100644 --- a/src/amd/vulkan/radv_meta_fmask_copy.c +++ b/src/amd/vulkan/radv_meta_fmask_copy.c @@ -251,7 +251,7 @@ radv_can_use_fmask_copy(struct radv_cmd_buffer *cmd_buffer, unsigned num_rects, const struct radv_meta_blit2d_rect *rects) { /* TODO: Test on pre GFX10 chips. */ - if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX10) + if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX10) return false; /* TODO: Add support for layers. */ diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c index 9db6c08da91..31dd0285fff 100644 --- a/src/amd/vulkan/radv_meta_resolve.c +++ b/src/amd/vulkan/radv_meta_resolve.c @@ -280,7 +280,7 @@ static bool image_hw_resolve_compat(const struct radv_device *device, struct radv_image *src_image, struct radv_image *dst_image) { - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { return dst_image->planes[0].surface.u.gfx9.swizzle_mode == src_image->planes[0].surface.u.gfx9.swizzle_mode; } else { diff --git a/src/amd/vulkan/radv_nir_apply_pipeline_layout.c b/src/amd/vulkan/radv_nir_apply_pipeline_layout.c index e9c1bc5ce3b..29235ca9544 100644 --- a/src/amd/vulkan/radv_nir_apply_pipeline_layout.c +++ b/src/amd/vulkan/radv_nir_apply_pipeline_layout.c @@ -29,7 +29,7 @@ #include "radv_shader_args.h" typedef struct { - enum chip_class chip_class; + enum amd_gfx_level gfx_level; uint32_t address32_hi; bool disable_aniso_single_level; bool has_image_load_dcc_bug; @@ -161,7 +161,7 @@ load_inline_buffer_descriptor(nir_builder *b, apply_layout_state *state, nir_ssa uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (state->chip_class >= GFX10) { + if (state->gfx_level >= GFX10) { desc_type |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -481,7 +481,7 @@ apply_layout_to_tex(nir_builder *b, apply_layout_state *state, nir_tex_instr *te tex->sampler_non_uniform, tex, false); if (state->disable_aniso_single_level && tex->sampler_dim < GLSL_SAMPLER_DIM_RECT && - state->chip_class < GFX8) { + state->gfx_level < GFX8) { /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL. * * GFX6-GFX7: @@ -527,7 +527,7 @@ radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device, const struct radv_shader_args *args) { apply_layout_state state = { - .chip_class = device->physical_device->rad_info.chip_class, + .gfx_level = device->physical_device->rad_info.gfx_level, .address32_hi = device->physical_device->rad_info.address32_hi, .disable_aniso_single_level = device->instance->disable_aniso_single_level, .has_image_load_dcc_bug = device->physical_device->rad_info.has_image_load_dcc_bug, diff --git a/src/amd/vulkan/radv_nir_lower_abi.c b/src/amd/vulkan/radv_nir_lower_abi.c index fd32c353514..249aa57e44a 100644 --- a/src/amd/vulkan/radv_nir_lower_abi.c +++ b/src/amd/vulkan/radv_nir_lower_abi.c @@ -30,7 +30,7 @@ #include "radv_shader_args.h" typedef struct { - enum chip_class chip_class; + enum amd_gfx_level gfx_level; const struct radv_shader_args *args; const struct radv_shader_info *info; const struct radv_pipeline_key *pl_key; @@ -221,14 +221,12 @@ filter_abi_instr(const nir_instr *instr, } void -radv_nir_lower_abi(nir_shader *shader, - enum chip_class chip_class, - const struct radv_shader_info *info, - const struct radv_shader_args *args, +radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, + const struct radv_shader_info *info, const struct radv_shader_args *args, const struct radv_pipeline_key *pl_key) { lower_abi_state state = { - .chip_class = chip_class, + .gfx_level = gfx_level, .info = info, .args = args, .pl_key = pl_key, diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 6069f573e40..55136212c7b 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -169,7 +169,7 @@ is_pre_gs_stage(gl_shader_stage stage) static void create_function(struct radv_shader_context *ctx, gl_shader_stage stage, bool has_previous_stage) { - if (ctx->ac.chip_class >= GFX10) { + if (ctx->ac.gfx_level >= GFX10) { if (is_pre_gs_stage(stage) && ctx->shader_info->is_ngg) { /* On GFX10, VS is merged into GS for NGG. */ stage = MESA_SHADER_GEOMETRY; @@ -466,11 +466,11 @@ load_vs_input(struct radv_shader_context *ctx, unsigned driver_location, LLVMTyp * dynamic) is unaligned and also if the VBO offset is aligned to a scalar (eg. stride is 8 and * VBO offset is 2 for R16G16B16A16_SNORM). */ - if (ctx->ac.chip_class == GFX6 || ctx->ac.chip_class >= GFX10) { + if (ctx->ac.gfx_level == GFX6 || ctx->ac.gfx_level >= GFX10) { unsigned chan_format = vtx_info->chan_format; LLVMValueRef values[4]; - assert(ctx->ac.chip_class == GFX6 || ctx->ac.chip_class >= GFX10); + assert(ctx->ac.gfx_level == GFX6 || ctx->ac.gfx_level >= GFX10); for (unsigned chan = 0; chan < num_channels; chan++) { unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size; @@ -645,7 +645,7 @@ si_llvm_init_export_args(struct radv_shader_context *ctx, LLVMValueRef *values, break; case V_028714_SPI_SHADER_32_AR: - if (ctx->ac.chip_class >= GFX10) { + if (ctx->ac.gfx_level >= GFX10) { args->enabled_channels = 0x3; args->out[0] = values[0]; args->out[1] = values[3]; @@ -986,7 +986,7 @@ radv_llvm_export_vs(struct radv_shader_context *ctx, struct radv_shader_output_v if (outinfo->writes_layer == true) pos_args[1].out[2] = layer_value; if (outinfo->writes_viewport_index == true) { - if (ctx->options->chip_class >= GFX9) { + if (ctx->options->gfx_level >= GFX9) { /* GFX9 has the layer in out.z[10:0] and the viewport * index in out.z[19:16]. */ @@ -1011,7 +1011,7 @@ radv_llvm_export_vs(struct radv_shader_context *ctx, struct radv_shader_output_v /* GFX10 skip POS0 exports if EXEC=0 and DONE=0, causing a hang. * Setting valid_mask=1 prevents it and has no other effect. */ - if (ctx->ac.chip_class == GFX10) + if (ctx->ac.gfx_level == GFX10) pos_args[0].valid_mask = 1; pos_idx = 0; @@ -1822,7 +1822,7 @@ emit_gs_epilogue(struct radv_shader_context *ctx) return; } - if (ctx->ac.chip_class >= GFX10) + if (ctx->ac.gfx_level >= GFX10) ac_build_waitcnt(&ctx->ac, AC_WAIT_VSTORE); ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id); @@ -1881,7 +1881,7 @@ ac_llvm_finalize_module(struct radv_shader_context *ctx, LLVMPassManagerRef pass static void ac_setup_rings(struct radv_shader_context *ctx) { - if (ctx->options->chip_class <= GFX8 && + if (ctx->options->gfx_level <= GFX8 && (ctx->stage == MESA_SHADER_GEOMETRY || (ctx->stage == MESA_SHADER_VERTEX && ctx->shader_info->vs.as_es) || (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->shader_info->tes.as_es))) { @@ -2041,13 +2041,13 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, float_mode = AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO; } - ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class, options->family, - options->info, float_mode, info->wave_size, info->ballot_bit_size); + ac_llvm_context_init(&ctx.ac, ac_llvm, options->gfx_level, options->family, options->info, + float_mode, info->wave_size, info->ballot_bit_size); ctx.context = ctx.ac.context; ctx.max_workgroup_size = info->workgroup_size; - if (ctx.ac.chip_class >= GFX10) { + if (ctx.ac.gfx_level >= GFX10) { if (is_pre_gs_stage(shaders[0]->info.stage) && info->is_ngg) { ctx.max_workgroup_size = 128; } @@ -2091,7 +2091,7 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, declare_esgs_ring(&ctx); /* GFX10 hang workaround - there needs to be an s_barrier before gs_alloc_req always */ - if (ctx.ac.chip_class == GFX10 && shader_count == 1) + if (ctx.ac.gfx_level == GFX10 && shader_count == 1) ac_build_s_barrier(&ctx.ac, shaders[0]->info.stage); } @@ -2426,8 +2426,8 @@ radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm, assert(args->is_gs_copy_shader); - ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class, options->family, - options->info, AC_FLOAT_MODE_DEFAULT, 64, 64); + ac_llvm_context_init(&ctx.ac, ac_llvm, options->gfx_level, options->family, options->info, + AC_FLOAT_MODE_DEFAULT, 64, 64); ctx.context = ctx.ac.context; ctx.stage = MESA_SHADER_VERTEX; diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 2e293fa6e7d..76ccce25ef9 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1183,7 +1183,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) | S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1); ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE( - pipeline->device->physical_device->rad_info.chip_class >= GFX9) | + pipeline->device->physical_device->rad_info.gfx_level >= GFX9) | S_028A48_VPORT_SCISSOR_ENABLE(1); const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line = vk_find_struct_const( @@ -1217,7 +1217,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) | S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */ S_028BE0_COVERED_CENTROID_IS_CENTER( - pipeline->device->physical_device->rad_info.chip_class >= GFX10_3); + pipeline->device->physical_device->rad_info.gfx_level >= GFX10_3); ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); if (ps_iter_samples > 1) pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); @@ -1500,7 +1500,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline) /* GS requirement. */ ia_multi_vgt_param.partial_es_wave = false; - if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8) + if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.gfx_level <= GFX8) if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3) ia_multi_vgt_param.partial_es_wave = true; @@ -1527,7 +1527,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline) /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */ if (device->physical_device->rad_info.has_distributed_tess) { if (radv_pipeline_has_gs(pipeline)) { - if (device->physical_device->rad_info.chip_class <= GFX8) + if (device->physical_device->rad_info.gfx_level <= GFX8) ia_multi_vgt_param.partial_es_wave = true; } else { ia_multi_vgt_param.partial_vs_wave = true; @@ -1558,9 +1558,9 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline) ia_multi_vgt_param.base = S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) | /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */ - S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) | - S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) | - S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9); + S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.gfx_level == GFX8 ? 2 : 0) | + S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.gfx_level >= GFX9) | + S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.gfx_level >= GFX9); return ia_multi_vgt_param; } @@ -1963,7 +1963,7 @@ radv_pipeline_init_raster_state(struct radv_pipeline *pipeline, S_028814_POLY_OFFSET_PARA_ENABLE(raster_info->depthBiasEnable ? 1 : 0) | S_028814_PROVOKING_VTX_LAST(provoking_vtx_last); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { /* It should also be set if PERPENDICULAR_ENDCAP_ENA is set. */ pipeline->graphics.pa_su_sc_mode_cntl |= S_028814_KEEP_TOGETHER_ENABLE(raster_info->polygonMode != VK_POLYGON_MODE_FILL); @@ -2026,7 +2026,7 @@ radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline, /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */ ds_state.db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(vkms && vkms->rasterizationSamples > 2); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10_3) ds_state.db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE(1); db_depth_control = S_028800_Z_ENABLE(ds_info->depthTestEnable ? 1 : 0) | @@ -2071,7 +2071,7 @@ gfx9_get_gs_info(const struct radv_pipeline_key *key, const struct radv_pipeline struct radv_shader_info *gs_info = &stages[MESA_SHADER_GEOMETRY].info; struct radv_es_output_info *es_info; bool has_tess = !!stages[MESA_SHADER_TESS_CTRL].nir; - if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) es_info = has_tess ? &gs_info->tes.es_info : &gs_info->vs.es_info; else es_info = has_tess ? &stages[MESA_SHADER_TESS_EVAL].info.tes.es_info @@ -2180,10 +2180,9 @@ gfx9_get_gs_info(const struct radv_pipeline_key *key, const struct radv_pipeline assert(max_prims_per_subgroup <= max_out_prims); gl_shader_stage es_stage = has_tess ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; - unsigned workgroup_size = - ac_compute_esgs_workgroup_size( - pipeline->device->physical_device->rad_info.chip_class, stages[es_stage].info.wave_size, - es_verts_per_subgroup, gs_inst_prims_in_subgroup); + unsigned workgroup_size = ac_compute_esgs_workgroup_size( + pipeline->device->physical_device->rad_info.gfx_level, stages[es_stage].info.wave_size, + es_verts_per_subgroup, gs_inst_prims_in_subgroup); stages[es_stage].info.workgroup_size = workgroup_size; stages[MESA_SHADER_GEOMETRY].info.workgroup_size = workgroup_size; } @@ -2221,7 +2220,8 @@ radv_get_num_input_vertices(const struct radv_pipeline_stage *stages) } static void -gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, enum chip_class chip_class, uint32_t oversub_pc_lines) +gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, + uint32_t oversub_pc_lines) { radeon_set_uconfig_reg( cs, R_030980_GE_PC_ALLOC, @@ -2318,7 +2318,7 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, struct radv_pipeline *pi /* All these are per subgroup: */ const unsigned min_esverts = - pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 29 : 24; + pipeline->device->physical_device->rad_info.gfx_level >= GFX10_3 ? 29 : 24; bool max_vert_out_per_gs_instance = false; unsigned max_esverts_base = 128; unsigned max_gsprims_base = 128; /* default prim group size clamp */ @@ -2425,7 +2425,7 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, struct radv_pipeline *pi max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim); /* Hardware restriction: minimum value of max_esverts */ - if (pipeline->device->physical_device->rad_info.chip_class == GFX10) + if (pipeline->device->physical_device->rad_info.gfx_level == GFX10) max_esverts = MAX2(max_esverts, min_esverts - 1 + max_verts_per_prim); else max_esverts = MAX2(max_esverts, min_esverts); @@ -2448,13 +2448,13 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, struct radv_pipeline *pi } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims); /* Verify the restriction. */ - if (pipeline->device->physical_device->rad_info.chip_class == GFX10) + if (pipeline->device->physical_device->rad_info.gfx_level == GFX10) assert(max_esverts >= min_esverts - 1 + max_verts_per_prim); else assert(max_esverts >= min_esverts); } else { /* Hardware restriction: minimum value of max_esverts */ - if (pipeline->device->physical_device->rad_info.chip_class == GFX10) + if (pipeline->device->physical_device->rad_info.gfx_level == GFX10) max_esverts = MAX2(max_esverts, min_esverts - 1 + max_verts_per_prim); else max_esverts = MAX2(max_esverts, min_esverts); @@ -2478,7 +2478,7 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, struct radv_pipeline *pi * whenever this check passes, there is enough space for a full * primitive without vertex reuse. */ - if (pipeline->device->physical_device->rad_info.chip_class == GFX10) + if (pipeline->device->physical_device->rad_info.gfx_level == GFX10) ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1; else ngg->hw_max_esverts = max_esverts; @@ -2520,7 +2520,7 @@ radv_pipeline_init_gs_ring_state(struct radv_pipeline *pipeline, const struct gf * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2). */ unsigned gs_vertex_reuse = - (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se; + (device->physical_device->rad_info.gfx_level >= GFX8 ? 32 : 16) * num_se; unsigned alignment = 256 * num_se; /* The maximum size is 63.999 MB per SE. */ unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; @@ -2538,7 +2538,7 @@ radv_pipeline_init_gs_ring_state(struct radv_pipeline *pipeline, const struct gf esgs_ring_size = align(esgs_ring_size, alignment); gsvs_ring_size = align(gsvs_ring_size, alignment); - if (pipeline->device->physical_device->rad_info.chip_class <= GFX8) + if (pipeline->device->physical_device->rad_info.gfx_level <= GFX8) pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size); @@ -2747,7 +2747,7 @@ radv_link_shaders(struct radv_pipeline *pipeline, bool has_geom_tess = stages[MESA_SHADER_GEOMETRY].nir || stages[MESA_SHADER_TESS_CTRL].nir; bool merged_gs = stages[MESA_SHADER_GEOMETRY].nir && - pipeline->device->physical_device->rad_info.chip_class >= GFX9; + pipeline->device->physical_device->rad_info.gfx_level >= GFX9; if (!optimize_conservatively && shader_count > 1) { unsigned first = ordered_shaders[shader_count - 1]->info.stage; @@ -2923,7 +2923,7 @@ radv_link_shaders(struct radv_pipeline *pipeline, if (progress) { if (nir_lower_global_vars_to_local(ordered_shaders[i])) { ac_nir_lower_indirect_derefs(ordered_shaders[i], - pipeline->device->physical_device->rad_info.chip_class); + pipeline->device->physical_device->rad_info.gfx_level); /* remove dead writes, which can remove input loads */ nir_lower_vars_to_ssa(ordered_shaders[i]); nir_opt_dce(ordered_shaders[i]); @@ -2931,7 +2931,7 @@ radv_link_shaders(struct radv_pipeline *pipeline, if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) { ac_nir_lower_indirect_derefs(ordered_shaders[i - 1], - pipeline->device->physical_device->rad_info.chip_class); + pipeline->device->physical_device->rad_info.gfx_level); } } } @@ -2991,7 +2991,7 @@ radv_set_driver_locations(struct radv_pipeline *pipeline, struct radv_pipeline_s unsigned vs_info_idx = MESA_SHADER_VERTEX; unsigned tes_info_idx = MESA_SHADER_TESS_EVAL; - if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) { /* These are merged into the next stage */ vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY; tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL; @@ -3059,10 +3059,10 @@ radv_generate_pipeline_key(const struct radv_pipeline *pipeline, VkPipelineCreat key.optimisations_disabled = 1; key.disable_aniso_single_level = device->instance->disable_aniso_single_level && - device->physical_device->rad_info.chip_class < GFX8; + device->physical_device->rad_info.gfx_level < GFX8; key.image_2d_view_of_3d = device->image_2d_view_of_3d && - device->physical_device->rad_info.chip_class == GFX9; + device->physical_device->rad_info.gfx_level == GFX9; return key; } @@ -3119,17 +3119,17 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline, key.ps.col_format = blend->spi_shader_col_format; key.ps.cb_target_mask = blend->cb_target_mask; key.ps.mrt0_is_dual_src = blend->mrt0_is_dual_src; - if (pipeline->device->physical_device->rad_info.chip_class < GFX8) { + if (pipeline->device->physical_device->rad_info.gfx_level < GFX8) { key.ps.is_int8 = blend->col_format_is_int8; key.ps.is_int10 = blend->col_format_is_int10; } - if (pipeline->device->physical_device->rad_info.chip_class >= GFX11) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX11) { key.ps.alpha_to_coverage_via_mrtz = G_028B70_ALPHA_TO_MASK_ENABLE(blend->db_alpha_to_mask); } key.vs.topology = vi_info->primitive_topology; - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { const VkPipelineRasterizationStateCreateInfo *raster_info = pCreateInfo->pRasterizationState; const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT *provoking_vtx_info = vk_find_struct_const(raster_info->pNext, @@ -3348,7 +3348,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, filled_stages |= (1 << MESA_SHADER_FRAGMENT); } - if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 && + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) { struct nir_shader *combined_nir[] = {stages[MESA_SHADER_VERTEX].nir, stages[MESA_SHADER_TESS_CTRL].nir}; @@ -3366,7 +3366,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline, filled_stages |= (1 << MESA_SHADER_TESS_CTRL); } - if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 && + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) { gl_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; @@ -3453,7 +3453,7 @@ static void radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stage *stages, const struct radv_pipeline_key *pipeline_key) { - enum chip_class chip_class = device->physical_device->rad_info.chip_class; + enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; unsigned active_stages = 0; for (int i = 0; i < MESA_VULKAN_SHADER_STAGES; i++) { @@ -3468,8 +3468,8 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag stages[i].args.load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr; } - if (chip_class >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) { - radv_declare_shader_args(chip_class, pipeline_key, &stages[MESA_SHADER_TESS_CTRL].info, + if (gfx_level >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) { + radv_declare_shader_args(gfx_level, pipeline_key, &stages[MESA_SHADER_TESS_CTRL].info, MESA_SHADER_TESS_CTRL, true, MESA_SHADER_VERTEX, &stages[MESA_SHADER_TESS_CTRL].args); stages[MESA_SHADER_TESS_CTRL].info.user_sgprs_locs = stages[MESA_SHADER_TESS_CTRL].args.user_sgprs_locs; @@ -3481,11 +3481,12 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag active_stages &= ~(1 << MESA_SHADER_TESS_CTRL); } - if (chip_class >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) { + if (gfx_level >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) { gl_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; - radv_declare_shader_args(chip_class, pipeline_key, &stages[MESA_SHADER_GEOMETRY].info, - MESA_SHADER_GEOMETRY, true, pre_stage, &stages[MESA_SHADER_GEOMETRY].args); + radv_declare_shader_args(gfx_level, pipeline_key, &stages[MESA_SHADER_GEOMETRY].info, + MESA_SHADER_GEOMETRY, true, pre_stage, + &stages[MESA_SHADER_GEOMETRY].args); stages[MESA_SHADER_GEOMETRY].info.user_sgprs_locs = stages[MESA_SHADER_GEOMETRY].args.user_sgprs_locs; stages[MESA_SHADER_GEOMETRY].info.inline_push_constant_mask = stages[MESA_SHADER_GEOMETRY].args.ac.inline_push_const_mask; @@ -3496,8 +3497,8 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag } u_foreach_bit(i, active_stages) { - radv_declare_shader_args(chip_class, pipeline_key, &stages[i].info, i, false, MESA_SHADER_VERTEX, - &stages[i].args); + radv_declare_shader_args(gfx_level, pipeline_key, &stages[i].info, i, false, + MESA_SHADER_VERTEX, &stages[i].args); stages[i].info.user_sgprs_locs = stages[i].args.user_sgprs_locs; stages[i].info.inline_push_constant_mask = stages[i].args.ac.inline_push_const_mask; } @@ -3572,12 +3573,13 @@ gather_tess_info(struct radv_device *device, struct radv_pipeline_stage *stages, tess_in_patch_size, tess_out_patch_size, stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_inputs, stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_outputs, - stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_patch_outputs, device->hs.tess_offchip_block_dw_size, - device->physical_device->rad_info.chip_class, device->physical_device->rad_info.family); + stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_patch_outputs, + device->hs.tess_offchip_block_dw_size, device->physical_device->rad_info.gfx_level, + device->physical_device->rad_info.family); /* LDS size used by VS+TCS for storing TCS inputs and outputs. */ unsigned tcs_lds_size = calculate_tess_lds_size( - device->physical_device->rad_info.chip_class, tess_in_patch_size, tess_out_patch_size, + device->physical_device->rad_info.gfx_level, tess_in_patch_size, tess_out_patch_size, stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_inputs, num_patches, stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_outputs, stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_patch_outputs); @@ -3608,7 +3610,7 @@ gather_tess_info(struct radv_device *device, struct radv_pipeline_stage *stages, * doesn't handle a instruction dominating another with a different mode. */ stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq = - device->physical_device->rad_info.chip_class >= GFX9 && + device->physical_device->rad_info.gfx_level >= GFX9 && tess_in_patch_size == tess_out_patch_size && stages[MESA_SHADER_VERTEX].nir->info.float_controls_execution_mode == stages[MESA_SHADER_TESS_CTRL].nir->info.float_controls_execution_mode; @@ -3629,9 +3631,8 @@ gather_tess_info(struct radv_device *device, struct radv_pipeline_stage *stages, for (gl_shader_stage s = MESA_SHADER_VERTEX; s <= MESA_SHADER_TESS_CTRL; ++s) stages[s].info.workgroup_size = - ac_compute_lshs_workgroup_size( - device->physical_device->rad_info.chip_class, s, - num_patches, tess_in_patch_size, tess_out_patch_size); + ac_compute_lshs_workgroup_size(device->physical_device->rad_info.gfx_level, s, num_patches, + tess_in_patch_size, tess_out_patch_size); } static bool @@ -3702,7 +3703,7 @@ static unsigned lower_bit_size_callback(const nir_instr *instr, void *_) { struct radv_device *device = _; - enum chip_class chip = device->physical_device->rad_info.chip_class; + enum amd_gfx_level chip = device->physical_device->rad_info.gfx_level; if (instr->type != nir_instr_type_alu) return 0; @@ -4450,7 +4451,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout /* On GFX6, read2/write2 is out-of-bounds if the offset register is negative, even if * the final offset is not. */ - .has_shared2_amd = device->physical_device->rad_info.chip_class >= GFX7, + .has_shared2_amd = device->physical_device->rad_info.gfx_level >= GFX7, }; if (device->robust_buffer_access2) { @@ -4467,7 +4468,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout } struct radv_shader_info *info = &stages[i].info; - if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) { if (i == MESA_SHADER_VERTEX && stages[MESA_SHADER_TESS_CTRL].nir) info = &stages[MESA_SHADER_TESS_CTRL].info; else if (i == MESA_SHADER_VERTEX && stages[MESA_SHADER_GEOMETRY].nir) @@ -4491,7 +4492,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout nir_lower_idiv(stages[i].nir, &(nir_lower_idiv_options){ .imprecise_32bit_lowering = false, - .allow_fp16 = device->physical_device->rad_info.chip_class >= GFX9, + .allow_fp16 = device->physical_device->rad_info.gfx_level >= GFX9, }); nir_move_options sink_opts = nir_move_const_undef | nir_move_copies; @@ -4509,13 +4510,13 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout radv_lower_ngg(device, &stages[i], pipeline_key); ac_nir_lower_global_access(stages[i].nir); - radv_nir_lower_abi(stages[i].nir, device->physical_device->rad_info.chip_class, + radv_nir_lower_abi(stages[i].nir, device->physical_device->rad_info.gfx_level, &stages[i].info, &stages[i].args, pipeline_key); radv_optimize_nir_algebraic( stages[i].nir, io_to_mem || lowered_ngg || i == MESA_SHADER_COMPUTE || i == MESA_SHADER_TASK); if (stages[i].nir->info.bit_sizes_int & (8 | 16)) { - if (device->physical_device->rad_info.chip_class >= GFX8) { + if (device->physical_device->rad_info.gfx_level >= GFX8) { nir_convert_to_lcssa(stages[i].nir, true, true); nir_divergence_analysis(stages[i].nir); } @@ -4525,11 +4526,11 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout NIR_PASS_V(stages[i].nir, nir_opt_dce); } - if (device->physical_device->rad_info.chip_class >= GFX8) + if (device->physical_device->rad_info.gfx_level >= GFX8) nir_opt_remove_phis(stages[i].nir); /* cleanup LCSSA phis */ } if (((stages[i].nir->info.bit_sizes_int | stages[i].nir->info.bit_sizes_float) & 16) && - device->physical_device->rad_info.chip_class >= GFX9) { + device->physical_device->rad_info.gfx_level >= GFX9) { bool copy_prop = false; uint32_t sampler_dims = UINT32_MAX; /* Skip because AMD doesn't support 16-bit types with these. */ @@ -4547,7 +4548,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout NIR_PASS_V(stages[i].nir, nir_opt_vectorize, opt_vectorize_callback, NULL); - } + } /* cleanup passes */ nir_lower_load_const_to_scalar(stages[i].nir); @@ -4585,7 +4586,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout struct radv_shader_args gs_copy_args = {0}; gs_copy_args.is_gs_copy_shader = true; gs_copy_args.explicit_scratch_args = !radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX); - radv_declare_shader_args(device->physical_device->rad_info.chip_class, pipeline_key, &info, + radv_declare_shader_args(device->physical_device->rad_info.gfx_level, pipeline_key, &info, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX, &gs_copy_args); info.user_sgprs_locs = gs_copy_args.user_sgprs_locs; info.inline_push_constant_mask = gs_copy_args.ac.inline_push_const_mask; @@ -4615,7 +4616,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout active_stages &= ~(1 << MESA_SHADER_FRAGMENT); } - if (device->physical_device->rad_info.chip_class >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) { + if (device->physical_device->rad_info.gfx_level >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) { if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) { struct nir_shader *combined_nir[] = {stages[MESA_SHADER_VERTEX].nir, stages[MESA_SHADER_TESS_CTRL].nir}; int64_t stage_start = os_time_get_nano(); @@ -4631,7 +4632,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout active_stages &= ~(1 << MESA_SHADER_TESS_CTRL); } - if (device->physical_device->rad_info.chip_class >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) { + if (device->physical_device->rad_info.gfx_level >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) { gl_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) { @@ -4731,7 +4732,7 @@ done: static uint32_t radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline, gl_shader_stage stage, - enum chip_class chip_class) + enum amd_gfx_level gfx_level) { bool has_gs = radv_pipeline_has_gs(pipeline); bool has_tess = radv_pipeline_has_tess(pipeline); @@ -4742,9 +4743,9 @@ radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline, gl_shader_sta return R_00B030_SPI_SHADER_USER_DATA_PS_0; case MESA_SHADER_VERTEX: if (has_tess) { - if (chip_class >= GFX10) { + if (gfx_level >= GFX10) { return R_00B430_SPI_SHADER_USER_DATA_HS_0; - } else if (chip_class == GFX9) { + } else if (gfx_level == GFX9) { return R_00B430_SPI_SHADER_USER_DATA_LS_0; } else { return R_00B530_SPI_SHADER_USER_DATA_LS_0; @@ -4752,7 +4753,7 @@ radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline, gl_shader_sta } if (has_gs) { - if (chip_class >= GFX10) { + if (gfx_level >= GFX10) { return R_00B230_SPI_SHADER_USER_DATA_GS_0; } else { return R_00B330_SPI_SHADER_USER_DATA_ES_0; @@ -4764,18 +4765,18 @@ radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline, gl_shader_sta return R_00B130_SPI_SHADER_USER_DATA_VS_0; case MESA_SHADER_GEOMETRY: - return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 - : R_00B230_SPI_SHADER_USER_DATA_GS_0; + return gfx_level == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 + : R_00B230_SPI_SHADER_USER_DATA_GS_0; case MESA_SHADER_COMPUTE: case MESA_SHADER_TASK: return R_00B900_COMPUTE_USER_DATA_0; case MESA_SHADER_TESS_CTRL: - return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 - : R_00B430_SPI_SHADER_USER_DATA_HS_0; + return gfx_level == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 + : R_00B430_SPI_SHADER_USER_DATA_HS_0; case MESA_SHADER_TESS_EVAL: if (has_gs) { - return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 - : R_00B330_SPI_SHADER_USER_DATA_ES_0; + return gfx_level >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 + : R_00B330_SPI_SHADER_USER_DATA_ES_0; } else if (has_ngg) { return R_00B230_SPI_SHADER_USER_DATA_GS_0; } else { @@ -5168,7 +5169,7 @@ radv_pipeline_init_disabled_binning_state(struct radv_pipeline *pipeline, uint32_t pa_sc_binner_cntl_0 = S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) | S_028C44_DISABLE_START_OF_PRIM(1); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { const VkPipelineRenderingCreateInfo *render_create_info = vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO); const VkPipelineColorBlendStateCreateInfo *vkblend = @@ -5232,13 +5233,13 @@ radv_pipeline_init_binning_state(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo, const struct radv_blend_state *blend) { - if (pipeline->device->physical_device->rad_info.chip_class < GFX9) + if (pipeline->device->physical_device->rad_info.gfx_level < GFX9) return; VkExtent2D bin_size; - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo); - } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) { + } else if (pipeline->device->physical_device->rad_info.gfx_level == GFX9) { bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo); } else unreachable("Unhandled generation for binning bin size calculation"); @@ -5302,7 +5303,7 @@ radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs, const VkConservativeRasterizationModeEXT mode = radv_get_conservative_raster_mode(vkraster); uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) { /* Conservative rasterization. */ if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) { pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) | S_028C4C_POSTZ_AA_MASK_ENABLE(1) | @@ -5348,7 +5349,7 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs, * if no sample lies on the pixel boundary (-8 sample offset). It's * currently always TRUE because the driver doesn't support 16 samples. */ - bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7; + bool exclusion = pipeline->device->physical_device->rad_info.gfx_level >= GFX7; radeon_set_context_reg( ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion)); @@ -5372,7 +5373,7 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs, const struct radv_shader *gs = pipeline->shaders[MESA_SHADER_GEOMETRY]; vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out, - pipeline->device->physical_device->rad_info.chip_class); + pipeline->device->physical_device->rad_info.gfx_level); } else if (outinfo->export_prim_id || vs->info.uses_prim_id) { vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A); vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1); @@ -5409,7 +5410,7 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf nparams = MAX2(outinfo->param_exports, 1); spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0); } @@ -5436,15 +5437,15 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) | total_mask << 8 | clip_dist_mask); - if (pipeline->device->physical_device->rad_info.chip_class <= GFX8) + if (pipeline->device->physical_device->rad_info.gfx_level <= GFX8) radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, outinfo->writes_viewport_index); unsigned late_alloc_wave64, cu_mask; ac_compute_late_alloc(&pipeline->device->physical_device->rad_info, false, false, shader->config.scratch_bytes_per_wave > 0, &late_alloc_wave64, &cu_mask); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) { - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX7) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { ac_set_reg_cu_en(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(cu_mask) | S_00B118_WAVE_LIMIT(0x3F), C_00B118_CU_EN, 0, &pipeline->device->physical_device->rad_info, @@ -5455,9 +5456,10 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf } radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(late_alloc_wave64)); } - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { uint32_t oversub_pc_lines = late_alloc_wave64 ? pipeline->device->physical_device->rad_info.pc_lines / 4 : 0; - gfx10_emit_ge_pc_alloc(cs, pipeline->device->physical_device->rad_info.chip_class, oversub_pc_lines); + gfx10_emit_ge_pc_alloc(cs, pipeline->device->physical_device->rad_info.gfx_level, + oversub_pc_lines); } } @@ -5485,7 +5487,7 @@ radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs, const struct radv_pipelin radeon_set_sh_reg(cs, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); rsrc2 |= S_00B52C_LDS_SIZE(num_lds_blocks); - if (pipeline->device->physical_device->rad_info.chip_class == GFX7 && + if (pipeline->device->physical_device->rad_info.gfx_level == GFX7 && pipeline->device->physical_device->rad_info.family != CHIP_HAWAII) radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2); @@ -5604,7 +5606,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf * * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5 */ - if (pipeline->device->physical_device->rad_info.chip_class == GFX10 && + if (pipeline->device->physical_device->rad_info.gfx_level == GFX10 && !radv_pipeline_has_tess(pipeline) && ngg_state->hw_max_esverts != 256) { ge_cntl &= C_03096C_VERT_GRP_SIZE; @@ -5619,7 +5621,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf ac_compute_late_alloc(&pipeline->device->physical_device->rad_info, true, shader->info.has_ngg_culling, shader->config.scratch_bytes_per_wave > 0, &late_alloc_wave64, &cu_mask); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { ac_set_reg_cu_en(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(cu_mask) | S_00B21C_WAVE_LIMIT(0x3F), C_00B21C_CU_EN, 0, &pipeline->device->physical_device->rad_info, @@ -5649,7 +5651,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf oversub_pc_lines *= oversub_factor; } - gfx10_emit_ge_pc_alloc(cs, pipeline->device->physical_device->rad_info.chip_class, oversub_pc_lines); + gfx10_emit_ge_pc_alloc(cs, pipeline->device->physical_device->rad_info.gfx_level, + oversub_pc_lines); } static void @@ -5658,8 +5661,8 @@ radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs, const struct radv_pipelin { uint64_t va = radv_shader_get_va(shader); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { radeon_set_sh_reg(cs, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); } else { radeon_set_sh_reg(cs, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8); @@ -5718,7 +5721,7 @@ radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs, struct radeon_ radv_pipeline_generate_hw_hs(cs, pipeline, tcs); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10 && !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) { radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, S_028A44_ES_VERTS_PER_SUBGRP(250) | S_028A44_GS_PRIMS_PER_SUBGRP(126) | @@ -5744,7 +5747,7 @@ radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs, ls_hs_config = S_028B58_NUM_PATCHES(num_patches) | S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) | S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX7) { radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config); } else { radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config); @@ -5857,8 +5860,8 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf va = radv_shader_get_va(gs); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { radeon_set_sh_reg(cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); } else { radeon_set_sh_reg(cs, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8); @@ -5879,7 +5882,7 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf radeon_emit(cs, gs->config.rsrc2); } - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { ac_set_reg_cu_en(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F), C_00B21C_CU_EN, 0, &pipeline->device->physical_device->rad_info, @@ -5888,12 +5891,12 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0), C_00B204_CU_EN_GFX10, 16, &pipeline->device->physical_device->rad_info, (void*)gfx10_set_sh_reg_idx3); - } else if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) { + } else if (pipeline->device->physical_device->rad_info.gfx_level >= GFX7) { radeon_set_sh_reg_idx( pipeline->device->physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, 3, S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F)); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { radeon_set_sh_reg_idx( pipeline->device->physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, 3, S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0)); @@ -6145,7 +6148,7 @@ radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs, const struct radv_pipeline *pipeline) { if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 || - pipeline->device->physical_device->rad_info.chip_class >= GFX10) + pipeline->device->physical_device->rad_info.gfx_level >= GFX10) return; unsigned vtx_reuse_depth = 30; @@ -6191,10 +6194,10 @@ radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf *ctx_cs, stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); } - if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) { uint8_t hs_size = 64, gs_size = 64, vs_size = 64; if (radv_pipeline_has_tess(pipeline)) @@ -6414,11 +6417,11 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo); radv_pipeline_generate_vgt_gs_out(ctx_cs, pipeline, vgt_gs_out_prim_type); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10 && !radv_pipeline_has_ngg(pipeline)) gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) { + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10_3) { gfx103_pipeline_generate_vgt_draw_payload_cntl(ctx_cs, pipeline, pCreateInfo); gfx103_pipeline_generate_vrs_state(ctx_cs, pipeline, pCreateInfo); } @@ -6501,7 +6504,7 @@ radv_pipeline_init_shader_stages_state(struct radv_pipeline *pipeline) if (shader_exists || i < MESA_SHADER_COMPUTE) { /* We need this info for some stages even when the shader doesn't exist. */ pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0( - pipeline, i, device->physical_device->rad_info.chip_class); + pipeline, i, device->physical_device->rad_info.gfx_level); if (shader_exists) pipeline->need_indirect_descriptor_sets |= @@ -6663,7 +6666,7 @@ radv_graphics_pipeline_init(struct radv_pipeline *pipeline, struct radv_device * struct radv_depth_stencil_state ds_state = radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10_3) gfx103_pipeline_init_vrs_state(pipeline, pCreateInfo); /* Ensure that some export memory is always allocated, for two reasons: @@ -6682,8 +6685,7 @@ radv_graphics_pipeline_init(struct radv_pipeline *pipeline, struct radv_device * * instructions if any are present. */ struct radv_shader *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; - if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 || - ps->info.ps.can_discard) && + if ((pipeline->device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard) && !blend.spi_shader_col_format) { if (!ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask) blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; @@ -6867,7 +6869,7 @@ radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs, const struct radv_pipelin radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2); radeon_emit(cs, shader->config.rsrc1); radeon_emit(cs, shader->config.rsrc2); - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3); } } @@ -6887,7 +6889,7 @@ radv_pipeline_generate_compute_state(struct radeon_cmdbuf *cs, const struct radv shader->info.cs.block_size[0] * shader->info.cs.block_size[1] * shader->info.cs.block_size[2]; waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup, shader->info.wave_size); - if (device->physical_device->rad_info.chip_class >= GFX10 && waves_per_threadgroup == 1) + if (device->physical_device->rad_info.gfx_level >= GFX10 && waves_per_threadgroup == 1) threadgroups_per_cu = 2; radeon_set_sh_reg( @@ -6907,7 +6909,7 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline) struct radv_device *device = pipeline->device; struct radeon_cmdbuf *cs = &pipeline->cs; - cs->max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 19 : 16; + cs->max_dw = device->physical_device->rad_info.gfx_level >= GFX10 ? 19 : 16; cs->buf = malloc(cs->max_dw * 4); radv_pipeline_generate_hw_cs(cs, pipeline); @@ -6979,7 +6981,7 @@ radv_compute_pipeline_create(VkDevice _device, VkPipelineCache _cache, } pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0( - pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class); + pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.gfx_level); pipeline->need_indirect_descriptor_sets |= radv_shader_need_indirect_descriptor_sets(pipeline, MESA_SHADER_COMPUTE); radv_pipeline_init_scratch(device, pipeline); @@ -7184,8 +7186,8 @@ radv_GetPipelineExecutableStatisticsKHR(VkDevice _device, struct radv_shader *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage); - enum chip_class chip_class = device->physical_device->rad_info.chip_class; - unsigned lds_increment = chip_class >= GFX7 ? 512 : 256; + enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; + unsigned lds_increment = gfx_level >= GFX7 ? 512 : 256; unsigned max_waves = radv_get_max_waves(device, shader, stage); VkPipelineExecutableStatisticKHR *s = pStatistics; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 6df9f16c75d..9c65d5b1ff6 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1598,14 +1598,14 @@ uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool inst bool indirect_draw, bool count_from_stream_output, uint32_t draw_vertex_count, unsigned topology, bool prim_restart_enable); -void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, bool is_mec, +void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec, unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, uint32_t new_fence, uint64_t gfx9_eop_bug_va); void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va, uint32_t ref, uint32_t mask); -void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, +void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *fence_ptr, uint64_t va, bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va); @@ -2283,7 +2283,7 @@ radv_image_is_tc_compat_htile(const struct radv_image *image) static inline bool radv_image_tile_stencil_disabled(const struct radv_device *device, const struct radv_image *image) { - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { return !vk_format_has_stencil(image->vk_format) && !radv_image_has_vrs_htile(device, image); } else { /* Due to a hw bug, TILE_STENCIL_DISABLE must be set to 0 for @@ -2392,11 +2392,10 @@ static inline bool radv_image_get_iterate256(struct radv_device *device, struct radv_image *image) { /* ITERATE_256 is required for depth or stencil MSAA images that are TC-compatible HTILE. */ - return device->physical_device->rad_info.chip_class >= GFX10 && - (image->usage & (VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT | - VK_IMAGE_USAGE_TRANSFER_DST_BIT)) && - radv_image_is_tc_compat_htile(image) && - image->info.samples > 1; + return device->physical_device->rad_info.gfx_level >= GFX10 && + (image->usage & + (VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT)) && + radv_image_is_tc_compat_htile(image) && image->info.samples > 1; } unsigned radv_image_queue_family_mask(const struct radv_image *image, @@ -2968,8 +2967,8 @@ radv_use_llvm_for_stage(struct radv_device *device, UNUSED gl_shader_stage stage static inline bool radv_has_shader_buffer_float_minmax(const struct radv_physical_device *pdevice) { - return (pdevice->rad_info.chip_class <= GFX7 && !pdevice->use_llvm) || - pdevice->rad_info.chip_class >= GFX10; + return (pdevice->rad_info.gfx_level <= GFX7 && !pdevice->use_llvm) || + pdevice->rad_info.gfx_level >= GFX10; } struct radv_acceleration_structure { diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index a7ac7a83136..91525be8305 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1540,7 +1540,7 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, radeon_emit(cs, va); radeon_emit(cs, va >> 32); - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class, + si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, radv_cmd_buffer_uses_mec(cmd_buffer), V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, avail_va, 1, cmd_buffer->gfx9_eop_bug_va); @@ -1580,7 +1580,7 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_INV_VCACHE; - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB; } @@ -1681,7 +1681,7 @@ radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 sta radeon_emit(cs, query_va); radeon_emit(cs, query_va >> 32); } else { - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class, + si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, mec, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_TIMESTAMP, query_va, 0, cmd_buffer->gfx9_eop_bug_va); @@ -1692,7 +1692,7 @@ radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 sta cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_INV_VCACHE; - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB; } diff --git a/src/amd/vulkan/radv_rt_common.c b/src/amd/vulkan/radv_rt_common.c index e12bb300d66..47172766e1a 100644 --- a/src/amd/vulkan/radv_rt_common.c +++ b/src/amd/vulkan/radv_rt_common.c @@ -35,7 +35,7 @@ bool radv_emulate_rt(const struct radv_physical_device *pdevice) { assert(radv_enable_rt(pdevice)); - return pdevice->rad_info.chip_class < GFX10_3 || + return pdevice->rad_info.gfx_level < GFX10_3 || (pdevice->instance->perftest_flags & RADV_PERFTEST_FORCE_EMULATE_RT); } @@ -348,7 +348,7 @@ build_node_to_addr(struct radv_device *device, nir_builder *b, nir_ssa_def *node addr = nir_ishl_imm(b, addr, 3); /* Assumes everything is in the top half of address space, which is true in * GFX9+ for now. */ - return device->physical_device->rad_info.chip_class >= GFX9 + return device->physical_device->rad_info.gfx_level >= GFX9 ? nir_ior_imm(b, addr, 0xffffull << 48) : addr; } diff --git a/src/amd/vulkan/radv_sdma_copy_image.c b/src/amd/vulkan/radv_sdma_copy_image.c index 9a86e76ab97..639f5d90149 100644 --- a/src/amd/vulkan/radv_sdma_copy_image.c +++ b/src/amd/vulkan/radv_sdma_copy_image.c @@ -121,7 +121,7 @@ radv_sdma_v4_v5_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct unsigned linear_slice_pitch = region->bufferRowLength * copy_height; uint64_t tiled_address = src_address; uint64_t linear_address = dst_address; - bool is_v5 = device->physical_device->rad_info.chip_class >= GFX10; + bool is_v5 = device->physical_device->rad_info.gfx_level >= GFX10; /* Only SDMA 5 supports DCC with SDMA */ bool dcc = radv_dcc_enabled(image, 0) && is_v5; @@ -191,6 +191,6 @@ bool radv_sdma_copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, struct radv_buffer *buffer, const VkBufferImageCopy2 *region) { - assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9); + assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9); return radv_sdma_v4_v5_copy_image_to_buffer(cmd_buffer, image, buffer, region); } diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 4b538188141..b871d44875a 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -79,13 +79,13 @@ get_nir_options_for_stage(struct radv_physical_device *device, gl_shader_stage s .lower_unpack_unorm_2x16 = true, .lower_unpack_unorm_4x8 = true, .lower_unpack_half_2x16 = true, - .lower_ffma16 = split_fma || device->rad_info.chip_class < GFX9, - .lower_ffma32 = split_fma || device->rad_info.chip_class < GFX10_3, + .lower_ffma16 = split_fma || device->rad_info.gfx_level < GFX9, + .lower_ffma32 = split_fma || device->rad_info.gfx_level < GFX10_3, .lower_ffma64 = split_fma, .lower_fpow = true, .lower_mul_2x32_64 = true, .lower_rotate = true, - .lower_iadd_sat = device->rad_info.chip_class <= GFX8, + .lower_iadd_sat = device->rad_info.gfx_level <= GFX8, .has_fsub = true, .has_isub = true, .has_sdot_4x8 = device->rad_info.has_accelerated_dot_product, @@ -654,7 +654,7 @@ radv_shader_compile_to_nir(struct radv_device *device, const struct radv_pipelin .variable_pointers = true, .vk_memory_model = true, .vk_memory_model_device_scope = true, - .fragment_shading_rate = device->physical_device->rad_info.chip_class >= GFX10_3, + .fragment_shading_rate = device->physical_device->rad_info.gfx_level >= GFX10_3, .workgroup_memory_explicit_layout = true, }, .ubo_addr_format = nir_address_format_vec2_index_32bit_offset, @@ -747,7 +747,7 @@ radv_shader_compile_to_nir(struct radv_device *device, const struct radv_pipelin nir_lower_doubles_options lower_doubles = nir->options->lower_doubles_options; - if (device->physical_device->rad_info.chip_class == GFX6) { + if (device->physical_device->rad_info.gfx_level == GFX6) { /* GFX6 doesn't support v_floor_f64 and the precision * of v_fract_f64 which is used to implement 64-bit * floor is less than what Vulkan requires. @@ -824,7 +824,7 @@ radv_shader_compile_to_nir(struct radv_device *device, const struct radv_pipelin nir_lower_global_vars_to_local(nir); nir_remove_dead_variables(nir, nir_var_function_temp, NULL); - bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7; + bool gfx7minus = device->physical_device->rad_info.gfx_level <= GFX7; nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options){ .subgroup_size = subgroup_size, .ballot_bit_size = ballot_bit_size, @@ -916,7 +916,7 @@ radv_shader_compile_to_nir(struct radv_device *device, const struct radv_pipelin * bloat the instruction count of the loop and cause it to be * considered too large for unrolling. */ - if (ac_nir_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class) && + if (ac_nir_lower_indirect_derefs(nir, device->physical_device->rad_info.gfx_level) && !key->optimisations_disabled && nir->info.stage != MESA_SHADER_COMPUTE) { /* Optimize the lowered code before the linking optimizations. */ radv_optimize_nir(nir, false, false); @@ -1023,14 +1023,14 @@ radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *sta info->vs.num_linked_outputs); return true; } else if (info->vs.as_es) { - ac_nir_lower_es_outputs_to_mem(nir, device->physical_device->rad_info.chip_class, + ac_nir_lower_es_outputs_to_mem(nir, device->physical_device->rad_info.gfx_level, info->vs.num_linked_outputs); return true; } } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) { ac_nir_lower_hs_inputs_to_mem(nir, info->vs.tcs_in_out_eq, info->tcs.num_linked_inputs); ac_nir_lower_hs_outputs_to_mem( - nir, device->physical_device->rad_info.chip_class, info->tcs.tes_reads_tess_factors, + nir, device->physical_device->rad_info.gfx_level, info->tcs.tes_reads_tess_factors, info->tcs.tes_inputs_read, info->tcs.tes_patch_inputs_read, info->tcs.num_linked_inputs, info->tcs.num_linked_outputs, info->tcs.num_linked_patch_outputs, true); @@ -1040,13 +1040,13 @@ radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *sta info->tes.num_linked_patch_inputs); if (info->tes.as_es) { - ac_nir_lower_es_outputs_to_mem(nir, device->physical_device->rad_info.chip_class, + ac_nir_lower_es_outputs_to_mem(nir, device->physical_device->rad_info.gfx_level, info->tes.num_linked_outputs); } return true; } else if (nir->info.stage == MESA_SHADER_GEOMETRY) { - ac_nir_lower_gs_inputs_to_mem(nir, device->physical_device->rad_info.chip_class, + ac_nir_lower_gs_inputs_to_mem(nir, device->physical_device->rad_info.gfx_level, info->gs.num_linked_inputs); return true; } else if (nir->info.stage == MESA_SHADER_TASK) { @@ -1484,7 +1484,7 @@ static bool radv_should_use_wgp_mode(const struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info) { - enum chip_class chip = device->physical_device->rad_info.chip_class; + enum amd_gfx_level chip = device->physical_device->rad_info.gfx_level; switch (stage) { case MESA_SHADER_COMPUTE: case MESA_SHADER_TESS_CTRL: @@ -1520,8 +1520,8 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader unsigned num_sgprs = MAX2(config_in->num_sgprs, args->ac.num_sgprs_used + 2 + 3); unsigned num_shared_vgprs = config_in->num_shared_vgprs; /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */ - assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0) || - (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0)); + assert((pdevice->rad_info.gfx_level >= GFX10 && num_shared_vgprs % 8 == 0) || + (pdevice->rad_info.gfx_level < GFX10 && num_shared_vgprs == 0)); unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8; unsigned excp_en = 0; @@ -1550,7 +1550,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / (info->wave_size == 32 ? 8 : 4)) | S_00B848_DX10_CLAMP(1) | S_00B848_FLOAT_MODE(config_out->float_mode); - if (pdevice->rad_info.chip_class >= GFX10) { + if (pdevice->rad_info.gfx_level >= GFX10) { config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(args->num_user_sgprs >> 5); } else { config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8); @@ -1562,10 +1562,10 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader switch (stage) { case MESA_SHADER_TESS_EVAL: if (info->is_ngg) { - config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); + config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1) | S_00B22C_EXCP_EN(excp_en); } else if (info->tes.as_es) { - assert(pdevice->rad_info.chip_class <= GFX8); + assert(pdevice->rad_info.gfx_level <= GFX8); vgpr_comp_cnt = info->uses_prim_id ? 3 : 2; config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en); @@ -1573,21 +1573,21 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader bool enable_prim_id = info->tes.outinfo.export_prim_id || info->uses_prim_id; vgpr_comp_cnt = enable_prim_id ? 3 : 2; - config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); + config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en); } config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks); break; case MESA_SHADER_TESS_CTRL: - if (pdevice->rad_info.chip_class >= GFX9) { + if (pdevice->rad_info.gfx_level >= GFX9) { /* We need at least 2 components for LS. * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID). * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded. */ - if (pdevice->rad_info.chip_class >= GFX10) { + if (pdevice->rad_info.gfx_level >= GFX10) { if (info->vs.needs_instance_id) { vgpr_comp_cnt = 3; - } else if (pdevice->rad_info.chip_class <= GFX10_3) { + } else if (pdevice->rad_info.gfx_level <= GFX10_3) { vgpr_comp_cnt = 1; } config_out->rsrc2 |= @@ -1601,21 +1601,21 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en); } config_out->rsrc1 |= - S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) | S_00B428_WGP_MODE(wgp_mode); + S_00B428_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10) | S_00B428_WGP_MODE(wgp_mode); config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks); break; case MESA_SHADER_VERTEX: if (info->is_ngg) { - config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); + config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); } else if (info->vs.as_ls) { - assert(pdevice->rad_info.chip_class <= GFX8); + assert(pdevice->rad_info.gfx_level <= GFX8); /* We need at least 2 components for LS. * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID). * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded. */ vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1; } else if (info->vs.as_es) { - assert(pdevice->rad_info.chip_class <= GFX8); + assert(pdevice->rad_info.gfx_level <= GFX8); /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */ vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0; } else { @@ -1623,7 +1623,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader * If PrimID is disabled. InstanceID / StepRate1 is loaded instead. * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded. */ - if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) { + if (info->vs.needs_instance_id && pdevice->rad_info.gfx_level >= GFX10) { vgpr_comp_cnt = 3; } else if (info->vs.outinfo.export_prim_id) { vgpr_comp_cnt = 2; @@ -1633,7 +1633,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader vgpr_comp_cnt = 0; } - config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); + config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); } config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) | S_00B12C_EXCP_EN(excp_en); @@ -1644,19 +1644,19 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) | S_00B12C_EXCP_EN(excp_en); break; case MESA_SHADER_FRAGMENT: - config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); + config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) | S_00B02C_EXCP_EN(excp_en); break; case MESA_SHADER_GEOMETRY: - config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); + config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) | S_00B22C_EXCP_EN(excp_en); break; case MESA_SHADER_COMPUTE: case MESA_SHADER_TASK: config_out->rsrc1 |= - S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) | S_00B848_WGP_MODE(wgp_mode); + S_00B848_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10) | S_00B848_WGP_MODE(wgp_mode); config_out->rsrc2 |= S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) | S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) | S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) | @@ -1673,7 +1673,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader break; } - if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg && + if (pdevice->rad_info.gfx_level >= GFX10 && info->is_ngg && (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY || stage == MESA_SHADER_MESH)) { unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt; @@ -1727,14 +1727,14 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | S_00B22C_LDS_SIZE(config_in->lds_size) | S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL); - } else if (pdevice->rad_info.chip_class >= GFX9 && stage == MESA_SHADER_GEOMETRY) { + } else if (pdevice->rad_info.gfx_level >= GFX9 && stage == MESA_SHADER_GEOMETRY) { unsigned es_type = info->gs.es_type; unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt; if (es_type == MESA_SHADER_VERTEX) { /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */ if (info->vs.needs_instance_id) { - es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1; + es_vgpr_comp_cnt = pdevice->rad_info.gfx_level >= GFX10 ? 3 : 1; } else { es_vgpr_comp_cnt = 0; } @@ -1761,7 +1761,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) | S_00B228_WGP_MODE(wgp_mode); config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL); - } else if (pdevice->rad_info.chip_class >= GFX9 && stage == MESA_SHADER_TESS_CTRL) { + } else if (pdevice->rad_info.gfx_level >= GFX9 && stage == MESA_SHADER_TESS_CTRL) { config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt); } else { config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt); @@ -1777,9 +1777,9 @@ radv_open_rtld_binary(struct radv_device *device, const struct radv_shader *shad struct ac_rtld_symbol lds_symbols[2]; unsigned num_lds_symbols = 0; - if (device->physical_device->rad_info.chip_class >= GFX9 && + if (device->physical_device->rad_info.gfx_level >= GFX9 && (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) && - !binary->is_gs_copy_shader) { + !binary->is_gs_copy_shader) { struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++]; sym->name = "esgs_ring"; sym->size = binary->info.ngg_info.esgs_ring_size; @@ -1986,7 +1986,7 @@ shader_compile(struct radv_device *device, struct nir_shader *const *shaders, in }; options->family = chip_family; - options->chip_class = device->physical_device->rad_info.chip_class; + options->gfx_level = device->physical_device->rad_info.gfx_level; options->info = &device->physical_device->rad_info; options->dump_shader = radv_can_dump_shader(device, shaders[0], gs_copy_shader || trap_handler_shader); options->dump_preoptir = @@ -2100,7 +2100,7 @@ radv_create_trap_handler_shader(struct radv_device *device) struct radv_shader_args args; args.explicit_scratch_args = true; args.is_trap_handler_shader = true; - radv_declare_shader_args(device->physical_device->rad_info.chip_class, &key, &info, + radv_declare_shader_args(device->physical_device->rad_info.gfx_level, &key, &info, MESA_SHADER_COMPUTE, false, MESA_SHADER_VERTEX, &args); shader = shader_compile(device, &b.shader, 1, MESA_SHADER_COMPUTE, &info, &args, &options, @@ -2174,7 +2174,7 @@ radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_ke struct radv_shader_args args = {0}; struct radv_nir_compiler_options options = {0}; options.family = device->physical_device->rad_info.family; - options.chip_class = device->physical_device->rad_info.chip_class; + options.gfx_level = device->physical_device->rad_info.gfx_level; options.info = &device->physical_device->rad_info; options.address32_hi = device->physical_device->rad_info.address32_hi; options.dump_shader = device->instance->debug_flags & RADV_DEBUG_DUMP_PROLOGS; @@ -2194,7 +2194,7 @@ radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_ke struct radv_pipeline_key pipeline_key = {0}; args.explicit_scratch_args = true; - radv_declare_shader_args(options.chip_class, &pipeline_key, &info, key->next_stage, + radv_declare_shader_args(options.gfx_level, &pipeline_key, &info, key->next_stage, key->next_stage != MESA_SHADER_VERTEX, MESA_SHADER_VERTEX, &args); info.user_sgprs_locs = args.user_sgprs_locs; @@ -2338,7 +2338,7 @@ radv_get_max_waves(const struct radv_device *device, struct radv_shader *shader, gl_shader_stage stage) { struct radeon_info *info = &device->physical_device->rad_info; - enum chip_class chip_class = info->chip_class; + enum amd_gfx_level gfx_level = info->gfx_level; uint8_t wave_size = shader->info.wave_size; struct ac_shader_config *conf = &shader->config; unsigned max_simd_waves; @@ -2357,28 +2357,28 @@ radv_get_max_waves(const struct radv_device *device, struct radv_shader *shader, lds_per_wave /= DIV_ROUND_UP(max_workgroup_size, wave_size); } - if (conf->num_sgprs && chip_class < GFX10) { - unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8); + if (conf->num_sgprs && gfx_level < GFX10) { + unsigned sgprs = align(conf->num_sgprs, gfx_level >= GFX8 ? 16 : 8); max_simd_waves = MIN2(max_simd_waves, info->num_physical_sgprs_per_simd / sgprs); } if (conf->num_vgprs) { unsigned physical_vgprs = info->num_physical_wave64_vgprs_per_simd * (64 / wave_size); unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4); - if (chip_class >= GFX10_3) + if (gfx_level >= GFX10_3) vgprs = align(vgprs, wave_size == 32 ? 16 : 8); max_simd_waves = MIN2(max_simd_waves, physical_vgprs / vgprs); } unsigned simd_per_workgroup = info->num_simd_per_compute_unit; - if (chip_class >= GFX10) + if (gfx_level >= GFX10) simd_per_workgroup *= 2; /* like lds_size_per_workgroup, assume WGP on GFX10+ */ unsigned max_lds_per_simd = info->lds_size_per_workgroup / simd_per_workgroup; if (lds_per_wave) max_simd_waves = MIN2(max_simd_waves, DIV_ROUND_UP(max_lds_per_simd, lds_per_wave)); - return chip_class >= GFX10 ? max_simd_waves * (wave_size / 32) : max_simd_waves; + return gfx_level >= GFX10 ? max_simd_waves * (wave_size / 32) : max_simd_waves; } unsigned diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 7f7a95e721b..787e5df67ea 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -129,7 +129,7 @@ struct radv_nir_compiler_options { uint8_t enable_mrt_output_nan_fixup; bool wgp_mode; enum radeon_family family; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; const struct radeon_info *info; uint32_t address32_hi; @@ -484,7 +484,7 @@ struct radv_shader { uint32_t exec_size; struct radv_shader_info info; - /* debug only */ + /* debug only */ char *spirv; uint32_t spirv_size; char *nir_string; @@ -528,9 +528,8 @@ nir_shader *radv_shader_compile_to_nir(struct radv_device *device, const struct radv_pipeline_stage *stage, const struct radv_pipeline_key *key); -void radv_nir_lower_abi(nir_shader *shader, enum chip_class chip_class, - const struct radv_shader_info *info, - const struct radv_shader_args *args, +void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, + const struct radv_shader_info *info, const struct radv_shader_args *args, const struct radv_pipeline_key *pl_key); void radv_init_shader_arenas(struct radv_device *device); @@ -601,7 +600,7 @@ VkResult radv_dump_shader_stats(struct radv_device *device, struct radv_pipeline gl_shader_stage stage, FILE *output); static inline unsigned -calculate_tess_lds_size(enum chip_class chip_class, unsigned tcs_num_input_vertices, +calculate_tess_lds_size(enum amd_gfx_level gfx_level, unsigned tcs_num_input_vertices, unsigned tcs_num_output_vertices, unsigned tcs_num_inputs, unsigned tcs_num_patches, unsigned tcs_num_outputs, unsigned tcs_num_patch_outputs) @@ -618,7 +617,7 @@ calculate_tess_lds_size(enum chip_class chip_class, unsigned tcs_num_input_verti unsigned lds_size = output_patch0_offset + output_patch_size * tcs_num_patches; - if (chip_class >= GFX7) { + if (gfx_level >= GFX7) { assert(lds_size <= 65536); lds_size = align(lds_size, 512) / 512; } else { @@ -633,7 +632,7 @@ static inline unsigned get_tcs_num_patches(unsigned tcs_num_input_vertices, unsigned tcs_num_output_vertices, unsigned tcs_num_inputs, unsigned tcs_num_outputs, unsigned tcs_num_patch_outputs, unsigned tess_offchip_block_dw_size, - enum chip_class chip_class, enum radeon_family family) + enum amd_gfx_level gfx_level, enum radeon_family family) { uint32_t input_vertex_size = tcs_num_inputs * 16; uint32_t input_patch_size = tcs_num_input_vertices * input_vertex_size; @@ -656,7 +655,7 @@ get_tcs_num_patches(unsigned tcs_num_input_vertices, unsigned tcs_num_output_ver * * Test: dEQP-VK.tessellation.shader_input_output.barrier */ - if (chip_class >= GFX7 && family != CHIP_STONEY) + if (gfx_level >= GFX7 && family != CHIP_STONEY) hardware_lds_size = 65536; if (input_patch_size + output_patch_size) @@ -670,7 +669,7 @@ get_tcs_num_patches(unsigned tcs_num_input_vertices, unsigned tcs_num_output_ver num_patches = MIN2(num_patches, 40); /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */ - if (chip_class == GFX6) { + if (gfx_level == GFX6) { unsigned one_wave = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices); num_patches = MIN2(num_patches, one_wave); } diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c index ce4f14a8777..7f8314d1c36 100644 --- a/src/amd/vulkan/radv_shader_args.c +++ b/src/amd/vulkan/radv_shader_args.c @@ -148,7 +148,7 @@ allocate_inline_push_consts(const struct radv_shader_info *info, } static void -allocate_user_sgprs(enum chip_class chip_class, const struct radv_shader_info *info, +allocate_user_sgprs(enum amd_gfx_level gfx_level, const struct radv_shader_info *info, struct radv_shader_args *args, gl_shader_stage stage, bool has_previous_stage, gl_shader_stage previous_stage, bool needs_view_index, bool has_api_gs, struct user_sgpr_info *user_sgpr_info) @@ -224,7 +224,7 @@ allocate_user_sgprs(enum chip_class chip_class, const struct radv_shader_info *i user_sgpr_count++; uint32_t available_sgprs = - chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE && stage != MESA_SHADER_TASK ? 32 : 16; + gfx_level >= GFX9 && stage != MESA_SHADER_COMPUTE && stage != MESA_SHADER_TASK ? 32 : 16; uint32_t remaining_sgprs = available_sgprs - user_sgpr_count; uint32_t num_desc_set = util_bitcount(info->desc_set_used_mask); @@ -295,18 +295,18 @@ declare_vs_specific_input_sgprs(const struct radv_shader_info *info, struct radv } static void -declare_vs_input_vgprs(enum chip_class chip_class, const struct radv_shader_info *info, +declare_vs_input_vgprs(enum amd_gfx_level gfx_level, const struct radv_shader_info *info, struct radv_shader_args *args) { ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.vertex_id); if (!args->is_gs_copy_shader) { if (info->vs.as_ls) { - if (chip_class >= GFX11) { + if (gfx_level >= GFX11) { ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user VGPR */ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user VGPR */ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id); - } else if (chip_class >= GFX10) { + } else if (gfx_level >= GFX10) { ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.vs_rel_patch_id); ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user vgpr */ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.instance_id); @@ -316,7 +316,7 @@ declare_vs_input_vgprs(enum chip_class chip_class, const struct radv_shader_info ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* unused */ } } else { - if (chip_class >= GFX10) { + if (gfx_level >= GFX10) { if (info->is_ngg) { ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user vgpr */ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user vgpr */ @@ -524,7 +524,7 @@ set_ms_input_locs(struct radv_shader_args *args, uint8_t *user_sgpr_idx) } void -radv_declare_shader_args(enum chip_class chip_class, const struct radv_pipeline_key *key, +radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipeline_key *key, const struct radv_shader_info *info, gl_shader_stage stage, bool has_previous_stage, gl_shader_stage previous_stage, struct radv_shader_args *args) @@ -533,7 +533,7 @@ radv_declare_shader_args(enum chip_class chip_class, const struct radv_pipeline_ bool needs_view_index = info->uses_view_index; bool has_api_gs = stage == MESA_SHADER_GEOMETRY; - if (chip_class >= GFX10 && info->is_ngg && stage != MESA_SHADER_GEOMETRY) { + if (gfx_level >= GFX10 && info->is_ngg && stage != MESA_SHADER_GEOMETRY) { /* Handle all NGG shaders as GS to simplify the code here. */ previous_stage = stage; stage = MESA_SHADER_GEOMETRY; @@ -545,7 +545,7 @@ radv_declare_shader_args(enum chip_class chip_class, const struct radv_pipeline_ for (int i = 0; i < AC_UD_MAX_UD; i++) args->user_sgprs_locs.shader_data[i].sgpr_idx = -1; - allocate_user_sgprs(chip_class, info, args, stage, has_previous_stage, previous_stage, + allocate_user_sgprs(gfx_level, info, args, stage, has_previous_stage, previous_stage, needs_view_index, has_api_gs, &user_sgpr_info); if (args->explicit_scratch_args) { @@ -603,7 +603,7 @@ radv_declare_shader_args(enum chip_class chip_class, const struct radv_pipeline_ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset); } - if (chip_class >= GFX11) + if (gfx_level >= GFX11) ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.local_invocation_ids); else ac_add_arg(&args->ac, AC_ARG_VGPR, 3, AC_ARG_INT, &args->ac.local_invocation_ids); @@ -636,7 +636,7 @@ radv_declare_shader_args(enum chip_class chip_class, const struct radv_pipeline_ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset); } - declare_vs_input_vgprs(chip_class, info, args); + declare_vs_input_vgprs(gfx_level, info, args); break; case MESA_SHADER_TESS_CTRL: if (has_previous_stage) { @@ -645,7 +645,7 @@ radv_declare_shader_args(enum chip_class chip_class, const struct radv_pipeline_ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.merged_wave_info); ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tcs_factor_offset); - if (chip_class >= GFX11) { + if (gfx_level >= GFX11) { ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tcs_wave_id); } else { ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset); @@ -665,7 +665,7 @@ radv_declare_shader_args(enum chip_class chip_class, const struct radv_pipeline_ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_patch_id); ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_rel_ids); - declare_vs_input_vgprs(chip_class, info, args); + declare_vs_input_vgprs(gfx_level, info, args); } else { declare_global_input_sgprs(info, &user_sgpr_info, args); @@ -747,7 +747,7 @@ radv_declare_shader_args(enum chip_class chip_class, const struct radv_pipeline_ ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[2]); if (previous_stage == MESA_SHADER_VERTEX) { - declare_vs_input_vgprs(chip_class, info, args); + declare_vs_input_vgprs(gfx_level, info, args); } else if (previous_stage == MESA_SHADER_TESS_EVAL) { declare_tes_input_vgprs(args); } else if (previous_stage == MESA_SHADER_MESH) { diff --git a/src/amd/vulkan/radv_shader_args.h b/src/amd/vulkan/radv_shader_args.h index b510c31d0ef..d79dce94f76 100644 --- a/src/amd/vulkan/radv_shader_args.h +++ b/src/amd/vulkan/radv_shader_args.h @@ -76,7 +76,7 @@ radv_shader_args_from_ac(struct ac_shader_args *args) struct radv_pipeline_key; struct radv_shader_info; -void radv_declare_shader_args(enum chip_class chip_class, const struct radv_pipeline_key *key, +void radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipeline_key *key, const struct radv_shader_info *info, gl_shader_stage stage, bool has_previous_stage, gl_shader_stage previous_stage, struct radv_shader_args *args); diff --git a/src/amd/vulkan/radv_spm.c b/src/amd/vulkan/radv_spm.c index f8669fee040..a0c03471004 100644 --- a/src/amd/vulkan/radv_spm.c +++ b/src/amd/vulkan/radv_spm.c @@ -200,7 +200,7 @@ radv_spm_init(struct radv_device *device) {GL1C, 0, 0xe}, /* Number of GL1C requests. */ {GL1C, 0, 0x12}, /* Number of GL1C misses. */ {GL2C, 0, 0x3}, /* Number of GL2C requests. */ - {GL2C, 0, info->chip_class >= GFX10_3 ? 0x2b : 0x23}, /* Number of GL2C misses. */ + {GL2C, 0, info->gfx_level >= GFX10_3 ? 0x2b : 0x23}, /* Number of GL2C misses. */ }; if (!ac_init_perfcounters(info, false, false, pc)) diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c index f6d55acbc28..a138cf92dc7 100644 --- a/src/amd/vulkan/radv_sqtt.c +++ b/src/amd/vulkan/radv_sqtt.c @@ -51,7 +51,7 @@ gfx10_get_thread_trace_ctrl(struct radv_device *device, bool enable) S_008D1C_SPI_STALL_EN(1) | S_008D1C_SQ_STALL_EN(1) | S_008D1C_REG_DROP_ON_STALL(0); - if (device->physical_device->rad_info.chip_class == GFX10_3) + if (device->physical_device->rad_info.gfx_level == GFX10_3) thread_trace_ctrl |= S_008D1C_LOWATER_OFFSET(4); if (device->physical_device->rad_info.has_sqtt_auto_flush_mode_bug) @@ -65,8 +65,8 @@ radv_emit_wait_for_idle(struct radv_device *device, struct radeon_cmdbuf *cs, in { enum rgp_flush_bits sqtt_flush_bits = 0; si_cs_emit_cache_flush( - cs, device->physical_device->rad_info.chip_class, NULL, 0, - family == AMD_IP_COMPUTE && device->physical_device->rad_info.chip_class >= GFX7, + cs, device->physical_device->rad_info.gfx_level, NULL, 0, + family == AMD_IP_COMPUTE && device->physical_device->rad_info.gfx_level >= GFX7, (family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) | @@ -97,7 +97,7 @@ radv_emit_thread_trace_start(struct radv_device *device, struct radeon_cmdbuf *c cs, R_030800_GRBM_GFX_INDEX, S_030800_SE_INDEX(se) | S_030800_SH_INDEX(0) | S_030800_INSTANCE_BROADCAST_WRITES(1)); - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { /* Order seems important for the following 2 registers. */ radeon_set_privileged_config_reg( cs, R_008D04_SQ_THREAD_TRACE_BUF0_SIZE, @@ -149,7 +149,7 @@ radv_emit_thread_trace_start(struct radv_device *device, struct radeon_cmdbuf *c S_030CC8_REG_STALL_EN(1) | S_030CC8_SPI_STALL_EN(1) | S_030CC8_SQ_STALL_EN(1); - if (device->physical_device->rad_info.chip_class < GFX9) { + if (device->physical_device->rad_info.gfx_level < GFX9) { thread_trace_mask |= S_030CC8_RANDOM_SEED(0xffff); } @@ -168,7 +168,7 @@ radv_emit_thread_trace_start(struct radv_device *device, struct radeon_cmdbuf *c radeon_set_uconfig_reg(cs, R_030CEC_SQ_THREAD_TRACE_HIWATER, S_030CEC_HIWATER(4)); - if (device->physical_device->rad_info.chip_class == GFX9) { + if (device->physical_device->rad_info.gfx_level == GFX9) { /* Reset thread trace status errors. */ radeon_set_uconfig_reg(cs, R_030CE8_SQ_THREAD_TRACE_STATUS, S_030CE8_UTC_ERROR(0)); } @@ -180,7 +180,7 @@ radv_emit_thread_trace_start(struct radv_device *device, struct radeon_cmdbuf *c S_030CD8_AUTOFLUSH_EN(1) | /* periodically flush SQTT data to memory */ S_030CD8_MODE(1); - if (device->physical_device->rad_info.chip_class == GFX9) { + if (device->physical_device->rad_info.gfx_level == GFX9) { /* Count SQTT traffic in TCC perf counters. */ thread_trace_mode |= S_030CD8_TC_PERF_EN(1); } @@ -227,12 +227,12 @@ radv_copy_thread_trace_info_regs(struct radv_device *device, struct radeon_cmdbu { const uint32_t *thread_trace_info_regs = NULL; - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { thread_trace_info_regs = gfx10_thread_trace_info_regs; - } else if (device->physical_device->rad_info.chip_class == GFX9) { + } else if (device->physical_device->rad_info.gfx_level == GFX9) { thread_trace_info_regs = gfx9_thread_trace_info_regs; } else { - assert(device->physical_device->rad_info.chip_class == GFX8); + assert(device->physical_device->rad_info.gfx_level == GFX8); thread_trace_info_regs = gfx8_thread_trace_info_regs; } @@ -283,7 +283,7 @@ radv_emit_thread_trace_stop(struct radv_device *device, struct radeon_cmdbuf *cs cs, R_030800_GRBM_GFX_INDEX, S_030800_SE_INDEX(se) | S_030800_SH_INDEX(0) | S_030800_INSTANCE_BROADCAST_WRITES(1)); - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { if (!device->physical_device->rad_info.has_sqtt_rb_harvest_bug) { /* Make sure to wait for the trace buffer. */ radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); @@ -347,7 +347,7 @@ radv_emit_thread_trace_userdata(const struct radv_device *device, struct radeon_ /* Without the perfctr bit the CP might not always pass the * write on correctly. */ - if (device->physical_device->rad_info.chip_class >= GFX10) + if (device->physical_device->rad_info.gfx_level >= GFX10) radeon_set_uconfig_reg_seq_perfctr(cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count); else radeon_set_uconfig_reg_seq(cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count); @@ -361,12 +361,12 @@ radv_emit_thread_trace_userdata(const struct radv_device *device, struct radeon_ static void radv_emit_spi_config_cntl(struct radv_device *device, struct radeon_cmdbuf *cs, bool enable) { - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { uint32_t spi_config_cntl = S_031100_GPR_WRITE_PRIORITY(0x2c688) | S_031100_EXP_PRIORITY_ORDER(3) | S_031100_ENABLE_SQG_TOP_EVENTS(enable) | S_031100_ENABLE_SQG_BOP_EVENTS(enable); - if (device->physical_device->rad_info.chip_class >= GFX10) + if (device->physical_device->rad_info.gfx_level >= GFX10) spi_config_cntl |= S_031100_PS_PKR_PRIORITY_CNTL(3); radeon_set_uconfig_reg(cs, R_031100_SPI_CONFIG_CNTL, spi_config_cntl); @@ -381,10 +381,10 @@ radv_emit_spi_config_cntl(struct radv_device *device, struct radeon_cmdbuf *cs, static void radv_emit_inhibit_clockgating(struct radv_device *device, struct radeon_cmdbuf *cs, bool inhibit) { - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { radeon_set_uconfig_reg(cs, R_037390_RLC_PERFMON_CLK_CNTL, S_037390_PERFMON_CLOCK_STATE(inhibit)); - } else if (device->physical_device->rad_info.chip_class >= GFX8) { + } else if (device->physical_device->rad_info.gfx_level >= GFX8) { radeon_set_uconfig_reg(cs, R_0372FC_RLC_PERFMON_CLK_CNTL, S_0372FC_PERFMON_CLOCK_STATE(inhibit)); } @@ -704,7 +704,7 @@ radv_get_thread_trace(struct radv_queue *queue, struct ac_thread_trace *thread_t thread_trace_se.shader_engine = se; /* RGP seems to expect units of WGP on GFX10+. */ - thread_trace_se.compute_unit = device->physical_device->rad_info.chip_class >= GFX10 + thread_trace_se.compute_unit = device->physical_device->rad_info.gfx_level >= GFX10 ? (first_active_cu / 2) : first_active_cu; diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c index 72b21659502..d3114ab2ecb 100644 --- a/src/amd/vulkan/radv_wsi.c +++ b/src/amd/vulkan/radv_wsi.c @@ -58,7 +58,7 @@ radv_wsi_get_prime_blit_queue(VkDevice _device) if (device->private_sdma_queue != VK_NULL_HANDLE) return vk_queue_to_handle(&device->private_sdma_queue->vk); - if (device->physical_device->rad_info.chip_class >= GFX9 && + if (device->physical_device->rad_info.gfx_level >= GFX9 && !(device->physical_device->instance->debug_flags & RADV_DEBUG_NO_DMA_BLIT)) { device->physical_device->vk_queue_to_radv[device->physical_device->num_queues++] = RADV_QUEUE_TRANSFER; @@ -96,7 +96,7 @@ radv_init_wsi(struct radv_physical_device *physical_device) if (result != VK_SUCCESS) return result; - physical_device->wsi_device.supports_modifiers = physical_device->rad_info.chip_class >= GFX9; + physical_device->wsi_device.supports_modifiers = physical_device->rad_info.gfx_level >= GFX9; physical_device->wsi_device.set_memory_ownership = radv_wsi_set_memory_ownership; physical_device->wsi_device.get_buffer_blit_queue = radv_wsi_get_prime_blit_queue; physical_device->wsi_device.signal_semaphore_with_memory = true; diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 7db61ce2b47..8d5bce94b0c 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -46,7 +46,7 @@ si_write_harvested_raster_configs(struct radv_physical_device *physical_device, for (se = 0; se < num_se; se++) { /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */ - if (physical_device->rad_info.chip_class < GFX7) + if (physical_device->rad_info.gfx_level < GFX7) radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, S_00802C_SE_INDEX(se) | S_00802C_SH_BROADCAST_WRITES(1) | S_00802C_INSTANCE_BROADCAST_WRITES(1)); @@ -58,7 +58,7 @@ si_write_harvested_raster_configs(struct radv_physical_device *physical_device, } /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */ - if (physical_device->rad_info.chip_class < GFX7) + if (physical_device->rad_info.gfx_level < GFX7) radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, S_00802C_SE_BROADCAST_WRITES(1) | S_00802C_SH_BROADCAST_WRITES(1) | S_00802C_INSTANCE_BROADCAST_WRITES(1)); @@ -67,7 +67,7 @@ si_write_harvested_raster_configs(struct radv_physical_device *physical_device, S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1)); - if (physical_device->rad_info.chip_class >= GFX7) + if (physical_device->rad_info.gfx_level >= GFX7) radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); } @@ -90,7 +90,7 @@ si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); - if (device->physical_device->rad_info.chip_class >= GFX7) { + if (device->physical_device->rad_info.gfx_level >= GFX7) { /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */ radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2); radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); @@ -105,12 +105,12 @@ si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) } } - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.gfx_level >= GFX9) { radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY, - device->physical_device->rad_info.chip_class >= GFX10 ? 0x20 : 0); + device->physical_device->rad_info.gfx_level >= GFX10 ? 0x20 : 0); } - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { radeon_set_sh_reg_seq(cs, R_00B890_COMPUTE_USER_ACCUM_0, 5); radeon_emit(cs, 0); /* R_00B890_COMPUTE_USER_ACCUM_0 */ radeon_emit(cs, 0); /* R_00B894_COMPUTE_USER_ACCUM_1 */ @@ -124,7 +124,7 @@ si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) * kernel if we want to use something other than the default value, * which is now 0x22f. */ - if (device->physical_device->rad_info.chip_class <= GFX6) { + if (device->physical_device->rad_info.gfx_level <= GFX6) { /* XXX: This should be: * (number of compute units) * 4 * (waves per simd) - 1 */ @@ -139,7 +139,7 @@ si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) if (device->tma_bo) { uint64_t tba_va, tma_va; - assert(device->physical_device->rad_info.chip_class == GFX8); + assert(device->physical_device->rad_info.gfx_level == GFX8); tba_va = radv_trap_handler_shader_get_va(device->trap_handler_shader); tma_va = radv_buffer_get_va(device->tma_bo); @@ -173,7 +173,7 @@ si_set_raster_config(struct radv_physical_device *physical_device, struct radeon */ if (!rb_mask || util_bitcount(rb_mask) >= num_rb) { radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config); - if (physical_device->rad_info.chip_class >= GFX7) + if (physical_device->rad_info.gfx_level >= GFX7) radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); } else { si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1); @@ -197,7 +197,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) radeon_emit(cs, 0); } - if (physical_device->rad_info.chip_class <= GFX8) + if (physical_device->rad_info.gfx_level <= GFX8) si_set_raster_config(physical_device, cs); radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); @@ -205,7 +205,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0)); /* FIXME calculate these values somehow ??? */ - if (physical_device->rad_info.chip_class <= GFX8) { + if (physical_device->rad_info.gfx_level <= GFX8) { radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES); radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40); } @@ -216,11 +216,11 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); } - if (physical_device->rad_info.chip_class <= GFX9) + if (physical_device->rad_info.gfx_level <= GFX9) radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1); if (!has_clear_state) radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0); - if (physical_device->rad_info.chip_class < GFX7) + if (physical_device->rad_info.gfx_level < GFX7) radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1)); @@ -230,7 +230,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) /* CLEAR_STATE doesn't clear these correctly on certain generations. * I don't know why. Deduced by trial and error. */ - if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) { + if (physical_device->rad_info.gfx_level <= GFX7 || !has_clear_state) { radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); @@ -267,7 +267,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE)); - if (physical_device->rad_info.chip_class >= GFX10) { + if (physical_device->rad_info.gfx_level >= GFX10) { radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0); radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0); radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0); @@ -278,7 +278,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) radeon_set_context_reg(cs, R_028038_DB_DFSM_CONTROL, S_028038_PUNCHOUT_MODE(V_028038_FORCE_OFF) | S_028038_POPS_DRAIN_PS_ON_OVERLAP(1)); - } else if (physical_device->rad_info.chip_class == GFX9) { + } else if (physical_device->rad_info.gfx_level == GFX9) { radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0); radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0); radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0); @@ -297,12 +297,12 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0); } - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->rad_info.gfx_level >= GFX10) { radeon_set_sh_reg(cs, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); - } else if (device->physical_device->rad_info.chip_class == GFX9) { + } else if (device->physical_device->rad_info.gfx_level == GFX9) { radeon_set_sh_reg(cs, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); radeon_set_sh_reg(cs, R_00B214_SPI_SHADER_PGM_HI_ES, @@ -327,11 +327,11 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) * CUs. In the future, we might disable or enable this tweak only for * certain apps. */ - if (physical_device->rad_info.chip_class >= GFX10_3) + if (physical_device->rad_info.gfx_level >= GFX10_3) cu_mask_ps = u_bit_consecutive(0, physical_device->rad_info.min_good_cu_per_sa); - if (physical_device->rad_info.chip_class >= GFX7) { - if (physical_device->rad_info.chip_class >= GFX10) { + if (physical_device->rad_info.gfx_level >= GFX7) { + if (physical_device->rad_info.gfx_level >= GFX10) { /* Logical CUs 16 - 31 */ ac_set_reg_cu_en(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS, S_00B404_CU_EN(0xffff), C_00B404_CU_EN, 16, &physical_device->rad_info, @@ -344,12 +344,12 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) (void*)gfx10_set_sh_reg_idx3); } - if (physical_device->rad_info.chip_class >= GFX10) { + if (physical_device->rad_info.gfx_level >= GFX10) { ac_set_reg_cu_en(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F), C_00B41C_CU_EN, 0, &physical_device->rad_info, (void*)gfx10_set_sh_reg_idx3); - } else if (physical_device->rad_info.chip_class == GFX9) { + } else if (physical_device->rad_info.gfx_level == GFX9) { radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F)); } else { @@ -366,7 +366,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) S_028A44_ES_VERTS_PER_SUBGRP(64) | S_028A44_GS_PRIMS_PER_SUBGRP(4)); } - if (physical_device->rad_info.chip_class >= GFX10) { + if (physical_device->rad_info.gfx_level >= GFX10) { ac_set_reg_cu_en(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(cu_mask_ps) | S_00B01C_WAVE_LIMIT(0x3F), C_00B01C_CU_EN, 0, &physical_device->rad_info, @@ -377,7 +377,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) } } - if (physical_device->rad_info.chip_class >= GFX10) { + if (physical_device->rad_info.gfx_level >= GFX10) { /* Break up a pixel wave if it contains deallocs for more than * half the parameter cache. * @@ -394,7 +394,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) * need to prevent drawing lines on internal edges of * decomposed primitives (such as quads) with polygon mode = lines. */ - unsigned vertex_reuse_depth = physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0; + unsigned vertex_reuse_depth = physical_device->rad_info.gfx_level >= GFX10_3 ? 30 : 0; radeon_set_context_reg(cs, R_028838_PA_CL_NGG_CNTL, S_028838_INDEX_BUF_EDGE_FLAG_ENA(0) | S_028838_VERTEX_REUSE_DEPTH(vertex_reuse_depth)); @@ -454,7 +454,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) S_00B0C0_SOFT_GROUPING_EN(1) | S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1)); radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0); - if (physical_device->rad_info.chip_class >= GFX10_3) { + if (physical_device->rad_info.gfx_level >= GFX10_3) { radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff); /* This allows sample shading. */ radeon_set_context_reg( @@ -463,12 +463,12 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) } } - if (physical_device->rad_info.chip_class >= GFX9) { + if (physical_device->rad_info.gfx_level >= GFX9) { radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, S_028B50_ACCUM_ISOLINE(40) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) | S_028B50_DONUT_SPLIT_GFX9(24) | S_028B50_TRAP_SPLIT(6)); - } else if (physical_device->rad_info.chip_class >= GFX8) { + } else if (physical_device->rad_info.gfx_level >= GFX8) { uint32_t vgt_tess_distribution; vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) | S_028B50_ACCUM_TRI(11) | @@ -488,13 +488,13 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) uint64_t border_color_va = radv_buffer_get_va(device->border_color_data.bo); radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8); - if (physical_device->rad_info.chip_class >= GFX7) { + if (physical_device->rad_info.gfx_level >= GFX7) { radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI, S_028084_ADDRESS(border_color_va >> 40)); } } - if (physical_device->rad_info.chip_class >= GFX9) { + if (physical_device->rad_info.gfx_level >= GFX9) { radeon_set_context_reg( cs, R_028C48_PA_SC_BINNER_CNTL_1, S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) | @@ -551,7 +551,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) if (device->tma_bo) { uint64_t tba_va, tma_va; - assert(device->physical_device->rad_info.chip_class == GFX8); + assert(device->physical_device->rad_info.gfx_level == GFX8); tba_va = radv_trap_handler_shader_get_va(device->trap_handler_shader); tma_va = radv_buffer_get_va(device->tma_bo); @@ -738,7 +738,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dra bool indirect_draw, bool count_from_stream_output, uint32_t draw_vertex_count, unsigned topology, bool prim_restart_enable) { - enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class; + enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level; enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family; struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info; const unsigned max_primgroup_in_wave = 2; @@ -768,7 +768,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dra ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi; partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave; - if (chip_class >= GFX7) { + if (gfx_level >= GFX7) { /* WD_SWITCH_ON_EOP has no effect on GPUs with less than * 4 shader engines. Set 1 to pass the assertion below. * The other cases are hardware requirements. */ @@ -791,7 +791,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dra * Assume indirect draws always use small instances. * This is needed for good VS wave utilization. */ - if (chip_class <= GFX8 && info->max_se == 4 && multi_instances_smaller_than_primgroup) + if (gfx_level <= GFX8 && info->max_se == 4 && multi_instances_smaller_than_primgroup) wd_switch_on_eop = true; /* Required on GFX7 and later. */ @@ -801,7 +801,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dra /* Required by Hawaii and, for some special cases, by GFX8. */ if (ia_switch_on_eoi && (family == CHIP_HAWAII || - (chip_class == GFX8 && + (gfx_level == GFX8 && /* max primgroup in wave is always 2 - leave this for documentation */ (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2)))) partial_vs_wave = true; @@ -820,7 +820,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dra assert(wd_switch_on_eop || !ia_switch_on_eop); } /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */ - if (chip_class <= GFX8 && ia_switch_on_eoi) + if (gfx_level <= GFX8 && ia_switch_on_eoi) partial_es_wave = true; if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) { @@ -853,11 +853,11 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dra S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) | S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) | S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) | - S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0); + S_028AA8_WD_SWITCH_ON_EOP(gfx_level >= GFX7 ? wd_switch_on_eop : 0); } void -si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, bool is_mec, +si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec, unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, uint32_t new_fence, uint64_t gfx9_eop_bug_va) @@ -865,7 +865,7 @@ si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, unsigned op = EVENT_TYPE(event) | EVENT_INDEX(event == V_028A90_CS_DONE || event == V_028A90_PS_DONE ? 6 : 5) | event_flags; - unsigned is_gfx8_mec = is_mec && chip_class < GFX9; + unsigned is_gfx8_mec = is_mec && gfx_level < GFX9; unsigned sel = EOP_DST_SEL(dst_sel) | EOP_DATA_SEL(data_sel); /* Wait for write confirmation before writing data, but don't send @@ -873,12 +873,12 @@ si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, if (data_sel != EOP_DATA_SEL_DISCARD) sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM); - if (chip_class >= GFX9 || is_gfx8_mec) { + if (gfx_level >= GFX9 || is_gfx8_mec) { /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion * counters) must immediately precede every timestamp event to * prevent a GPU hang on GFX9. */ - if (chip_class == GFX9 && !is_mec) { + if (gfx_level == GFX9 && !is_mec) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); radeon_emit(cs, gfx9_eop_bug_va); @@ -920,7 +920,7 @@ si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, radeon_emit(cs, new_fence); } } else { - if (chip_class == GFX7 || chip_class == GFX8) { + if (gfx_level == GFX7 || gfx_level == GFX8) { /* Two EOP events are required to make all * engines go idle (and optional cache flushes * executed) before the timestamp is written. @@ -981,9 +981,10 @@ si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigne } static void -gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uint32_t *flush_cnt, - uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, - enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) +gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, + uint32_t *flush_cnt, uint64_t flush_va, bool is_mec, + enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, + uint64_t gfx9_eop_bug_va) { uint32_t gcr_cntl = 0; unsigned cb_db_event = 0; @@ -1107,7 +1108,7 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, (*flush_cnt)++; si_cs_emit_write_event_eop( - cs, chip_class, false, cb_db_event, + cs, gfx_level, false, cb_db_event, S_490_GLM_WB(glm_wb) | S_490_GLM_INV(glm_inv) | S_490_GLV_INV(glv_inv) | S_490_GL1_INV(gl1_inv) | S_490_GL2_INV(gl2_inv) | S_490_GL2_WB(gl2_wb) | S_490_SEQ(gcr_seq), @@ -1157,7 +1158,7 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, } void -si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uint32_t *flush_cnt, +si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) { @@ -1165,9 +1166,9 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uin uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB); - if (chip_class >= GFX10) { + if (gfx_level >= GFX10) { /* GFX10 cache flush handling is quite different. */ - gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va, is_mec, flush_bits, + gfx10_cs_emit_cache_flush(cs, gfx_level, flush_cnt, flush_va, is_mec, flush_bits, sqtt_flush_bits, gfx9_eop_bug_va); return; } @@ -1181,7 +1182,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uin *sqtt_flush_bits |= RGP_FLUSH_INVAL_SMEM_L0; } - if (chip_class <= GFX8) { + if (gfx_level <= GFX8) { if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) { cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) | S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) | S_0085F0_CB2_DEST_BASE_ENA(1) | @@ -1190,8 +1191,8 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uin S_0085F0_CB7_DEST_BASE_ENA(1); /* Necessary for DCC */ - if (chip_class >= GFX8) { - si_cs_emit_write_event_eop(cs, chip_class, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, + if (gfx_level >= GFX8) { + si_cs_emit_write_event_eop(cs, gfx_level, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_DISCARD, 0, 0, gfx9_eop_bug_va); } @@ -1238,7 +1239,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uin *sqtt_flush_bits |= RGP_FLUSH_CS_PARTIAL_FLUSH; } - if (chip_class == GFX9 && flush_cb_db) { + if (gfx_level == GFX9 && flush_cb_db) { unsigned cb_db_event, tc_flags; /* Set the CB/DB flush event. */ @@ -1275,7 +1276,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uin assert(flush_cnt); (*flush_cnt)++; - si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags, EOP_DST_SEL_MEM, + si_cs_emit_write_event_eop(cs, gfx_level, false, cb_db_event, tc_flags, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, flush_va, *flush_cnt, gfx9_eop_bug_va); radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff); } @@ -1305,10 +1306,10 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uin } if ((flush_bits & RADV_CMD_FLAG_INV_L2) || - (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) { - si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, + (gfx_level <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) { + si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | S_0085F0_TCL1_ACTION_ENA(1) | - S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8)); + S_0301F0_TC_WB_ACTION_ENA(gfx_level >= GFX8)); cp_coher_cntl = 0; *sqtt_flush_bits |= RGP_FLUSH_INVAL_L2 | RGP_FLUSH_INVAL_VMEM_L0; @@ -1321,14 +1322,14 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uin * WB doesn't work without NC. */ si_emit_acquire_mem( - cs, is_mec, chip_class == GFX9, + cs, is_mec, gfx_level == GFX9, cp_coher_cntl | S_0301F0_TC_WB_ACTION_ENA(1) | S_0301F0_TC_NC_ACTION_ENA(1)); cp_coher_cntl = 0; *sqtt_flush_bits |= RGP_FLUSH_FLUSH_L2 | RGP_FLUSH_INVAL_VMEM_L0; } if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) { - si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, + si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1)); cp_coher_cntl = 0; @@ -1340,7 +1341,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uin * Therefore, it should be last. Done in PFP. */ if (cp_coher_cntl) - si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl); + si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl); if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); @@ -1371,7 +1372,7 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128); - si_cs_emit_cache_flush(cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.chip_class, + si_cs_emit_cache_flush(cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.gfx_level, &cmd_buffer->gfx9_fence_idx, cmd_buffer->gfx9_fence_va, radv_cmd_buffer_uses_mec(cmd_buffer), cmd_buffer->state.flush_bits, &cmd_buffer->state.sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va); @@ -1415,7 +1416,7 @@ si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_visi */ op |= draw_visible ? PREDICATION_DRAW_VISIBLE : PREDICATION_DRAW_NOT_VISIBLE; } - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0)); radeon_emit(cmd_buffer->cs, op); radeon_emit(cmd_buffer->cs, va); @@ -1445,7 +1446,7 @@ si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_visi static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer) { - unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 + unsigned max = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9 ? S_415_BYTE_COUNT_GFX9(~0u) : S_415_BYTE_COUNT_GFX6(~0u); @@ -1467,7 +1468,7 @@ si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t src assert(size <= cp_dma_max_byte_count(cmd_buffer)); radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9); - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) command |= S_415_BYTE_COUNT_GFX9(size); else command |= S_415_BYTE_COUNT_GFX6(size); @@ -1476,7 +1477,7 @@ si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t src if (flags & CP_DMA_SYNC) header |= S_411_CP_SYNC(1); else { - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) command |= S_415_DISABLE_WR_CONFIRM_GFX9(1); else command |= S_415_DISABLE_WR_CONFIRM_GFX6(1); @@ -1486,8 +1487,8 @@ si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t src command |= S_415_RAW_WAIT(1); /* Src and dst flags. */ - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 && - !(flags & CP_DMA_CLEAR) && src_va == dst_va) + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9 && !(flags & CP_DMA_CLEAR) && + src_va == dst_va) header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */ else if (flags & CP_DMA_USE_L2) header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2); @@ -1497,7 +1498,7 @@ si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t src else if (flags & CP_DMA_USE_L2) header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2); - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) { radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating)); radeon_emit(cs, header); radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ @@ -1548,7 +1549,7 @@ si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va, unsigned siz radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9); - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { command |= S_415_BYTE_COUNT_GFX9(aligned_size) | S_415_DISABLE_WR_CONFIRM_GFX9(1); header |= S_411_DST_SEL(V_411_NOWHERE); @@ -1650,7 +1651,7 @@ si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint6 unsigned dma_flags = 0; unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer)); - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { /* DMA operations via L2 are coherent and faster. * TODO: GFX7-GFX8 should also support this but it * requires tests/benchmarks. @@ -1704,7 +1705,7 @@ si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer)); unsigned dma_flags = CP_DMA_CLEAR; - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { /* DMA operations via L2 are coherent and faster. * TODO: GFX7-GFX8 should also support this but it * requires tests/benchmarks. @@ -1727,7 +1728,7 @@ si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer) { - if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7) + if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX7) return; if (!cmd_buffer->state.dma_is_busy) diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c index d8b1e2e12cb..c29dd153494 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c @@ -53,7 +53,7 @@ radv_amdgpu_bo_va_op(struct radv_amdgpu_winsys *ws, amdgpu_bo_handle bo, uint64_ if (bo) { flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_EXECUTABLE; - if ((bo_flags & RADEON_FLAG_VA_UNCACHED) && ws->info.chip_class >= GFX9) + if ((bo_flags & RADEON_FLAG_VA_UNCACHED) && ws->info.gfx_level >= GFX9) flags |= AMDGPU_VM_MTYPE_UC; if (!(bo_flags & RADEON_FLAG_READ_ONLY)) @@ -573,7 +573,7 @@ radv_amdgpu_get_optimal_vm_alignment(struct radv_amdgpu_winsys *ws, uint64_t siz /* Gfx9: Increase the VM alignment to the most significant bit set * in the size for faster address translation. */ - if (ws->info.chip_class >= GFX9) { + if (ws->info.gfx_level >= GFX9) { unsigned msb = util_last_bit64(size); /* 0 = no bit is set */ uint64_t msb_alignment = msb ? 1ull << (msb - 1) : 0; @@ -870,7 +870,7 @@ radv_amdgpu_winsys_bo_set_metadata(struct radeon_winsys *_ws, struct radeon_wins struct amdgpu_bo_metadata metadata = {0}; uint64_t tiling_flags = 0; - if (ws->info.chip_class >= GFX9) { + if (ws->info.gfx_level >= GFX9) { tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode); tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, md->u.gfx9.dcc_offset_256b); tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, md->u.gfx9.dcc_pitch_max); @@ -924,7 +924,7 @@ radv_amdgpu_winsys_bo_get_metadata(struct radeon_winsys *_ws, struct radeon_wins uint64_t tiling_flags = info.metadata.tiling_info; - if (ws->info.chip_class >= GFX9) { + if (ws->info.gfx_level >= GFX9) { md->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); md->u.gfx9.scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT); } else { diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c index 4c06bd72d89..59211aab871 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c @@ -285,7 +285,7 @@ static uint32_t get_nop_packet(struct radv_amdgpu_cs *cs) case AMDGPU_HW_IP_COMPUTE: return cs->ws->info.gfx_ib_pad_with_type2 ? PKT2_NOP_PAD : PKT3_NOP_PAD; case AMDGPU_HW_IP_DMA: - return cs->ws->info.chip_class <= GFX6 ? 0xF0000000 : SDMA_NOP_PAD; + return cs->ws->info.gfx_level <= GFX6 ? 0xF0000000 : SDMA_NOP_PAD; case AMDGPU_HW_IP_UVD: case AMDGPU_HW_IP_UVD_ENC: return PKT2_NOP_PAD; @@ -1492,7 +1492,7 @@ radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf *_cs, FILE *file, const int *tra num_dw = cs->ib.size; } assert(ib); - ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count, "main IB", cs->ws->info.chip_class, + ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count, "main IB", cs->ws->info.gfx_level, radv_amdgpu_winsys_get_cpu_addr, cs); } diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c index 2e8ca6d940c..409f77aada1 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c @@ -59,7 +59,7 @@ do_winsys_init(struct radv_amdgpu_winsys *ws, int fd) ws->info.ip[AMD_IP_SDMA].num_queues = MIN2(ws->info.ip[AMD_IP_SDMA].num_queues, MAX_RINGS_PER_TYPE); ws->info.ip[AMD_IP_COMPUTE].num_queues = MIN2(ws->info.ip[AMD_IP_COMPUTE].num_queues, MAX_RINGS_PER_TYPE); - ws->use_ib_bos = ws->info.chip_class >= GFX7; + ws->use_ib_bos = ws->info.gfx_level >= GFX7; return true; } diff --git a/src/amd/vulkan/winsys/null/radv_null_winsys.c b/src/amd/vulkan/winsys/null/radv_null_winsys.c index 3b3566ac239..9ae4dfa0cc7 100644 --- a/src/amd/vulkan/winsys/null/radv_null_winsys.c +++ b/src/amd/vulkan/winsys/null/radv_null_winsys.c @@ -77,29 +77,29 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info) const char *family = getenv("RADV_FORCE_FAMILY"); unsigned i; - info->chip_class = CLASS_UNKNOWN; + info->gfx_level = CLASS_UNKNOWN; info->family = CHIP_UNKNOWN; for (i = CHIP_TAHITI; i < CHIP_LAST; i++) { if (!strcasecmp(family, ac_get_family_name(i))) { - /* Override family and chip_class. */ + /* Override family and gfx_level. */ info->family = i; info->name = ac_get_family_name(i); if (info->family >= CHIP_GFX1100) - info->chip_class = GFX11; + info->gfx_level = GFX11; else if (i >= CHIP_SIENNA_CICHLID) - info->chip_class = GFX10_3; + info->gfx_level = GFX10_3; else if (i >= CHIP_NAVI10) - info->chip_class = GFX10; + info->gfx_level = GFX10; else if (i >= CHIP_VEGA10) - info->chip_class = GFX9; + info->gfx_level = GFX9; else if (i >= CHIP_TONGA) - info->chip_class = GFX8; + info->gfx_level = GFX8; else if (i >= CHIP_BONAIRE) - info->chip_class = GFX7; + info->gfx_level = GFX7; else - info->chip_class = GFX6; + info->gfx_level = GFX6; } } @@ -111,32 +111,32 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info) info->pci_id = gpu_info[info->family].pci_id; info->max_se = 4; info->num_se = 4; - if (info->chip_class >= GFX10_3) + if (info->gfx_level >= GFX10_3) info->max_wave64_per_simd = 16; - else if (info->chip_class >= GFX10) + else if (info->gfx_level >= GFX10) info->max_wave64_per_simd = 20; else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM) info->max_wave64_per_simd = 8; else info->max_wave64_per_simd = 10; - if (info->chip_class >= GFX10) + if (info->gfx_level >= GFX10) info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2; - else if (info->chip_class >= GFX8) + else if (info->gfx_level >= GFX8) info->num_physical_sgprs_per_simd = 800; else info->num_physical_sgprs_per_simd = 512; - info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256; - info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4; - info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024; - info->lds_encode_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4; + info->num_physical_wave64_vgprs_per_simd = info->gfx_level >= GFX10 ? 512 : 256; + info->num_simd_per_compute_unit = info->gfx_level >= GFX10 ? 2 : 4; + info->lds_size_per_workgroup = info->gfx_level >= GFX10 ? 128 * 1024 : 64 * 1024; + info->lds_encode_granularity = info->gfx_level >= GFX7 ? 128 * 4 : 64 * 4; info->lds_alloc_granularity = - info->chip_class >= GFX10_3 ? 256 * 4 : info->lds_encode_granularity; + info->gfx_level >= GFX10_3 ? 256 * 4 : info->lds_encode_granularity; info->max_render_backends = gpu_info[info->family].num_render_backends; info->has_dedicated_vram = gpu_info[info->family].has_dedicated_vram; - info->has_packed_math_16bit = info->chip_class >= GFX9; + info->has_packed_math_16bit = info->gfx_level >= GFX9; info->has_image_load_dcc_bug = info->family == CHIP_DIMGREY_CAVEFISH || info->family == CHIP_VANGOGH; @@ -145,13 +145,13 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info) info->family == CHIP_ARCTURUS || info->family == CHIP_ALDEBARAN || info->family == CHIP_VEGA20 || info->family >= CHIP_NAVI12; - info->address32_hi = info->chip_class >= GFX9 ? 0xffff8000u : 0x0; + info->address32_hi = info->gfx_level >= GFX9 ? 0xffff8000u : 0x0; - info->has_rbplus = info->family == CHIP_STONEY || info->chip_class >= GFX9; + info->has_rbplus = info->family == CHIP_STONEY || info->gfx_level >= GFX9; info->rbplus_allowed = info->has_rbplus && (info->family == CHIP_STONEY || info->family == CHIP_VEGA12 || info->family == CHIP_RAVEN || - info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->chip_class >= GFX10_3); + info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->gfx_level >= GFX10_3); } diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c index 9468e4b014f..a0eb629a368 100644 --- a/src/gallium/drivers/r600/eg_asm.c +++ b/src/gallium/drivers/r600/eg_asm.c @@ -75,7 +75,7 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf) S_SQ_CF_WORD1_BARRIER(1) | S_SQ_CF_WORD1_VALID_PIXEL_MODE(cf->vpm) | S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1); - if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ + if (bc->gfx_level == EVERGREEN) /* no EOP on cayman */ bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program); id++; } else if (cfop->flags & CF_EXP) { @@ -95,7 +95,7 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf) S_SQ_CF_ALLOC_EXPORT_WORD1_MARK(cf->mark) | S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode); - if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ + if (bc->gfx_level == EVERGREEN) /* no EOP on cayman */ bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program); id++; } else if (cfop->flags & CF_RAT) { @@ -114,7 +114,7 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf) S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask) | S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) | S_SQ_CF_ALLOC_EXPORT_WORD1_MARK(cf->output.mark); - if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ + if (bc->gfx_level == EVERGREEN) /* no EOP on cayman */ bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program); id++; @@ -131,7 +131,7 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf) S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) | S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask) | S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size); - if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ + if (bc->gfx_level == EVERGREEN) /* no EOP on cayman */ bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program); id++; } else { @@ -143,7 +143,7 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf) S_SQ_CF_WORD1_COND(cf->cond) | S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) | S_SQ_CF_WORD1_COUNT(cf->count); - if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ + if (bc->gfx_level == EVERGREEN) /* no EOP on cayman */ bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program); id++; } @@ -181,7 +181,7 @@ int egcm_load_index_reg(struct r600_bytecode *bc, unsigned id, bool inside_alu_c unsigned type; assert(id < 2); - assert(bc->chip_class >= EVERGREEN); + assert(bc->gfx_level >= EVERGREEN); if (bc->index_loaded[id]) return 0; @@ -190,7 +190,7 @@ int egcm_load_index_reg(struct r600_bytecode *bc, unsigned id, bool inside_alu_c alu.op = ALU_OP1_MOVA_INT; alu.src[0].sel = bc->index_reg[id]; alu.src[0].chan = bc->index_reg_chan[id]; - if (bc->chip_class == CAYMAN) + if (bc->gfx_level == CAYMAN) alu.dst.sel = id == 0 ? CM_V_SQ_MOVA_DST_CF_IDX0 : CM_V_SQ_MOVA_DST_CF_IDX1; alu.last = 1; @@ -200,7 +200,7 @@ int egcm_load_index_reg(struct r600_bytecode *bc, unsigned id, bool inside_alu_c bc->ar_loaded = 0; /* clobbered */ - if (bc->chip_class == EVERGREEN) { + if (bc->gfx_level == EVERGREEN) { memset(&alu, 0, sizeof(alu)); alu.op = id == 0 ? ALU_OP0_SET_CF_IDX0 : ALU_OP0_SET_CF_IDX1; alu.last = 1; diff --git a/src/gallium/drivers/r600/eg_debug.c b/src/gallium/drivers/r600/eg_debug.c index 853b610441f..8d0924319c0 100644 --- a/src/gallium/drivers/r600/eg_debug.c +++ b/src/gallium/drivers/r600/eg_debug.c @@ -141,7 +141,7 @@ static void ac_parse_set_reg_packet(FILE *f, uint32_t *ib, unsigned count, } static uint32_t *ac_parse_packet3(FILE *f, uint32_t *ib, int *num_dw, - int trace_id, enum chip_class chip_class, + int trace_id, enum amd_gfx_level gfx_level, ac_debug_addr_callback addr_callback, void *addr_callback_data) { @@ -275,7 +275,7 @@ static uint32_t *ac_parse_packet3(FILE *f, uint32_t *ib, int *num_dw, * \param f file * \param ib IB * \param num_dw size of the IB - * \param chip_class chip class + * \param gfx_level gfx level * \param trace_id the last trace ID that is known to have been reached * and executed by the CP, typically read from a buffer * \param addr_callback Get a mapped pointer of the IB at a given address. Can @@ -283,7 +283,7 @@ static uint32_t *ac_parse_packet3(FILE *f, uint32_t *ib, int *num_dw, * \param addr_callback_data user data for addr_callback */ static void eg_parse_ib(FILE *f, uint32_t *ib, int num_dw, int trace_id, - const char *name, enum chip_class chip_class, + const char *name, enum amd_gfx_level gfx_level, ac_debug_addr_callback addr_callback, void *addr_callback_data) { fprintf(f, "------------------ %s begin ------------------\n", name); @@ -294,7 +294,7 @@ static void eg_parse_ib(FILE *f, uint32_t *ib, int num_dw, int trace_id, switch (type) { case 3: ib = ac_parse_packet3(f, ib, &num_dw, trace_id, - chip_class, addr_callback, + gfx_level, addr_callback, addr_callback_data); break; case 2: @@ -341,7 +341,7 @@ static void eg_dump_last_ib(struct r600_context *rctx, FILE *f) } eg_parse_ib(f, rctx->last_gfx.ib, rctx->last_gfx.num_dw, - last_trace_id, "IB", rctx->b.chip_class, + last_trace_id, "IB", rctx->b.gfx_level, NULL, NULL); } diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c index 18a50b5b864..d1fe115bbd2 100644 --- a/src/gallium/drivers/r600/evergreen_compute.c +++ b/src/gallium/drivers/r600/evergreen_compute.c @@ -646,7 +646,7 @@ static void evergreen_emit_dispatch(struct r600_context *rctx, radeon_emit(cs, info->block[1]); /* R_0286F0_SPI_COMPUTE_NUM_THREAD_Y */ radeon_emit(cs, info->block[2]); /* R_0286F4_SPI_COMPUTE_NUM_THREAD_Z */ - if (rctx->b.chip_class < CAYMAN) { + if (rctx->b.gfx_level < CAYMAN) { assert(lds_size <= 8192); } else { /* Cayman appears to have a slightly smaller limit, see the @@ -796,7 +796,7 @@ static void compute_emit_cs(struct r600_context *rctx, r600_emit_command_buffer(cs, &rctx->start_compute_cs_cmd); /* emit config state */ - if (rctx->b.chip_class == EVERGREEN) { + if (rctx->b.gfx_level == EVERGREEN) { if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI|| rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_NIR) { radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3); @@ -858,7 +858,7 @@ static void compute_emit_cs(struct r600_context *rctx, r600_flush_emit(rctx); rctx->b.flags = 0; - if (rctx->b.chip_class >= CAYMAN) { + if (rctx->b.gfx_level >= CAYMAN) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); /* DEALLOC_STATE prevents the GPU from hanging when a @@ -1117,7 +1117,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *rctx) r600_store_config_reg(cb, R_008958_VGT_PRIMITIVE_TYPE, V_008958_DI_PT_POINTLIST); - if (rctx->b.chip_class < CAYMAN) { + if (rctx->b.gfx_level < CAYMAN) { /* These registers control which simds can be used by each stage. * The default for these registers is 0xffffffff, which means @@ -1167,7 +1167,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *rctx) * allocate the appropriate amount of LDS dwords using the * CM_R_0288E8_SQ_LDS_ALLOC register. */ - if (rctx->b.chip_class < CAYMAN) { + if (rctx->b.gfx_level < CAYMAN) { r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT, S_008E2C_NUM_PS_LDS(0x0000) | S_008E2C_NUM_LS_LDS(8192)); } else { @@ -1178,7 +1178,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *rctx) /* Context Registers */ - if (rctx->b.chip_class < CAYMAN) { + if (rctx->b.gfx_level < CAYMAN) { /* workaround for hw issues with dyn gpr - must set all limits * to 240 instead of 0, 0x1e == 240 / 8 */ diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 65a4fd8b3cc..553ebf28e21 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -228,7 +228,7 @@ static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pi FALSE) != ~0U; } -static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format) +static bool r600_is_colorbuffer_format_supported(enum amd_gfx_level chip, enum pipe_format format) { return r600_translate_colorformat(chip, format, FALSE) != ~0U && r600_translate_colorswap(format, FALSE) != ~0U; @@ -286,7 +286,7 @@ bool evergreen_is_format_supported(struct pipe_screen *screen, PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_BLENDABLE)) && - r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) { + r600_is_colorbuffer_format_supported(rscreen->b.gfx_level, format)) { retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | @@ -545,7 +545,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx, S_028A48_VPORT_SCISSOR_ENABLE(1) | S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable)); - if (rctx->b.chip_class == CAYMAN) { + if (rctx->b.gfx_level == CAYMAN) { r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL, S_028C08_PIX_CENTER_HALF(state->half_pixel_center) | S_028C08_QUANT_MODE(V_028C08_X_1_256TH)); @@ -821,7 +821,7 @@ static int evergreen_fill_tex_resource_words(struct r600_context *rctx, fmask_bankh = eg_bank_wh(tmp->fmask.bank_height); /* 128 bit formats require tile type = 1 */ - if (rscreen->b.chip_class == CAYMAN) { + if (rscreen->b.gfx_level == CAYMAN) { if (util_format_get_blocksize(params->pipe_format) >= 16) non_disp_tiling = 1; } @@ -845,7 +845,7 @@ static int evergreen_fill_tex_resource_words(struct r600_context *rctx, tex_resource_words[0] = (S_030000_DIM(dim) | S_030000_PITCH((pitch / 8) - 1) | S_030000_TEX_WIDTH(width - 1)); - if (rscreen->b.chip_class == CAYMAN) + if (rscreen->b.gfx_level == CAYMAN) tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling); else tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling); @@ -883,7 +883,7 @@ static int evergreen_fill_tex_resource_words(struct r600_context *rctx, if (texture->nr_samples > 1) { unsigned log_samples = util_logbase2(texture->nr_samples); - if (rscreen->b.chip_class == CAYMAN) { + if (rscreen->b.gfx_level == CAYMAN) { tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples); } /* LAST_LEVEL holds log2(nr_samples) for multisample textures */ @@ -1063,7 +1063,7 @@ static void evergreen_set_color_surface_buffer(struct r600_context *rctx, width_elements = last_element - first_element + 1; - format = r600_translate_colorformat(rctx->b.chip_class, pformat, FALSE); + format = r600_translate_colorformat(rctx->b.gfx_level, pformat, FALSE); swap = r600_translate_colorswap(pformat, FALSE); endian = r600_colorformat_endian_swap(format, FALSE); @@ -1173,7 +1173,7 @@ static void evergreen_set_color_surface_common(struct r600_context *rctx, bankh = eg_bank_wh(bankh); fmask_bankh = eg_bank_wh(fmask_bankh); - if (rscreen->b.chip_class == CAYMAN) { + if (rscreen->b.gfx_level == CAYMAN) { if (util_format_get_blocksize(pformat) >= 16) non_disp_tiling = 1; } @@ -1192,7 +1192,7 @@ static void evergreen_set_color_surface_common(struct r600_context *rctx, S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) | S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); - if (rctx->b.chip_class == CAYMAN) { + if (rctx->b.gfx_level == CAYMAN) { color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1); @@ -1223,7 +1223,7 @@ static void evergreen_set_color_surface_common(struct r600_context *rctx, if (R600_BIG_ENDIAN) do_endian_swap = !rtex->db_compatible; - format = r600_translate_colorformat(rctx->b.chip_class, pformat, do_endian_swap); + format = r600_translate_colorformat(rctx->b.gfx_level, pformat, do_endian_swap); assert(format != ~0); swap = r600_translate_colorswap(pformat, do_endian_swap); assert(swap != ~0); @@ -1396,7 +1396,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, S_028040_BANK_WIDTH(bankw) | S_028040_BANK_HEIGHT(bankh) | S_028040_MACRO_TILE_ASPECT(macro_aspect); - if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) { + if (rscreen->b.gfx_level == CAYMAN && rtex->resource.b.b.nr_samples > 1) { surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)); } @@ -1559,7 +1559,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, log_samples = util_logbase2(rctx->framebuffer.nr_samples); /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */ - if ((rctx->b.chip_class == CAYMAN || + if ((rctx->b.gfx_level == CAYMAN || rctx->b.family == CHIP_RV770) && rctx->db_misc_state.log_samples != log_samples) { rctx->db_misc_state.log_samples = log_samples; @@ -1571,7 +1571,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */ /* MSAA. */ - if (rctx->b.chip_class == EVERGREEN) + if (rctx->b.gfx_level == EVERGREEN) rctx->framebuffer.atom.num_dw += 17; /* Evergreen */ else rctx->framebuffer.atom.num_dw += 28; /* Cayman */ @@ -1967,7 +1967,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */ radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */ - if (rctx->b.chip_class == EVERGREEN) { + if (rctx->b.gfx_level == EVERGREEN) { evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples); } else { cayman_emit_msaa_state(cs, rctx->framebuffer.nr_samples, @@ -2084,7 +2084,7 @@ static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_ if (rctx->b.num_occlusion_queries > 0 && !a->occlusion_queries_disabled) { db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1); - if (rctx->b.chip_class == CAYMAN) { + if (rctx->b.gfx_level == CAYMAN) { db_count_control |= S_028004_SAMPLE_RATE(a->log_samples); } db_render_override |= S_02800C_NOOP_CULL_DISABLE(1); @@ -2709,7 +2709,7 @@ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom } void cayman_init_common_regs(struct r600_command_buffer *cb, - enum chip_class ctx_chip_class, + enum amd_gfx_level gfx_level, enum radeon_family ctx_family, int ctx_drm_minor) { @@ -2753,7 +2753,7 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0)); - cayman_init_common_regs(cb, rctx->b.chip_class, + cayman_init_common_regs(cb, rctx->b.gfx_level, rctx->b.family, rctx->screen->b.info.drm_minor); r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0); @@ -2891,7 +2891,7 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) } void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb, - enum chip_class ctx_chip_class, + enum amd_gfx_level gfx_level, enum radeon_family ctx_family, int ctx_drm_minor) { @@ -2979,7 +2979,7 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) enum radeon_family family; unsigned tmp, i; - if (rctx->b.chip_class == CAYMAN) { + if (rctx->b.gfx_level == CAYMAN) { cayman_init_atom_start_cs(rctx); return; } @@ -3001,7 +3001,7 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0)); - evergreen_init_common_regs(rctx, cb, rctx->b.chip_class, + evergreen_init_common_regs(rctx, cb, rctx->b.gfx_level, rctx->b.family, rctx->screen->b.info.drm_minor); family = rctx->b.family; @@ -3957,7 +3957,7 @@ static void evergreen_dma_copy(struct pipe_context *ctx, * DMA only supports it on the tiled side. As such * the tile order is backwards after a L2T/T2L packet. */ - if ((rctx->b.chip_class == CAYMAN) && + if ((rctx->b.gfx_level == CAYMAN) && (src_mode != dst_mode) && (util_format_get_blocksize(src->format) >= 16)) { goto fallback; @@ -4424,7 +4424,7 @@ void evergreen_init_state_functions(struct r600_context *rctx) * or piglit regression). * !!! */ - if (rctx->b.chip_class == EVERGREEN) { + if (rctx->b.gfx_level == EVERGREEN) { r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11); rctx->config_state.dyn_gpr_enabled = true; } @@ -4461,7 +4461,7 @@ void evergreen_init_state_functions(struct r600_context *rctx) r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10); - if (rctx->b.chip_class == EVERGREEN) { + if (rctx->b.gfx_level == EVERGREEN) { r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3); } else { r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4); @@ -4504,7 +4504,7 @@ void evergreen_init_state_functions(struct r600_context *rctx) rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers; rctx->b.b.set_shader_images = evergreen_set_shader_images; rctx->b.b.set_shader_buffers = evergreen_set_shader_buffers; - if (rctx->b.chip_class == EVERGREEN) + if (rctx->b.gfx_level == EVERGREEN) rctx->b.b.get_sample_position = evergreen_get_sample_position; else rctx->b.b.get_sample_position = cayman_get_sample_position; @@ -4783,7 +4783,7 @@ void eg_trace_emit(struct r600_context *rctx) struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; unsigned reloc; - if (rctx->b.chip_class < EVERGREEN) + if (rctx->b.gfx_level < EVERGREEN) return; /* This must be done after r600_need_cs_space. */ @@ -4969,7 +4969,7 @@ void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx, struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer); assert(resource); - if (rctx->b.chip_class == CAYMAN) + if (rctx->b.gfx_level == CAYMAN) cayman_write_count_to_gds(rctx, atomic, resource, pkt_flags); else evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags); @@ -5002,7 +5002,7 @@ void evergreen_emit_atomic_buffer_save(struct r600_context *rctx, struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer); assert(resource); - if (rctx->b.chip_class == CAYMAN) + if (rctx->b.gfx_level == CAYMAN) cayman_emit_event_write_eos(rctx, atomic, resource, pkt_flags); else evergreen_emit_event_write_eos(rctx, atomic, resource, pkt_flags); diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c index ec772d48dc1..00fc1e5dea0 100644 --- a/src/gallium/drivers/r600/r600_asm.c +++ b/src/gallium/drivers/r600/r600_asm.c @@ -137,7 +137,7 @@ static unsigned stack_entry_size(enum radeon_family chip) { } void r600_bytecode_init(struct r600_bytecode *bc, - enum chip_class chip_class, + enum amd_gfx_level gfx_level, enum radeon_family family, bool has_compressed_msaa_texturing) { @@ -145,7 +145,7 @@ void r600_bytecode_init(struct r600_bytecode *bc, bc->debug_id = ++next_shader_id; - if ((chip_class == R600) && + if ((gfx_level == R600) && (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) { bc->ar_handling = AR_HANDLE_RV6XX; @@ -166,7 +166,7 @@ void r600_bytecode_init(struct r600_bytecode *bc, } list_inithead(&bc->cf); - bc->chip_class = chip_class; + bc->gfx_level = gfx_level; bc->family = family; bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing; bc->stack.entry_size = stack_entry_size(family); @@ -261,7 +261,7 @@ int r600_bytecode_wait_acks(struct r600_bytecode *bc) { /* Store acks are an R700+ feature. */ - if (bc->chip_class < R700) + if (bc->gfx_level < R700) return 0; if (!bc->need_wait_ack) @@ -282,7 +282,7 @@ r600_bytecode_wait_acks(struct r600_bytecode *bc) uint32_t r600_bytecode_write_export_ack_type(struct r600_bytecode *bc, bool indirect) { - if (bc->chip_class >= R700) { + if (bc->gfx_level >= R700) { if (indirect) return V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND_ACK_EG; else @@ -382,7 +382,7 @@ static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu * { struct r600_bytecode_alu *alu; unsigned i, chan, trans; - int max_slots = bc->chip_class == CAYMAN ? 4 : 5; + int max_slots = bc->gfx_level == CAYMAN ? 4 : 5; for (i = 0; i < max_slots; i++) assignment[i] = NULL; @@ -470,7 +470,7 @@ static int reserve_cfile(const struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan) { int res, num_res = 4; - if (bc->chip_class >= R700) { + if (bc->gfx_level >= R700) { num_res = 2; chan /= 2; } @@ -591,8 +591,8 @@ static int check_and_set_bank_swizzle(const struct r600_bytecode *bc, struct alu_bank_swizzle bs; int bank_swizzle[5]; int i, r = 0, forced = 1; - boolean scalar_only = bc->chip_class == CAYMAN ? false : true; - int max_slots = bc->chip_class == CAYMAN ? 4 : 5; + boolean scalar_only = bc->gfx_level == CAYMAN ? false : true; + int max_slots = bc->gfx_level == CAYMAN ? 4 : 5; for (i = 0; i < max_slots; i++) { if (slots[i]) { @@ -670,7 +670,7 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc, struct r600_bytecode_alu *prev[5]; int gpr[5], chan[5]; int i, j, r, src, num_src; - int max_slots = bc->chip_class == CAYMAN ? 4 : 5; + int max_slots = bc->gfx_level == CAYMAN ? 4 : 5; r = assign_alu_units(bc, alu_prev, prev); if (r) @@ -706,7 +706,7 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc, if (!is_gpr(alu->src[src].sel) || alu->src[src].rel) continue; - if (bc->chip_class < CAYMAN) { + if (bc->gfx_level < CAYMAN) { if (alu->src[src].sel == gpr[4] && alu->src[src].chan == chan[4] && alu_prev->pred_sel == alu->pred_sel) { @@ -815,7 +815,7 @@ static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu int i, j, r, src, num_src; int num_once_inst = 0; int have_mova = 0, have_rel = 0; - int max_slots = bc->chip_class == CAYMAN ? 4 : 5; + int max_slots = bc->gfx_level == CAYMAN ? 4 : 5; r = assign_alu_units(bc, alu_prev, prev); if (r) @@ -1010,7 +1010,7 @@ static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc, struct r600_bytecode_kcache *kcache, unsigned bank, unsigned line, unsigned index_mode) { - int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2; + int i, kcache_banks = bc->gfx_level >= EVERGREEN ? 4 : 2; for (i = 0; i < kcache_banks; i++) { if (kcache[i].mode) { @@ -1168,7 +1168,7 @@ static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */ if (kcache[2].mode != V_SQ_CF_KCACHE_NOP || kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) { - if (bc->chip_class < EVERGREEN) + if (bc->gfx_level < EVERGREEN) return -ENOMEM; bc->cf_last->eg_alu_extended = 1; } @@ -1295,7 +1295,7 @@ int r600_bytecode_add_alu_type(struct r600_bytecode *bc, bc->cf_last->op = type; /* Load index register if required */ - if (bc->chip_class >= EVERGREEN) { + if (bc->gfx_level >= EVERGREEN) { for (i = 0; i < 3; i++) if (nalu->src[i].kc_bank && nalu->src[i].kc_rel) egcm_load_index_reg(bc, 0, true); @@ -1341,7 +1341,7 @@ int r600_bytecode_add_alu_type(struct r600_bytecode *bc, uint32_t literal[4]; unsigned nliteral; struct r600_bytecode_alu *slots[5]; - int max_slots = bc->chip_class == CAYMAN ? 4 : 5; + int max_slots = bc->gfx_level == CAYMAN ? 4 : 5; r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots); if (r) return r; @@ -1410,7 +1410,7 @@ int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_a static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc) { - switch (bc->chip_class) { + switch (bc->gfx_level) { case R600: return 8; @@ -1420,7 +1420,7 @@ static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_byt return 16; default: - R600_ERR("Unknown chip class %d.\n", bc->chip_class); + R600_ERR("Unknown gfx level %d.\n", bc->gfx_level); return 8; } } @@ -1429,7 +1429,7 @@ static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc) { return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) && bc->cf_last->op != CF_OP_GDS && - (bc->chip_class == CAYMAN || + (bc->gfx_level == CAYMAN || bc->cf_last->op != CF_OP_TEX)); } @@ -1444,7 +1444,7 @@ static int r600_bytecode_add_vtx_internal(struct r600_bytecode *bc, const struct memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx)); /* Load index register if required */ - if (bc->chip_class >= EVERGREEN) { + if (bc->gfx_level >= EVERGREEN) { if (vtx->buffer_index_mode) egcm_load_index_reg(bc, vtx->buffer_index_mode - 1, false); } @@ -1458,7 +1458,7 @@ static int r600_bytecode_add_vtx_internal(struct r600_bytecode *bc, const struct free(nvtx); return r; } - switch (bc->chip_class) { + switch (bc->gfx_level) { case R600: case R700: bc->cf_last->op = CF_OP_VTX; @@ -1473,7 +1473,7 @@ static int r600_bytecode_add_vtx_internal(struct r600_bytecode *bc, const struct bc->cf_last->op = CF_OP_TEX; break; default: - R600_ERR("Unknown chip class %d.\n", bc->chip_class); + R600_ERR("Unknown gfx level %d.\n", bc->gfx_level); free(nvtx); return -EINVAL; } @@ -1511,7 +1511,7 @@ int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_t memcpy(ntex, tex, sizeof(struct r600_bytecode_tex)); /* Load index register if required */ - if (bc->chip_class >= EVERGREEN) { + if (bc->gfx_level >= EVERGREEN) { if (tex->sampler_index_mode || tex->resource_index_mode) egcm_load_index_reg(bc, 1, false); } @@ -1574,7 +1574,7 @@ int r600_bytecode_add_gds(struct r600_bytecode *bc, const struct r600_bytecode_g return -ENOMEM; memcpy(ngds, gds, sizeof(struct r600_bytecode_gds)); - if (bc->chip_class >= EVERGREEN) { + if (bc->gfx_level >= EVERGREEN) { if (gds->uav_index_mode) egcm_load_index_reg(bc, gds->uav_index_mode - 1, false); } @@ -1629,7 +1629,7 @@ static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecod S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) | S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) | S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x); - if (bc->chip_class < CAYMAN) + if (bc->gfx_level < CAYMAN) bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count); id++; bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) | @@ -1644,9 +1644,9 @@ static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecod S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr); bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)| S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian); - if (bc->chip_class >= EVERGREEN) + if (bc->gfx_level >= EVERGREEN) bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode); - if (bc->chip_class < CAYMAN) + if (bc->gfx_level < CAYMAN) bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1); id++; bc->bytecode[id++] = 0; @@ -1662,7 +1662,7 @@ static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecod S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) | S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) | S_SQ_TEX_WORD0_SRC_REL(tex->src_rel); - if (bc->chip_class >= EVERGREEN) + if (bc->gfx_level >= EVERGREEN) bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode); ((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode) id++; @@ -1767,10 +1767,10 @@ static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) | S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) | S_SQ_CF_ALU_WORD1_BARRIER(1) | - S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) | + S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->gfx_level == R600 ? cf->r6xx_uses_waterfall : 0) | S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1); } else if (cfop->flags & CF_FETCH) { - if (bc->chip_class == R700) + if (bc->gfx_level == R700) r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf); else r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf); @@ -1851,7 +1851,7 @@ int r600_bytecode_build(struct r600_bytecode *bc) LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) { const struct cf_op_info *cfop = r600_isa_cf(cf->op); addr = cf->addr; - if (bc->chip_class >= EVERGREEN) + if (bc->gfx_level >= EVERGREEN) r = eg_bytecode_cf_build(bc, cf); else r = r600_bytecode_cf_build(bc, cf); @@ -1867,7 +1867,7 @@ int r600_bytecode_build(struct r600_bytecode *bc) r600_bytecode_alu_adjust_literals(alu, literal, nliteral); r600_bytecode_assign_kcache_banks(alu, cf->kcache); - switch(bc->chip_class) { + switch(bc->gfx_level) { case R600: r = r600_bytecode_alu_build(bc, alu, addr); break; @@ -1879,7 +1879,7 @@ int r600_bytecode_build(struct r600_bytecode *bc) r = eg_bytecode_alu_build(bc, alu, addr); break; default: - R600_ERR("unknown chip class %d.\n", bc->chip_class); + R600_ERR("unknown gfx level %d.\n", bc->gfx_level); return -EINVAL; } if (r) @@ -1901,7 +1901,7 @@ int r600_bytecode_build(struct r600_bytecode *bc) addr += 4; } } else if (cf->op == CF_OP_GDS) { - assert(bc->chip_class >= EVERGREEN); + assert(bc->gfx_level >= EVERGREEN); LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) { r = eg_bytecode_gds_build(bc, gds, addr); if (r) @@ -1910,7 +1910,7 @@ int r600_bytecode_build(struct r600_bytecode *bc) } } else if (cf->op == CF_OP_TEX) { LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) { - assert(bc->chip_class >= EVERGREEN); + assert(bc->gfx_level >= EVERGREEN); r = r600_bytecode_vtx_build(bc, vtx, addr); if (r) return r; @@ -2169,7 +2169,7 @@ void r600_bytecode_disasm(struct r600_bytecode *bc) unsigned nliteral; char chip = '6'; - switch (bc->chip_class) { + switch (bc->gfx_level) { case R700: chip = '7'; break; @@ -2459,10 +2459,10 @@ void r600_bytecode_disasm(struct r600_bytecode *bc) fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]); - if (bc->chip_class < CAYMAN && vtx->mega_fetch_count) + if (bc->gfx_level < CAYMAN && vtx->mega_fetch_count) fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count); - if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode) + if (bc->gfx_level >= EVERGREEN && vtx->buffer_index_mode) fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]); if (r600_isa_fetch(vtx->op)->flags & FF_MEM) { @@ -2710,7 +2710,7 @@ void *r600_create_vertex_fetch_shader(struct pipe_context *ctx, struct r600_bytecode bc; struct r600_bytecode_vtx vtx; const struct util_format_description *desc; - unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160; + unsigned fetch_resource_start = rctx->b.gfx_level >= EVERGREEN ? 0 : 160; unsigned format, num_format, format_comp, endian; uint32_t *bytecode; int i, j, r, fs_size; @@ -2722,14 +2722,14 @@ void *r600_create_vertex_fetch_shader(struct pipe_context *ctx, assert(count < 32); memset(&bc, 0, sizeof(bc)); - r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family, + r600_bytecode_init(&bc, rctx->b.gfx_level, rctx->b.family, rctx->screen->has_compressed_msaa_texturing); bc.isa = rctx->isa; for (i = 0; i < count; i++) { if (elements[i].instance_divisor > 1) { - if (rctx->b.chip_class == CAYMAN) { + if (rctx->b.gfx_level == CAYMAN) { for (j = 0; j < 4; j++) { struct r600_bytecode_alu alu; memset(&alu, 0, sizeof(alu)); diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h index 4590783592f..f7a24edbabc 100644 --- a/src/gallium/drivers/r600/r600_asm.h +++ b/src/gallium/drivers/r600/r600_asm.h @@ -254,7 +254,7 @@ struct r600_stack_info { }; struct r600_bytecode { - enum chip_class chip_class; + enum amd_gfx_level gfx_level; enum radeon_family family; bool has_compressed_msaa_texturing; int type; @@ -295,7 +295,7 @@ int eg_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id); /* r600_asm.c */ void r600_bytecode_init(struct r600_bytecode *bc, - enum chip_class chip_class, + enum amd_gfx_level gfx_level, enum radeon_family family, bool has_compressed_msaa_texturing); void r600_bytecode_clear(struct r600_bytecode *bc); diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index ddceebfeffe..5f386c9ff27 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -131,7 +131,7 @@ static void r600_blit_decompress_depth(struct pipe_context *ctx, /* XXX Decompressing MSAA depth textures is broken on R6xx. * There is also a hardlock if CMASK and FMASK are not present. * Just skip this until we find out how to fix it. */ - if (rctx->b.chip_class == R600 && max_sample > 0) { + if (rctx->b.gfx_level == R600 && max_sample > 0) { texture->dirty_level_mask = 0; return; } @@ -470,7 +470,7 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers, struct r600_context *rctx = (struct r600_context *)ctx; struct pipe_framebuffer_state *fb = &rctx->framebuffer.state; - if (buffers & PIPE_CLEAR_COLOR && rctx->b.chip_class >= EVERGREEN) { + if (buffers & PIPE_CLEAR_COLOR && rctx->b.gfx_level >= EVERGREEN) { evergreen_do_fast_color_clear(&rctx->b, fb, &rctx->framebuffer.atom, &buffers, NULL, color); if (!buffers) @@ -648,7 +648,7 @@ static void r600_clear_buffer(struct pipe_context *ctx, struct pipe_resource *ds struct r600_context *rctx = (struct r600_context*)ctx; if (rctx->screen->b.has_cp_dma && - rctx->b.chip_class >= EVERGREEN && + rctx->b.gfx_level >= EVERGREEN && offset % 4 == 0 && size % 4 == 0) { evergreen_cp_dma_clear_buffer(rctx, dst, offset, size, value, coher); } else if (rctx->screen->b.has_streamout && offset % 4 == 0 && size % 4 == 0) { @@ -796,7 +796,7 @@ void r600_resource_copy_region(struct pipe_context *ctx, dst->width0, dst->height0, dst_width, dst_height); - if (rctx->b.chip_class >= EVERGREEN) { + if (rctx->b.gfx_level >= EVERGREEN) { src_view = evergreen_create_sampler_view_custom(ctx, src, &src_templ, src_width0, src_height0, src_force_level); @@ -829,7 +829,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx, unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level); enum pipe_format format = info->src.format; unsigned sample_mask = - rctx->b.chip_class == CAYMAN ? ~0 : + rctx->b.gfx_level == CAYMAN ? ~0 : ((1ull << MAX2(1, info->src.resource->nr_samples)) - 1); struct pipe_resource *tmp, templ; struct pipe_blit_info blit; diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index b3446f93760..a73862db6ee 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -73,7 +73,7 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, } /* SX_MISC */ - if (ctx->b.chip_class == R600) { + if (ctx->b.gfx_level == R600) { num_dw += 3; } @@ -139,13 +139,13 @@ void r600_flush_emit(struct r600_context *rctx) } } - if (rctx->b.chip_class >= R700 && + if (rctx->b.gfx_level >= R700 && (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); } - if (rctx->b.chip_class >= R700 && + if (rctx->b.gfx_level >= R700 && (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_DB_META)) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); @@ -160,7 +160,7 @@ void r600_flush_emit(struct r600_context *rctx) } if (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV || - (rctx->b.chip_class == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) { + (rctx->b.gfx_level == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); } @@ -186,7 +186,7 @@ void r600_flush_emit(struct r600_context *rctx) /* Don't use the DB CP COHER logic on r6xx. * There are hw bugs. */ - if (rctx->b.chip_class >= R700 && + if (rctx->b.gfx_level >= R700 && (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_DB)) { cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1) | @@ -196,7 +196,7 @@ void r600_flush_emit(struct r600_context *rctx) /* Don't use the CB CP COHER logic on r6xx. * There are hw bugs. */ - if (rctx->b.chip_class >= R700 && + if (rctx->b.gfx_level >= R700 && (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_CB)) { cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) | S_0085F0_CB0_DEST_BASE_ENA(1) | @@ -208,14 +208,14 @@ void r600_flush_emit(struct r600_context *rctx) S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) | S_0085F0_SMX_ACTION_ENA(1); - if (rctx->b.chip_class >= EVERGREEN) + if (rctx->b.gfx_level >= EVERGREEN) cp_coher_cntl |= S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) | S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1); } - if (rctx->b.chip_class >= R700 && + if (rctx->b.gfx_level >= R700 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH) { cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) | S_0085F0_SO1_DEST_BASE_ENA(1) | @@ -285,7 +285,7 @@ void r600_context_gfx_flush(void *context, unsigned flags, if (ctx->trace_buf) eg_trace_emit(ctx); /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */ - if (ctx->b.chip_class == R600) { + if (ctx->b.gfx_level == R600) { radeon_set_context_reg(cs, R_028350_SX_MISC, 0); } @@ -356,7 +356,7 @@ void r600_begin_new_cs(struct r600_context *ctx) r600_mark_atom_dirty(ctx, &ctx->db_misc_state.atom); r600_mark_atom_dirty(ctx, &ctx->db_state.atom); r600_mark_atom_dirty(ctx, &ctx->framebuffer.atom); - if (ctx->b.chip_class >= EVERGREEN) { + if (ctx->b.gfx_level >= EVERGREEN) { r600_mark_atom_dirty(ctx, &ctx->fragment_images.atom); r600_mark_atom_dirty(ctx, &ctx->fragment_buffers.atom); r600_mark_atom_dirty(ctx, &ctx->compute_images.atom); @@ -371,7 +371,7 @@ void r600_begin_new_cs(struct r600_context *ctx) ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1; ctx->b.viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1; r600_mark_atom_dirty(ctx, &ctx->b.viewports.atom); - if (ctx->b.chip_class <= EVERGREEN) { + if (ctx->b.gfx_level <= EVERGREEN) { r600_mark_atom_dirty(ctx, &ctx->config_state.atom); } r600_mark_atom_dirty(ctx, &ctx->stencil_ref.atom); @@ -397,7 +397,7 @@ void r600_begin_new_cs(struct r600_context *ctx) if (ctx->rasterizer_state.cso) r600_mark_atom_dirty(ctx, &ctx->rasterizer_state.atom); - if (ctx->b.chip_class <= R700) { + if (ctx->b.gfx_level <= R700) { r600_mark_atom_dirty(ctx, &ctx->seamless_cube_map.atom); } @@ -438,7 +438,7 @@ void r600_emit_pfp_sync_me(struct r600_context *rctx) { struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; - if (rctx->b.chip_class >= EVERGREEN && + if (rctx->b.gfx_level >= EVERGREEN && rctx->b.screen->info.drm_minor >= 46) { radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); radeon_emit(cs, 0); @@ -565,7 +565,7 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx, } /* CP_DMA_CP_SYNC doesn't wait for idle on R6xx, but this does. */ - if (rctx->b.chip_class == R600) + if (rctx->b.gfx_level == R600) radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_CP_DMA_IDLE(1)); diff --git a/src/gallium/drivers/r600/r600_isa.c b/src/gallium/drivers/r600/r600_isa.c index 0a5c4dac101..49ee7834974 100644 --- a/src/gallium/drivers/r600/r600_isa.c +++ b/src/gallium/drivers/r600/r600_isa.c @@ -538,8 +538,8 @@ r600_isa_cf(unsigned op) { int r600_isa_init(struct r600_context *ctx, struct r600_isa *isa) { unsigned i; - assert(ctx->b.chip_class >= R600 && ctx->b.chip_class <= CAYMAN); - isa->hw_class = ctx->b.chip_class - R600; + assert(ctx->b.gfx_level >= R600 && ctx->b.gfx_level <= CAYMAN); + isa->hw_class = ctx->b.gfx_level - R600; /* reverse lookup maps are required for bytecode parsing */ diff --git a/src/gallium/drivers/r600/r600_isa.h b/src/gallium/drivers/r600/r600_isa.h index 1c098fbb187..41f2cbc5ddf 100644 --- a/src/gallium/drivers/r600/r600_isa.h +++ b/src/gallium/drivers/r600/r600_isa.h @@ -172,7 +172,7 @@ struct alu_op_info * (-1) if instruction doesn't exist (more precise info in "slots") */ int opcode[2]; /* slots for r6xx, r7xx, evergreen, cayman - * (0 if instruction doesn't exist for chip class) */ + * (0 if instruction doesn't exist for gfx level) */ int slots[4]; /* flags (mostly autogenerated from instruction name) */ unsigned int flags; @@ -182,7 +182,7 @@ struct alu_op_info struct fetch_op_info { const char * name; - /* for every chip class */ + /* for every gfx level */ int opcode[4]; int flags; }; @@ -191,7 +191,7 @@ struct fetch_op_info struct cf_op_info { const char * name; - /* for every chip class */ + /* for every gfx level */ int opcode[4]; int flags; }; @@ -697,29 +697,29 @@ const struct cf_op_info * r600_isa_cf(unsigned op); static inline unsigned -r600_isa_alu_opcode(enum r600_chip_class chip_class, unsigned op) { - int opc = r600_isa_alu(op)->opcode[chip_class >> 1]; +r600_isa_alu_opcode(enum r600_chip_class gfx_level, unsigned op) { + int opc = r600_isa_alu(op)->opcode[gfx_level >> 1]; assert(opc != -1); return opc; } static inline unsigned -r600_isa_alu_slots(enum r600_chip_class chip_class, unsigned op) { - unsigned slots = r600_isa_alu(op)->slots[chip_class]; +r600_isa_alu_slots(enum r600_chip_class gfx_level, unsigned op) { + unsigned slots = r600_isa_alu(op)->slots[gfx_level]; assert(slots != 0); return slots; } static inline unsigned -r600_isa_fetch_opcode(enum r600_chip_class chip_class, unsigned op) { - int opc = r600_isa_fetch(op)->opcode[chip_class]; +r600_isa_fetch_opcode(enum r600_chip_class gfx_level, unsigned op) { + int opc = r600_isa_fetch(op)->opcode[gfx_level]; assert(opc != -1); return opc; } static inline unsigned -r600_isa_cf_opcode(enum r600_chip_class chip_class, unsigned op) { - int opc = r600_isa_cf(op)->opcode[chip_class]; +r600_isa_cf_opcode(enum r600_chip_class gfx_level, unsigned op) { + int opc = r600_isa_cf(op)->opcode[gfx_level]; assert(opc != -1); return opc; } diff --git a/src/gallium/drivers/r600/r600_opcodes.h b/src/gallium/drivers/r600/r600_opcodes.h index b27e123c054..93dda44283a 100644 --- a/src/gallium/drivers/r600/r600_opcodes.h +++ b/src/gallium/drivers/r600/r600_opcodes.h @@ -503,8 +503,8 @@ #define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_EXPORT_COMBINED EG_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(0x0000005B) #define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT_COMBINED_CACHELESS EG_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(0x0000005C) -#define BC_INST(bc, x) ((bc)->chip_class >= EVERGREEN ? EG_##x : x) +#define BC_INST(bc, x) ((bc)->gfx_level >= EVERGREEN ? EG_##x : x) -#define CTX_INST(x) (ctx->bc->chip_class >= EVERGREEN ? EG_##x : x) +#define CTX_INST(x) (ctx->bc->gfx_level >= EVERGREEN ? EG_##x : x) #endif diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 0af98571084..d5f50b8b163 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -72,7 +72,7 @@ static void r600_destroy_context(struct pipe_context *context) r600_sb_context_destroy(rctx->sb_context); - for (sh = 0; sh < (rctx->b.chip_class < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) { + for (sh = 0; sh < (rctx->b.gfx_level < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) { r600_resource_reference(&rctx->scratch_buffers[sh].buffer, NULL); } r600_resource_reference(&rctx->dummy_cmask, NULL); @@ -169,13 +169,13 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, rctx->is_debug = true; r600_init_common_state_functions(rctx); - switch (rctx->b.chip_class) { + switch (rctx->b.gfx_level) { case R600: case R700: r600_init_state_functions(rctx); r600_init_atom_start_cs(rctx); rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); - rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx) + rctx->custom_blend_resolve = rctx->b.gfx_level == R700 ? r700_create_resolve_blend(rctx) : r600_create_resolve_blend(rctx); rctx->custom_blend_decompress = r600_create_decompress_blend(rctx); rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 || @@ -205,7 +205,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, PIPE_USAGE_DEFAULT, 32); break; default: - R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class); + R600_ERR("Unsupported gfx level %d.\n", rctx->b.gfx_level); goto fail; } @@ -339,7 +339,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr; case PIPE_CAP_COMPUTE: - return rscreen->b.chip_class > R700; + return rscreen->b.gfx_level > R700; case PIPE_CAP_TGSI_TEXCOORD: return 1; @@ -524,7 +524,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_UMA: return 0; case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: - return rscreen->b.chip_class >= R700; + return rscreen->b.gfx_level >= R700; case PIPE_CAP_PCI_GROUP: return rscreen->b.info.pci_domain; case PIPE_CAP_PCI_BUS: @@ -721,7 +721,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws, return NULL; } - if (rscreen->b.info.chip_class >= EVERGREEN) { + if (rscreen->b.info.gfx_level >= EVERGREEN) { rscreen->b.b.is_format_supported = evergreen_is_format_supported; } else { rscreen->b.b.is_format_supported = r600_is_format_supported; @@ -742,7 +742,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws, } /* Figure out streamout kernel support. */ - switch (rscreen->b.chip_class) { + switch (rscreen->b.gfx_level) { case R600: if (rscreen->b.family < CHIP_RS780) { rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14; @@ -763,7 +763,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws, } /* MSAA support. */ - switch (rscreen->b.chip_class) { + switch (rscreen->b.gfx_level) { case R600: case R700: rscreen->has_msaa = rscreen->b.info.drm_minor >= 22; diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 777f003e1ba..837a71f22f3 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -685,11 +685,11 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, unsigned force_level); void evergreen_init_common_regs(struct r600_context *ctx, struct r600_command_buffer *cb, - enum chip_class ctx_chip_class, + enum amd_gfx_level ctx_chip_class, enum radeon_family ctx_family, int ctx_drm_minor); void cayman_init_common_regs(struct r600_command_buffer *cb, - enum chip_class ctx_chip_class, + enum amd_gfx_level ctx_chip_class, enum radeon_family ctx_family, int ctx_drm_minor); @@ -851,7 +851,7 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format f const unsigned char *swizzle_view, uint32_t *word4_p, uint32_t *yuv_format_p, bool do_endian_swap); -uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format, +uint32_t r600_translate_colorformat(enum amd_gfx_level chip, enum pipe_format format, bool do_endian_swap); uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap); diff --git a/src/gallium/drivers/r600/r600_pipe_common.c b/src/gallium/drivers/r600/r600_pipe_common.c index 8d360fca86e..c6a1f042f5a 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.c +++ b/src/gallium/drivers/r600/r600_pipe_common.c @@ -217,7 +217,7 @@ static void r600_dma_emit_wait_idle(struct r600_common_context *rctx) { struct radeon_cmdbuf *cs = &rctx->dma.cs; - if (rctx->chip_class >= EVERGREEN) + if (rctx->gfx_level >= EVERGREEN) radeon_emit(cs, 0xf0000000); /* NOP */ else { /* TODO: R600-R700 should use the FENCE packet. @@ -586,7 +586,7 @@ bool r600_common_context_init(struct r600_common_context *rctx, rctx->screen = rscreen; rctx->ws = rscreen->ws; rctx->family = rscreen->family; - rctx->chip_class = rscreen->chip_class; + rctx->gfx_level = rscreen->gfx_level; rctx->b.invalidate_resource = r600_invalidate_resource; rctx->b.resource_commit = r600_resource_commit; @@ -604,7 +604,7 @@ bool r600_common_context_init(struct r600_common_context *rctx, /* evergreen_compute.c has a special codepath for global buffers. * Everything else can use the direct path. */ - if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) && + if ((rscreen->gfx_level == EVERGREEN || rscreen->gfx_level == CAYMAN) && (context_flags & PIPE_CONTEXT_COMPUTE_ONLY)) rctx->b.buffer_subdata = u_default_buffer_subdata; else @@ -912,7 +912,7 @@ static unsigned get_max_threads_per_block(struct r600_common_screen *screen, if (ir_type != PIPE_SHADER_IR_TGSI && ir_type != PIPE_SHADER_IR_NIR) return 256; - if (screen->chip_class >= EVERGREEN) + if (screen->gfx_level >= EVERGREEN) return 1024; return 256; } @@ -1257,7 +1257,7 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen, r600_init_screen_query_functions(rscreen); rscreen->family = rscreen->info.family; - rscreen->chip_class = rscreen->info.chip_class; + rscreen->gfx_level = rscreen->info.gfx_level; rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0); r600_disk_cache_create(rscreen); @@ -1281,7 +1281,7 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen, printf("pci_id = 0x%x\n", rscreen->info.pci_id); printf("family = %i (%s)\n", rscreen->info.family, r600_get_family_name(rscreen)); - printf("chip_class = %i\n", rscreen->info.chip_class); + printf("gfx_level = %i\n", rscreen->info.gfx_level); printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size); printf("gart_page_size = %u\n", rscreen->info.gart_page_size); printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024)); @@ -1364,13 +1364,13 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen, * lowered code */ rscreen->nir_options.lower_fpow = rscreen->debug_flags & DBG_NIR_PREFERRED; - if (rscreen->info.chip_class < EVERGREEN) { + if (rscreen->info.gfx_level < EVERGREEN) { /* Pre-EG doesn't have these ALU ops */ rscreen->nir_options.lower_bit_count = true; rscreen->nir_options.lower_bitfield_reverse = true; } - if (rscreen->info.chip_class < CAYMAN) { + if (rscreen->info.gfx_level < CAYMAN) { rscreen->nir_options.lower_doubles_options = nir_lower_fp64_full_software; rscreen->nir_options.lower_int64_options = ~0; } else { diff --git a/src/gallium/drivers/r600/r600_pipe_common.h b/src/gallium/drivers/r600/r600_pipe_common.h index 0ff827ef4c2..60560de69e4 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.h +++ b/src/gallium/drivers/r600/r600_pipe_common.h @@ -329,7 +329,7 @@ struct r600_common_screen { struct pipe_screen b; struct radeon_winsys *ws; enum radeon_family family; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; struct radeon_info info; uint64_t debug_flags; bool has_cp_dma; @@ -492,7 +492,7 @@ struct r600_common_context { struct radeon_winsys *ws; struct radeon_winsys_ctx *ctx; enum radeon_family family; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; struct r600_ring gfx; struct r600_ring dma; struct pipe_fence_handle *last_gfx_fence; diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c index 8d6ada94a76..9c8f916ae5f 100644 --- a/src/gallium/drivers/r600/r600_query.c +++ b/src/gallium/drivers/r600/r600_query.c @@ -655,7 +655,7 @@ static struct pipe_query *r600_query_hw_create(struct r600_common_screen *rscree break; case PIPE_QUERY_PIPELINE_STATISTICS: /* 11 values on EG, 8 on R600. */ - query->result_size = (rscreen->chip_class >= EVERGREEN ? 11 : 8) * 16; + query->result_size = (rscreen->gfx_level >= EVERGREEN ? 11 : 8) * 16; query->result_size += 8; /* for the fence + alignment */ query->num_cs_dw_begin = 6; query->num_cs_dw_end = 6 + r600_gfx_write_fence_dwords(rscreen); @@ -1232,7 +1232,7 @@ static void r600_query_hw_add_result(struct r600_common_screen *rscreen, } break; case PIPE_QUERY_PIPELINE_STATISTICS: - if (rscreen->chip_class >= EVERGREEN) { + if (rscreen->gfx_level >= EVERGREEN) { result->pipeline_statistics.ps_invocations += r600_query_read_result(buffer, 0, 22, false); result->pipeline_statistics.c_primitives += @@ -1849,7 +1849,7 @@ void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen) } max_rbs = ctx->screen->info.max_render_backends; - assert(rscreen->chip_class <= CAYMAN); + assert(rscreen->gfx_level <= CAYMAN); /* * if backend_map query is supported by the kernel. @@ -1859,12 +1859,12 @@ void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen) * (Albeit some chips with just one active rb can have a valid 0 map.) */ if (rscreen->info.r600_gb_backend_map_valid && - (ctx->chip_class < EVERGREEN || rscreen->info.r600_gb_backend_map != 0)) { + (ctx->gfx_level < EVERGREEN || rscreen->info.r600_gb_backend_map != 0)) { unsigned num_tile_pipes = rscreen->info.num_tile_pipes; unsigned backend_map = rscreen->info.r600_gb_backend_map; unsigned item_width, item_mask; - if (ctx->chip_class >= EVERGREEN) { + if (ctx->gfx_level >= EVERGREEN) { item_width = 4; item_mask = 0x7; } else { diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index de1181062eb..22aa41ff82b 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -343,7 +343,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx, evergreen_update_vs_state(ctx, shader); break; case PIPE_SHADER_GEOMETRY: - if (rctx->b.chip_class >= EVERGREEN) { + if (rctx->b.gfx_level >= EVERGREEN) { evergreen_update_gs_state(ctx, shader); evergreen_update_vs_state(ctx, shader->gs_copy_shader); } else { @@ -353,7 +353,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx, break; case PIPE_SHADER_VERTEX: export_shader = key.vs.as_es; - if (rctx->b.chip_class >= EVERGREEN) { + if (rctx->b.gfx_level >= EVERGREEN) { if (key.vs.as_ls) evergreen_update_ls_state(ctx, shader); else if (key.vs.as_es) @@ -368,7 +368,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx, } break; case PIPE_SHADER_FRAGMENT: - if (rctx->b.chip_class >= EVERGREEN) { + if (rctx->b.gfx_level >= EVERGREEN) { evergreen_update_ps_state(ctx, shader); } else { r600_update_ps_state(ctx, shader); @@ -834,7 +834,7 @@ static int single_alu_op2(struct r600_shader_ctx *ctx, int op, struct r600_bytecode_alu alu; int r, i; - if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) { + if (ctx->bc->gfx_level == CAYMAN && op == ALU_OP2_MULLO_INT) { for (i = 0; i < 4; i++) { memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = op; @@ -1117,7 +1117,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx) ctx->shader->ps_prim_id_input = i; break; } - if (ctx->bc->chip_class >= EVERGREEN) { + if (ctx->bc->gfx_level >= EVERGREEN) { if ((r = evergreen_interp_input(ctx, i))) return r; } @@ -1361,7 +1361,7 @@ static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_off inputs[1].enabled = true; } - if (ctx->bc->chip_class >= EVERGREEN) { + if (ctx->bc->gfx_level >= EVERGREEN) { int num_baryc = 0; /* assign gpr to each interpolator according to priority */ for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) { @@ -1638,7 +1638,7 @@ static void tgsi_src(struct r600_shader_ctx *ctx, r600_src->sel = reg; - if (ctx->bc->chip_class < R700) { + if (ctx->bc->gfx_level < R700) { struct r600_bytecode_output cf; memset(&cf, 0, sizeof(struct r600_bytecode_output)); @@ -1985,7 +1985,7 @@ static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_regi vtx.dst_sel_y = 1; /* SEL_Y */ vtx.dst_sel_z = 2; /* SEL_Z */ vtx.dst_sel_w = 3; /* SEL_W */ - if (ctx->bc->chip_class >= EVERGREEN) { + if (ctx->bc->gfx_level >= EVERGREEN) { vtx.use_const_fields = 1; } else { vtx.data_format = FMT_32_32_32_32_FLOAT; @@ -2501,7 +2501,7 @@ static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output output.array_size = 0xFFF; output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i]; - if (ctx->bc->chip_class >= EVERGREEN) { + if (ctx->bc->gfx_level >= EVERGREEN) { switch (so->output[i].output_buffer) { case 0: output.op = CF_OP_MEM_STREAM0_BUF0; @@ -2604,7 +2604,7 @@ int generate_gs_copy_shader(struct r600_context *rctx, ctx.bc = &ctx.shader->bc; ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX; - r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family, + r600_bytecode_init(ctx.bc, rctx->b.gfx_level, rctx->b.family, rctx->screen->has_compressed_msaa_texturing); ctx.bc->isa = rctx->isa; @@ -2649,7 +2649,7 @@ int generate_gs_copy_shader(struct r600_context *rctx, vtx.dst_sel_y = 1; vtx.dst_sel_z = 2; vtx.dst_sel_w = 3; - if (rctx->b.chip_class >= EVERGREEN) { + if (rctx->b.gfx_level >= EVERGREEN) { vtx.use_const_fields = 1; } else { vtx.data_format = FMT_32_32_32_32_FLOAT; @@ -2704,7 +2704,7 @@ int generate_gs_copy_shader(struct r600_context *rctx, } /* bc adds nops - copy it */ - if (ctx.bc->chip_class == R600) { + if (ctx.bc->gfx_level == R600) { memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = ALU_OP0_NOP; alu.last = 1; @@ -2870,7 +2870,7 @@ int generate_gs_copy_shader(struct r600_context *rctx, cf_pop->cf_addr = cf_pop->id + 2; cf_pop->pop_count = 1; - if (ctx.bc->chip_class == CAYMAN) + if (ctx.bc->gfx_level == CAYMAN) cm_bytecode_add_cf_end(ctx.bc); else { r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP); @@ -3460,7 +3460,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, ctx.bc = &shader->bc; ctx.shader = shader; - r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family, + r600_bytecode_init(ctx.bc, rscreen->b.gfx_level, rscreen->b.family, rscreen->has_compressed_msaa_texturing); ctx.tokens = tokens; tgsi_scan_shader(tokens, &ctx.info); @@ -3589,7 +3589,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS); } if (ctx.type == PIPE_SHADER_FRAGMENT) { - if (ctx.bc->chip_class >= EVERGREEN) + if (ctx.bc->gfx_level >= EVERGREEN) ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx); else ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]); @@ -3798,7 +3798,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, // Non LLVM path computes it later (in process_twoside_color) ctx.shader->input[ni].lds_pos = next_lds_loc++; ctx.shader->input[i].back_color_input = ni; - if (ctx.bc->chip_class >= EVERGREEN) { + if (ctx.bc->gfx_level >= EVERGREEN) { if ((r = evergreen_interp_input(&ctx, ni))) return r; } @@ -3807,7 +3807,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, } if (ctx.shader->uses_helper_invocation) { - if (ctx.bc->chip_class == CAYMAN) + if (ctx.bc->gfx_level == CAYMAN) r = cm_load_helper_invocation(&ctx); else r = eg_load_helper_invocation(&ctx); @@ -3865,7 +3865,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, } if (ctx.fragcoord_input >= 0) { - if (ctx.bc->chip_class == CAYMAN) { + if (ctx.bc->gfx_level == CAYMAN) { for (j = 0 ; j < 4; j++) { struct r600_bytecode_alu alu; memset(&alu, 0, sizeof(struct r600_bytecode_alu)); @@ -3901,7 +3901,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, int r; /* GS thread with no output workaround - emit a cut at start of GS */ - if (ctx.bc->chip_class == R600) + if (ctx.bc->gfx_level == R600) r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX); for (j = 0; j < 4; j++) { @@ -3980,9 +3980,9 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, if ((r = tgsi_split_lds_inputs(&ctx))) goto out_err; } - if (ctx.bc->chip_class == CAYMAN) + if (ctx.bc->gfx_level == CAYMAN) ctx.inst_info = &cm_shader_tgsi_instruction[opcode]; - else if (ctx.bc->chip_class >= EVERGREEN) + else if (ctx.bc->gfx_level >= EVERGREEN) ctx.inst_info = &eg_shader_tgsi_instruction[opcode]; else ctx.inst_info = &r600_shader_tgsi_instruction[opcode]; @@ -4219,7 +4219,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, if (shader->output[i].sid > shader->ps_export_highest) shader->ps_export_highest = shader->output[i].sid; - if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) { + if (shader->fs_write_all && (rscreen->b.gfx_level >= EVERGREEN)) { for (k = 1; k < max_color_exports; k++) { j++; memset(&output[j], 0, sizeof(struct r600_bytecode_output)); @@ -4346,7 +4346,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, } /* add program end */ - if (ctx.bc->chip_class == CAYMAN) + if (ctx.bc->gfx_level == CAYMAN) cm_bytecode_add_cf_end(ctx.bc); else { const struct cf_op_info *last = NULL; @@ -4978,7 +4978,7 @@ static int egcm_int_to_double(struct r600_shader_ctx *ctx) alu.dst.sel = temp_reg; alu.dst.chan = i; alu.dst.write = 1; - if (ctx->bc->chip_class == CAYMAN) + if (ctx->bc->gfx_level == CAYMAN) alu.last = i == dchan + 1; else alu.last = 1; /* trans only ops on evergreen */ @@ -5095,7 +5095,7 @@ static int cayman_emit_unary_double_raw(struct r600_bytecode *bc, alu.dst.chan = i; alu.dst.write = (i == 0 || i == 1); - if (bc->chip_class != CAYMAN || i == last_slot - 1) + if (bc->gfx_level != CAYMAN || i == last_slot - 1) alu.last = 1; r = r600_bytecode_add_alu(bc, &alu); if (r) @@ -5392,7 +5392,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx) alu.src[2].sel = V_SQ_ALU_SRC_LITERAL; alu.src[2].chan = 0; - if (ctx->bc->chip_class == R600) { + if (ctx->bc->gfx_level == R600) { alu.src[1].value = u_bitcast_f2u(2.0f * M_PI); alu.src[2].value = u_bitcast_f2u(-M_PI); } else { @@ -5544,7 +5544,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx) int sel; unsigned i; - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { for (i = 0; i < 3; i++) { /* tmp.z = log(tmp.x) */ memset(&alu, 0, sizeof(struct r600_bytecode_alu)); @@ -5597,7 +5597,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx) if (r) return r; - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { for (i = 0; i < 3; i++) { /* dst.z = exp(tmp.x) */ memset(&alu, 0, sizeof(struct r600_bytecode_alu)); @@ -5828,7 +5828,7 @@ static int emit_mul_int_op(struct r600_bytecode *bc, struct r600_bytecode_alu alu; int i, r; alu = *alu_src; - if (bc->chip_class == CAYMAN) { + if (bc->gfx_level == CAYMAN) { for (i = 0; i < 4; i++) { alu.dst.chan = i; alu.dst.write = (i == alu_src->dst.chan); @@ -6008,7 +6008,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op) } /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */ - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { /* tmp3.x = u2f(src2) */ memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = ALU_OP1_UINT_TO_FLT; @@ -7457,7 +7457,7 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_l if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx))) return r; - if (ctx->bc->chip_class >= EVERGREEN) + if (ctx->bc->gfx_level >= EVERGREEN) return 0; for (i = 0; i < 4; i++) { @@ -7517,7 +7517,7 @@ static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offs int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset; int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE - if (ctx->bc->chip_class < EVERGREEN) { + if (ctx->bc->gfx_level < EVERGREEN) { struct r600_bytecode_alu alu; memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = ALU_OP1_MOV; @@ -7610,12 +7610,12 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) { if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) { - if (ctx->bc->chip_class < EVERGREEN) + if (ctx->bc->gfx_level < EVERGREEN) ctx->shader->uses_tex_buffers = true; return r600_do_buffer_txq(ctx, 1, 0, R600_MAX_CONST_BUFFERS); } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) { - if (ctx->bc->chip_class < EVERGREEN) + if (ctx->bc->gfx_level < EVERGREEN) ctx->shader->uses_tex_buffers = true; return do_vtx_fetch_inst(ctx, src_requires_loading); } @@ -7624,7 +7624,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) { int out_chan; /* Add perspective divide */ - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { out_chan = 2; for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bytecode_alu)); @@ -7712,7 +7712,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) } /* tmp1.z = RCP_e(|tmp1.z|) */ - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = ALU_OP1_RECIP_IEEE; @@ -7812,7 +7812,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY || inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) { - if (ctx->bc->chip_class >= EVERGREEN) { + if (ctx->bc->gfx_level >= EVERGREEN) { int mytmp = r600_get_temp(ctx); memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = ALU_OP1_MOV; @@ -7875,7 +7875,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) r = r600_bytecode_add_alu(ctx->bc, &alu); if (r) return r; - } else if (ctx->bc->chip_class < EVERGREEN) { + } else if (ctx->bc->gfx_level < EVERGREEN) { memset(&tex, 0, sizeof(struct r600_bytecode_tex)); tex.op = FETCH_OP_SET_CUBEMAP_INDEX; tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg); @@ -8069,7 +8069,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) return r; /* coord.xy = -0.5 * (1.0/int_to_flt(size)) + coord.xy */ - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { /* */ for (i = 0; i < 2; i++) { memset(&alu, 0, sizeof(struct r600_bytecode_alu)); @@ -8372,7 +8372,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) alu.op = ALU_OP1_MOV; alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL; - if (ctx->bc->chip_class >= EVERGREEN) { + if (ctx->bc->gfx_level >= EVERGREEN) { /* with eg each dword is number of cubes */ alu.src[0].sel += id / 4; alu.src[0].chan = id % 4; @@ -8487,7 +8487,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) tex.inst_mod = texture_component_select; } - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; @@ -8598,7 +8598,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) array_index_offset_channel = tex.src_sel_z; } else if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY || inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) && - (ctx->bc->chip_class >= EVERGREEN)) + (ctx->bc->gfx_level >= EVERGREEN)) /* the array index is read from Z, coordinate will be corrected elsewhere */ tex.coord_type_z = 0; @@ -8683,7 +8683,7 @@ static int tgsi_set_gds_temp(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; int uav_id, uav_index_mode = 0; int r; - bool is_cm = (ctx->bc->chip_class == CAYMAN); + bool is_cm = (ctx->bc->gfx_level == CAYMAN); uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]); @@ -8732,7 +8732,7 @@ static int tgsi_load_gds(struct r600_shader_ctx *ctx) struct r600_bytecode_gds gds; int uav_id = 0; int uav_index_mode = 0; - bool is_cm = (ctx->bc->chip_class == CAYMAN); + bool is_cm = (ctx->bc->gfx_level == CAYMAN); r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode); if (r) @@ -9294,7 +9294,7 @@ static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx) memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = ALU_OP1_MOV; alu.dst.sel = ctx->thread_id_gpr; - if (ctx->bc->chip_class == CAYMAN) + if (ctx->bc->gfx_level == CAYMAN) alu.dst.chan = 2; else alu.dst.chan = 3; @@ -9415,7 +9415,7 @@ static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx) int r; int uav_id = 0; int uav_index_mode = 0; - bool is_cm = (ctx->bc->chip_class == CAYMAN); + bool is_cm = (ctx->bc->gfx_level == CAYMAN); if (gds_op == -1) { fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode); @@ -9598,7 +9598,7 @@ static int tgsi_resq(struct r600_shader_ctx *ctx) if (inst->Src[0].Register.File == TGSI_FILE_BUFFER || (inst->Src[0].Register.File == TGSI_FILE_IMAGE && inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) { - if (ctx->bc->chip_class < EVERGREEN) + if (ctx->bc->gfx_level < EVERGREEN) ctx->shader->uses_tex_buffers = true; unsigned eg_buffer_base = 0; eg_buffer_base = R600_IMAGE_REAL_RESOURCE_OFFSET; @@ -9868,7 +9868,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx) if (r) return r; - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { for (i = 0; i < 3; i++) { alu.op = ALU_OP1_EXP_IEEE; alu.src[0].sel = ctx->temp_reg; @@ -9922,7 +9922,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx) /* result.z = RoughApprox2ToX(tmp);*/ if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) { - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = ALU_OP1_EXP_IEEE; @@ -9984,7 +9984,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx) /* result.x = floor(log2(|src|)); */ if (inst->Dst[0].Register.WriteMask & 1) { - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bytecode_alu)); @@ -10036,7 +10036,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx) /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */ if ((inst->Dst[0].Register.WriteMask >> 1) & 1) { - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bytecode_alu)); @@ -10087,7 +10087,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx) if (r) return r; - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = ALU_OP1_EXP_IEEE; @@ -10121,7 +10121,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx) return r; } - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = ALU_OP1_RECIP_IEEE; @@ -10177,7 +10177,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx) /* result.z = log2(|src|);*/ if ((inst->Dst[0].Register.WriteMask >> 2) & 1) { - if (ctx->bc->chip_class == CAYMAN) { + if (ctx->bc->gfx_level == CAYMAN) { for (i = 0; i < 3; i++) { memset(&alu, 0, sizeof(struct r600_bytecode_alu)); @@ -10462,7 +10462,7 @@ static inline int callstack_update_max_depth(struct r600_shader_ctx *ctx, elements = (stack->loop + stack->push_wqm ) * entry_size; elements += stack->push; - switch (ctx->bc->chip_class) { + switch (ctx->bc->gfx_level) { case R600: case R700: /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on @@ -10640,10 +10640,10 @@ static int emit_if(struct r600_shader_ctx *ctx, int opcode, bool needs_workaround = false; int elems = callstack_push(ctx, FC_PUSH_VPM); - if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) + if (ctx->bc->gfx_level == CAYMAN && ctx->bc->stack.loop > 1) needs_workaround = true; - if (ctx->bc->chip_class == EVERGREEN && ctx_needs_stack_workaround_8xx(ctx)) { + if (ctx->bc->gfx_level == EVERGREEN && ctx_needs_stack_workaround_8xx(ctx)) { unsigned dmod1 = (elems - 1) % ctx->bc->stack.entry_size; unsigned dmod2 = (elems) % ctx->bc->stack.entry_size; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 144ef549be8..95f90d3b362 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -147,7 +147,7 @@ static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pi FALSE) != ~0U; } -static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format) +static bool r600_is_colorbuffer_format_supported(enum amd_gfx_level chip, enum pipe_format format) { return r600_translate_colorformat(chip, format, FALSE) != ~0U && r600_translate_colorswap(format, FALSE) != ~0U; @@ -181,7 +181,7 @@ bool r600_is_format_supported(struct pipe_screen *screen, return false; /* R11G11B10 is broken on R6xx. */ - if (rscreen->b.chip_class == R600 && + if (rscreen->b.gfx_level == R600 && format == PIPE_FORMAT_R11G11B10_FLOAT) return false; @@ -215,7 +215,7 @@ bool r600_is_format_supported(struct pipe_screen *screen, PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_BLENDABLE)) && - r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) { + r600_is_colorbuffer_format_supported(rscreen->b.gfx_level, format)) { retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | @@ -487,7 +487,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx, S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) | S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) | S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); - if (rctx->b.chip_class == R700) { + if (rctx->b.gfx_level == R700) { rs->pa_cl_clip_cntl |= S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard); } @@ -516,7 +516,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx, /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */ sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1); } - if (rctx->b.chip_class >= R700) { + if (rctx->b.gfx_level >= R700) { sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) | S_028A4C_R700_ZMM_LINE_OFFSET(1) | S_028A4C_R700_VPORT_SCISSOR_ENABLE(1); @@ -563,10 +563,10 @@ static void *r600_create_rs_state(struct pipe_context *ctx, state->fill_back != PIPE_POLYGON_MODE_FILL) | S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)); - if (rctx->b.chip_class == R700) { + if (rctx->b.gfx_level == R700) { r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl); } - if (rctx->b.chip_class == R600) { + if (rctx->b.gfx_level == R600) { r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard)); } @@ -880,7 +880,7 @@ static void r600_init_color_surface(struct r600_context *rctx, if (R600_BIG_ENDIAN) do_endian_swap = !rtex->db_compatible; - format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format, + format = r600_translate_colorformat(rctx->b.gfx_level, surf->base.format, do_endian_swap); assert(format != ~0); @@ -916,7 +916,7 @@ static void r600_init_color_surface(struct r600_context *rctx, /* EXPORT_NORM is an optimization that can be enabled for better * performance in certain cases */ - if (rctx->b.chip_class == R600) { + if (rctx->b.gfx_level == R600) { /* EXPORT_NORM can be enabled if: * - 11-bit or smaller UNORM/SNORM/SRGB * - BLEND_CLAMP is enabled @@ -1122,7 +1122,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, /* Colorbuffers. */ for (i = 0; i < state->nr_cbufs; i++) { /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */ - bool force_cmask_fmask = rctx->b.chip_class == R600 && + bool force_cmask_fmask = rctx->b.gfx_level == R600 && rctx->framebuffer.is_msaa_resolve && i == 1; @@ -1513,7 +1513,7 @@ static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples) rctx->ps_iter_samples = min_samples; if (rctx->framebuffer.nr_samples > 1) { r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom); - if (rctx->b.chip_class == R600) + if (rctx->b.gfx_level == R600) r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); } } @@ -1525,7 +1525,7 @@ static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) { radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); - if (rctx->b.chip_class == R600) { + if (rctx->b.gfx_level == R600) { radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */ radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */ } else { @@ -1578,7 +1578,7 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); - if (rctx->b.chip_class >= R700) { + if (rctx->b.gfx_level >= R700) { switch (a->ps_conservative_z) { default: /* fall through */ case TGSI_FS_DEPTH_LAYOUT_ANY: @@ -1595,7 +1595,7 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom if (rctx->b.num_occlusion_queries > 0 && !a->occlusion_queries_disabled) { - if (rctx->b.chip_class >= R700) { + if (rctx->b.gfx_level >= R700) { db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); } db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); @@ -1616,7 +1616,7 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom } else { db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE); } - if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) { + if (rctx->b.gfx_level == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) { /* sample shading and hyperz causes lockups on R6xx chips */ db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE); } @@ -1628,7 +1628,7 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom S_028D0C_COPY_CENTROID(1) | S_028D0C_COPY_SAMPLE(a->copy_sample); - if (rctx->b.chip_class == R600) + if (rctx->b.gfx_level == R600) db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 || @@ -2115,7 +2115,7 @@ void r600_init_atom_start_cs(struct r600_context *rctx) r600_init_command_buffer(cb, 256); /* R6xx requires this packet at the start of each command buffer */ - if (rctx->b.chip_class == R600) { + if (rctx->b.gfx_level == R600) { r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0)); r600_store_value(cb, 0); } @@ -2307,7 +2307,7 @@ void r600_init_atom_start_cs(struct r600_context *rctx) r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0); - if (rctx->b.chip_class >= R700) { + if (rctx->b.gfx_level >= R700) { r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4); r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000); r600_store_config_reg(cb, R_009830_DB_DEBUG, 0); @@ -2388,7 +2388,7 @@ void r600_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); - if (rctx->b.chip_class >= R700) { + if (rctx->b.gfx_level >= R700) { r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); } @@ -2421,9 +2421,9 @@ void r600_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0); - if (rctx->b.chip_class == R700) + if (rctx->b.gfx_level == R700) r600_store_context_reg(cb, R_028350_SX_MISC, 0); - if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout) + if (rctx->b.gfx_level == R700 && rctx->screen->b.has_streamout) r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf)); r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); @@ -2687,7 +2687,7 @@ void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *sha /* VGT_GS_MODE is written by r600_emit_shader_stages */ r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1); - if (rctx->b.chip_class >= R700) { + if (rctx->b.gfx_level >= R700) { r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT, S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices)); } diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 2c7b47807b2..0bd5eebfb73 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -87,7 +87,7 @@ void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom; unsigned alpha_ref = a->sx_alpha_ref; - if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) { + if (rctx->b.gfx_level >= EVERGREEN && a->cb0_export_16bpc) { alpha_ref &= ~0x1FFF; } @@ -209,7 +209,7 @@ static void r600_bind_blend_state_internal(struct r600_context *rctx, rctx->cb_misc_state.blend_colormask = blend->cb_target_mask; update_cb = true; } - if (rctx->b.chip_class <= R700 && + if (rctx->b.gfx_level <= R700 && rctx->cb_misc_state.cb_color_control != color_control) { rctx->cb_misc_state.cb_color_control = color_control; update_cb = true; @@ -354,7 +354,7 @@ static void r600_bind_dsa_state(struct pipe_context *ctx, void *state) ref.writemask[1] = dsa->writemask[1]; if (rctx->zwritemask != dsa->zwritemask) { rctx->zwritemask = dsa->zwritemask; - if (rctx->b.chip_class >= EVERGREEN) { + if (rctx->b.gfx_level >= EVERGREEN) { /* work around some issue when not writing to zbuffer * we are having lockup on evergreen so do not enable * hyperz when not writing zbuffer @@ -500,7 +500,7 @@ static void r600_bind_sampler_states(struct pipe_context *pipe, r600_sampler_states_dirty(rctx, &dst->states); /* Seamless cubemap state. */ - if (rctx->b.chip_class <= R700 && + if (rctx->b.gfx_level <= R700 && seamless_cube_map != -1 && seamless_cube_map != rctx->seamless_cube_map.enabled) { /* change in TA_CNTL_AUX need a pipeline flush */ @@ -560,7 +560,7 @@ static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state) void r600_vertex_buffers_dirty(struct r600_context *rctx) { if (rctx->vertex_buffer_state.dirty_mask) { - rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) * + rctx->vertex_buffer_state.atom.num_dw = (rctx->b.gfx_level >= EVERGREEN ? 12 : 11) * util_bitcount(rctx->vertex_buffer_state.dirty_mask); r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom); } @@ -632,7 +632,7 @@ void r600_sampler_views_dirty(struct r600_context *rctx, struct r600_samplerview_state *state) { if (state->dirty_mask) { - state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) * + state->atom.num_dw = (rctx->b.gfx_level >= EVERGREEN ? 14 : 13) * util_bitcount(state->dirty_mask); r600_mark_atom_dirty(rctx, &state->atom); } @@ -703,7 +703,7 @@ static void r600_set_sampler_views(struct pipe_context *pipe, /* Changing from array to non-arrays textures and vice versa requires * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */ - if (rctx->b.chip_class <= R700 && + if (rctx->b.gfx_level <= R700 && (dst->states.enabled_mask & (1 << i)) && (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) { @@ -1256,7 +1256,7 @@ static void r600_delete_tes_state(struct pipe_context *ctx, void *state) void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state) { if (state->dirty_mask) { - state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20 + state->atom.num_dw = rctx->b.gfx_level >= EVERGREEN ? util_bitcount(state->dirty_mask)*20 : util_bitcount(state->dirty_mask)*19; r600_mark_atom_dirty(rctx, &state->atom); } @@ -1977,7 +1977,7 @@ static bool r600_update_derived_state(struct r600_context *rctx) (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade) || (msaa != rctx->ps_shader->current->msaa)))) { - if (rctx->b.chip_class >= EVERGREEN) + if (rctx->b.gfx_level >= EVERGREEN) evergreen_update_ps_state(ctx, rctx->ps_shader->current); else r600_update_ps_state(ctx, rctx->ps_shader->current); @@ -1990,7 +1990,7 @@ static bool r600_update_derived_state(struct r600_context *rctx) r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom); } - if (rctx->b.chip_class <= R700) { + if (rctx->b.gfx_level <= R700) { bool multiwrite = rctx->ps_shader->current->shader.fs_write_all; if (rctx->cb_misc_state.multiwrite != multiwrite) { @@ -2003,14 +2003,14 @@ static bool r600_update_derived_state(struct r600_context *rctx) } UPDATE_SHADER(R600_HW_STAGE_PS, ps); - if (rctx->b.chip_class >= EVERGREEN) { + if (rctx->b.gfx_level >= EVERGREEN) { evergreen_update_db_shader_control(rctx); } else { r600_update_db_shader_control(rctx); } /* For each shader stage that needs to spill, set up buffer for MEM_SCRATCH */ - if (rctx->b.chip_class >= EVERGREEN) { + if (rctx->b.gfx_level >= EVERGREEN) { evergreen_setup_scratch_buffers(rctx); } else { r600_setup_scratch_buffers(rctx); @@ -2021,7 +2021,7 @@ static bool r600_update_derived_state(struct r600_context *rctx) if (rctx->ps_shader) { need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp; if (need_buf_const) { - if (rctx->b.chip_class < EVERGREEN) + if (rctx->b.gfx_level < EVERGREEN) r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT); else eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT); @@ -2031,7 +2031,7 @@ static bool r600_update_derived_state(struct r600_context *rctx) if (rctx->vs_shader) { need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp; if (need_buf_const) { - if (rctx->b.chip_class < EVERGREEN) + if (rctx->b.gfx_level < EVERGREEN) r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX); else eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX); @@ -2041,7 +2041,7 @@ static bool r600_update_derived_state(struct r600_context *rctx) if (rctx->gs_shader) { need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp; if (need_buf_const) { - if (rctx->b.chip_class < EVERGREEN) + if (rctx->b.gfx_level < EVERGREEN) r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY); else eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY); @@ -2049,7 +2049,7 @@ static bool r600_update_derived_state(struct r600_context *rctx) } if (rctx->tes_shader) { - assert(rctx->b.chip_class >= EVERGREEN); + assert(rctx->b.gfx_level >= EVERGREEN); need_buf_const = rctx->tes_shader->current->shader.uses_tex_buffers || rctx->tes_shader->current->shader.has_txq_cube_array_z_comp; if (need_buf_const) { @@ -2066,14 +2066,14 @@ static bool r600_update_derived_state(struct r600_context *rctx) r600_update_driver_const_buffers(rctx, false); - if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) { + if (rctx->b.gfx_level < EVERGREEN && rctx->ps_shader && rctx->vs_shader) { if (!r600_adjust_gprs(rctx)) { /* discard rendering */ return false; } } - if (rctx->b.chip_class == EVERGREEN) { + if (rctx->b.gfx_level == EVERGREEN) { if (!evergreen_adjust_gprs(rctx)) { /* discard rendering */ return false; @@ -2107,7 +2107,7 @@ void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom (state->clip_plane_enable & state->clip_dist_write) | (state->cull_dist_write << 8)); /* reuse needs to be set off if we write oViewport */ - if (rctx->b.chip_class >= EVERGREEN) + if (rctx->b.gfx_level >= EVERGREEN) radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, S_028AB4_REUSE_OFF(state->vs_out_viewport)); } @@ -2224,7 +2224,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info : (rctx->tes_shader)? rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] : info->mode; - if (rctx->b.chip_class >= EVERGREEN) { + if (rctx->b.gfx_level >= EVERGREEN) { evergreen_emit_atomic_buffer_setup_count(rctx, NULL, combined_atomics, &atomic_used_mask); } @@ -2309,12 +2309,12 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info } /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */ - if (rctx->b.chip_class == R600) { + if (rctx->b.gfx_level == R600) { rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH; r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom); } - if (rctx->b.chip_class >= EVERGREEN) + if (rctx->b.gfx_level >= EVERGREEN) evergreen_setup_tess_constants(rctx, info, &num_patches); /* Emit states. */ @@ -2326,11 +2326,11 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]); } - if (rctx->b.chip_class >= EVERGREEN) { + if (rctx->b.gfx_level >= EVERGREEN) { evergreen_emit_atomic_buffer_setup(rctx, false, combined_atomics, atomic_used_mask); } - if (rctx->b.chip_class == CAYMAN) { + if (rctx->b.gfx_level == CAYMAN) { /* Copied from radeonsi. */ unsigned primgroup_size = 128; /* recommended without a GS */ bool ia_switch_on_eop = false; @@ -2353,7 +2353,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1)); } - if (rctx->b.chip_class >= EVERGREEN) { + if (rctx->b.gfx_level >= EVERGREEN) { uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, info, num_patches); @@ -2363,7 +2363,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles, * even though it should have no effect on those. */ - if (rctx->b.chip_class == R600 && rctx->rasterizer) { + if (rctx->b.gfx_level == R600 && rctx->rasterizer) { unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl; unsigned prim = info->mode; @@ -2401,7 +2401,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info radeon_emit(cs, info->instance_count); } else { uint64_t va = r600_resource(indirect->buffer)->gpu_address; - assert(rctx->b.chip_class >= EVERGREEN); + assert(rctx->b.gfx_level >= EVERGREEN); // Invalidate so non-indirect draw calls reset this state rctx->vgt_state.last_draw_was_indirect = true; @@ -2513,13 +2513,13 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info } /* ES ring rolling over at EOP - workaround */ - if (rctx->b.chip_class == R600) { + if (rctx->b.gfx_level == R600) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT)); } - if (rctx->b.chip_class >= EVERGREEN) + if (rctx->b.gfx_level >= EVERGREEN) evergreen_emit_atomic_buffer_save(rctx, false, combined_atomics, &atomic_used_mask); if (rctx->trace_buf) @@ -2828,7 +2828,7 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen, goto out_word4; case PIPE_FORMAT_X8Z24_UNORM: case PIPE_FORMAT_S8_UINT_Z24_UNORM: - if (rscreen->b.chip_class < EVERGREEN) + if (rscreen->b.gfx_level < EVERGREEN) goto out_unknown; word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE); result = FMT_24_8; @@ -2853,7 +2853,7 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen, result = FMT_8_24; goto out_word4; case PIPE_FORMAT_S8X24_UINT: - if (rscreen->b.chip_class < EVERGREEN) + if (rscreen->b.gfx_level < EVERGREEN) goto out_unknown; word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE); @@ -2934,7 +2934,7 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen, } if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) { - if (rscreen->b.chip_class < EVERGREEN) + if (rscreen->b.gfx_level < EVERGREEN) goto out_unknown; switch (format) { @@ -3148,7 +3148,7 @@ out_unknown: return ~0; } -uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format, +uint32_t r600_translate_colorformat(enum amd_gfx_level chip, enum pipe_format format, bool do_endian_swap) { const struct util_format_description *desc = util_format_description(format); diff --git a/src/gallium/drivers/r600/r600_streamout.c b/src/gallium/drivers/r600/r600_streamout.c index 3c03d3e5e86..8b720d24aa2 100644 --- a/src/gallium/drivers/r600/r600_streamout.c +++ b/src/gallium/drivers/r600/r600_streamout.c @@ -158,7 +158,7 @@ static void r600_flush_vgt_streamout(struct r600_common_context *rctx) unsigned reg_strmout_cntl; /* The register is at different places on different ASICs. */ - if (rctx->chip_class >= EVERGREEN) { + if (rctx->gfx_level >= EVERGREEN) { reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL; } else { reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL; @@ -306,7 +306,7 @@ static void r600_emit_streamout_enable(struct r600_common_context *rctx, unsigned strmout_buffer_val = rctx->streamout.hw_enabled_mask & rctx->streamout.enabled_stream_buffers_mask; - if (rctx->chip_class >= EVERGREEN) { + if (rctx->gfx_level >= EVERGREEN) { strmout_buffer_reg = R_028B98_VGT_STRMOUT_BUFFER_CONFIG; strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG; diff --git a/src/gallium/drivers/r600/r600_test_dma.c b/src/gallium/drivers/r600/r600_test_dma.c index 50b78c9672b..c2c65ae0ba6 100644 --- a/src/gallium/drivers/r600/r600_test_dma.c +++ b/src/gallium/drivers/r600/r600_test_dma.c @@ -138,7 +138,7 @@ static enum pipe_format get_format_from_bpp(int bpp) static const char *array_mode_to_string(struct r600_common_screen *rscreen, struct radeon_surf *surf) { - if (rscreen->chip_class >= GFX9) { + if (rscreen->gfx_level >= GFX9) { /* TODO */ return " UNKNOWN"; } else { diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 2be8c90ebda..930e9b6dd9f 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -213,7 +213,7 @@ static int r600_init_surface(struct r600_common_screen *rscreen, is_depth = util_format_has_depth(desc); is_stencil = util_format_has_stencil(desc); - if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth && + if (rscreen->gfx_level >= EVERGREEN && !is_flushed_depth && ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { bpe = 4; /* stencil is allocated separately on evergreen */ } else { @@ -365,7 +365,7 @@ static void r600_reallocate_texture_inplace(struct r600_common_context *rctx, templ.bind |= new_bind_flag; /* r600g doesn't react to dirty_tex_descriptor_counter */ - if (rctx->chip_class < GFX6) + if (rctx->gfx_level < GFX6) return; if (rtex->resource.b.is_shared) @@ -630,7 +630,7 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen, /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption. * This can be fixed by writing a separate FMASK allocator specifically * for R600-R700 asics. */ - if (rscreen->chip_class <= R700) { + if (rscreen->gfx_level <= R700) { bpe *= 2; } @@ -756,12 +756,12 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen, rtex->surface.meta_size = 0; - if (rscreen->chip_class <= EVERGREEN && + if (rscreen->gfx_level <= EVERGREEN && rscreen->info.drm_minor < 26) return; /* HW bug on R6xx. */ - if (rscreen->chip_class == R600 && + if (rscreen->gfx_level == R600 && (rtex->resource.b.b.width0 > 7680 || rtex->resource.b.b.height0 > 7680)) return; @@ -933,7 +933,7 @@ r600_texture_create_object(struct pipe_screen *screen, if (rtex->is_depth) { if (base->flags & (R600_RESOURCE_FLAG_TRANSFER | R600_RESOURCE_FLAG_FLUSHED_DEPTH) || - rscreen->chip_class >= EVERGREEN) { + rscreen->gfx_level >= EVERGREEN) { rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted; rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted; } else { @@ -1043,7 +1043,7 @@ r600_choose_tiling(struct r600_common_screen *rscreen, return RADEON_SURF_MODE_LINEAR_ALIGNED; /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */ - if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN && + if (rscreen->gfx_level >= R600 && rscreen->gfx_level <= CAYMAN && (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) && (templ->target == PIPE_TEXTURE_2D || templ->target == PIPE_TEXTURE_3D)) @@ -1253,7 +1253,7 @@ static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen, const struct pipe_box *box) { /* r600g doesn't react to dirty_tex_descriptor_counter */ - return rscreen->chip_class >= GFX6 && + return rscreen->gfx_level >= GFX6 && !rtex->resource.b.is_shared && !(transfer_usage & PIPE_MAP_READ) && rtex->resource.b.b.last_level == 0 && diff --git a/src/gallium/drivers/r600/r600_uvd.c b/src/gallium/drivers/r600/r600_uvd.c index 18ac073da36..9c84b6380ba 100644 --- a/src/gallium/drivers/r600/r600_uvd.c +++ b/src/gallium/drivers/r600/r600_uvd.c @@ -81,7 +81,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe, vl_video_buffer_template(&templ, &template, resource_formats[0], 1, array_size, PIPE_USAGE_DEFAULT, 0, chroma_format); - if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING) + if (ctx->b.gfx_level < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING) templ.bind = PIPE_BIND_LINEAR; resources[0] = (struct r600_texture *) pipe->screen->resource_create(pipe->screen, &templ); @@ -91,7 +91,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe, if (resource_formats[1] != PIPE_FORMAT_NONE) { vl_video_buffer_template(&templ, &template, resource_formats[1], 1, array_size, PIPE_USAGE_DEFAULT, 1, chroma_format); - if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING) + if (ctx->b.gfx_level < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING) templ.bind = PIPE_BIND_LINEAR; resources[1] = (struct r600_texture *) pipe->screen->resource_create(pipe->screen, &templ); @@ -102,7 +102,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe, if (resource_formats[2] != PIPE_FORMAT_NONE) { vl_video_buffer_template(&templ, &template, resource_formats[2], 1, array_size, PIPE_USAGE_DEFAULT, 2, chroma_format); - if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING) + if (ctx->b.gfx_level < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING) templ.bind = PIPE_BIND_LINEAR; resources[2] = (struct r600_texture *) pipe->screen->resource_create(pipe->screen, &templ); diff --git a/src/gallium/drivers/r600/r600_viewport.c b/src/gallium/drivers/r600/r600_viewport.c index a8ed01a0c8e..6c51a78f6e5 100644 --- a/src/gallium/drivers/r600/r600_viewport.c +++ b/src/gallium/drivers/r600/r600_viewport.c @@ -48,7 +48,7 @@ #define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0 #define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4 -#define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192) +#define GET_MAX_SCISSOR(rctx) (rctx->gfx_level >= EVERGREEN ? 16384 : 8192) static void r600_set_scissor_states(struct pipe_context *ctx, unsigned start_slot, @@ -141,13 +141,13 @@ static void r600_scissor_make_union(struct r600_signed_scissor *out, void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx, struct pipe_scissor_state *scissor) { - if (rctx->chip_class == EVERGREEN || rctx->chip_class == CAYMAN) { + if (rctx->gfx_level == EVERGREEN || rctx->gfx_level == CAYMAN) { if (scissor->maxx == 0) scissor->minx = 1; if (scissor->maxy == 0) scissor->miny = 1; - if (rctx->chip_class == CAYMAN && + if (rctx->gfx_level == CAYMAN && scissor->maxx == 1 && scissor->maxy == 1) scissor->maxx = 2; } @@ -180,7 +180,7 @@ static void r600_emit_one_scissor(struct r600_common_context *rctx, } /* the range is [-MAX, MAX] */ -#define GET_MAX_VIEWPORT_RANGE(rctx) (rctx->chip_class >= EVERGREEN ? 32768 : 16384) +#define GET_MAX_VIEWPORT_RANGE(rctx) (rctx->gfx_level >= EVERGREEN ? 32768 : 16384) static void r600_emit_guardband(struct r600_common_context *rctx, struct r600_signed_scissor *vp_as_scissor) @@ -222,7 +222,7 @@ static void r600_emit_guardband(struct r600_common_context *rctx, guardband_y = MIN2(-top, bottom); /* If any of the GB registers is updated, all of them must be updated. */ - if (rctx->chip_class >= CAYMAN) + if (rctx->gfx_level >= CAYMAN) radeon_set_context_reg_seq(cs, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4); else radeon_set_context_reg_seq(cs, R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4); diff --git a/src/gallium/drivers/r600/sb/sb_context.cpp b/src/gallium/drivers/r600/sb/sb_context.cpp index 5dba85b8645..2734b24fe38 100644 --- a/src/gallium/drivers/r600/sb/sb_context.cpp +++ b/src/gallium/drivers/r600/sb/sb_context.cpp @@ -101,7 +101,7 @@ const char* sb_context::get_hw_class_name() { TRANSLATE_HW_CLASS(CAYMAN); #undef TRANSLATE_HW_CLASS default: - assert(!"unknown chip class"); + assert(!"unknown gfx level"); return "INVALID_CHIP_CLASS"; } } diff --git a/src/gallium/drivers/r600/sb/sb_core.cpp b/src/gallium/drivers/r600/sb/sb_core.cpp index a94d8d32b50..7c387d2a4a8 100644 --- a/src/gallium/drivers/r600/sb/sb_core.cpp +++ b/src/gallium/drivers/r600/sb/sb_core.cpp @@ -42,7 +42,7 @@ using namespace r600_sb; -static sb_hw_class translate_chip_class(enum chip_class cc); +static sb_hw_class translate_chip_class(enum amd_gfx_level cc); static sb_hw_chip translate_chip(enum radeon_family rf); sb_context *r600_sb_context_create(struct r600_context *rctx) { @@ -50,7 +50,7 @@ sb_context *r600_sb_context_create(struct r600_context *rctx) { sb_context *sctx = new sb_context(); if (sctx->init(rctx->isa, translate_chip(rctx->b.family), - translate_chip_class(rctx->b.chip_class))) { + translate_chip_class(rctx->b.gfx_level))) { delete sctx; sctx = NULL; } @@ -324,7 +324,7 @@ static sb_hw_chip translate_chip(enum radeon_family rf) { } } -static sb_hw_class translate_chip_class(enum chip_class cc) { +static sb_hw_class translate_chip_class(enum amd_gfx_level cc) { switch(cc) { case R600: return HW_CLASS_R600; case R700: return HW_CLASS_R700; @@ -332,7 +332,7 @@ static sb_hw_class translate_chip_class(enum chip_class cc) { case CAYMAN: return HW_CLASS_CAYMAN; default: - assert(!"unknown chip class"); + assert(!"unknown gfx level"); return HW_CLASS_UNKNOWN; } } diff --git a/src/gallium/drivers/r600/sfn/sfn_callstack.cpp b/src/gallium/drivers/r600/sfn/sfn_callstack.cpp index 681b89d8679..ce0a00aed2f 100644 --- a/src/gallium/drivers/r600/sfn/sfn_callstack.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_callstack.cpp @@ -90,7 +90,7 @@ int CallStack::update_max_depth(unsigned type) elements = (stack.loop + stack.push_wqm ) * entry_size; elements += stack.push; - switch (m_bc.chip_class) { + switch (m_bc.gfx_level) { case R600: case R700: /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on diff --git a/src/gallium/drivers/r600/sfn/sfn_emitinstruction.cpp b/src/gallium/drivers/r600/sfn/sfn_emitinstruction.cpp index 9a75cd18bee..ee603789807 100644 --- a/src/gallium/drivers/r600/sfn/sfn_emitinstruction.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_emitinstruction.cpp @@ -124,7 +124,7 @@ PValue EmitInstruction::create_register_from_nir_src(const nir_src& src, unsigne return m_proc.create_register_from_nir_src(src, swizzle); } -enum chip_class EmitInstruction::get_chip_class(void) const +enum amd_gfx_level EmitInstruction::get_chip_class(void) const { return m_proc.get_chip_class(); } diff --git a/src/gallium/drivers/r600/sfn/sfn_emitinstruction.h b/src/gallium/drivers/r600/sfn/sfn_emitinstruction.h index 09a6489b0a7..ba3c4982533 100644 --- a/src/gallium/drivers/r600/sfn/sfn_emitinstruction.h +++ b/src/gallium/drivers/r600/sfn/sfn_emitinstruction.h @@ -77,7 +77,7 @@ protected: const nir_variable *get_deref_location(const nir_src& v) const; - enum chip_class get_chip_class(void) const; + enum amd_gfx_level get_chip_class(void) const; PValue literal(uint32_t value); diff --git a/src/gallium/drivers/r600/sfn/sfn_ir_to_assembly.cpp b/src/gallium/drivers/r600/sfn/sfn_ir_to_assembly.cpp index 38cead78983..f97dba97c35 100644 --- a/src/gallium/drivers/r600/sfn/sfn_ir_to_assembly.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_ir_to_assembly.cpp @@ -147,7 +147,7 @@ bool AssemblyFromShaderLegacy::do_lower(const std::vector<InstructionBlock>& ir) else if (impl->m_bc->cf_last->op == CF_OP_CALL_FS) impl->m_bc->cf_last->op = CF_OP_NOP; - if (impl->m_shader->bc.chip_class != CAYMAN) + if (impl->m_shader->bc.gfx_level != CAYMAN) impl->m_bc->cf_last->end_of_program = 1; else cm_bytecode_add_cf_end(impl->m_bc); @@ -480,7 +480,7 @@ bool AssemblyFromShaderLegacyImpl::visit(const IfInstruction & if_instr) int elems = m_callstack.push(FC_PUSH_VPM); bool needs_workaround = false; - if (m_bc->chip_class == CAYMAN && m_bc->stack.loop > 1) + if (m_bc->gfx_level == CAYMAN && m_bc->stack.loop > 1) needs_workaround = true; if (m_bc->family != CHIP_HEMLOCK && @@ -717,7 +717,7 @@ bool AssemblyFromShaderLegacyImpl::visit(const FetchInstruction& fetch_instr) } } - bool use_tc = fetch_instr.use_tc() || (m_bc->chip_class == CAYMAN); + bool use_tc = fetch_instr.use_tc() || (m_bc->gfx_level == CAYMAN); if (!use_tc && vtx_fetch_results.find(fetch_instr.src().sel()) != vtx_fetch_results.end()) { @@ -1085,7 +1085,7 @@ AssemblyFromShaderLegacyImpl::emit_index_reg(const Value& addr, unsigned idx) if ((m_bc->cf_last->ndw>>1) >= 110) m_bc->force_add_cf = 1; - if (m_bc->chip_class != CAYMAN) { + if (m_bc->gfx_level != CAYMAN) { EAluOp idxop = idx ? op1_set_cf_idx1 : op1_set_cf_idx0; memset(&alu, 0, sizeof(alu)); diff --git a/src/gallium/drivers/r600/sfn/sfn_nir.cpp b/src/gallium/drivers/r600/sfn/sfn_nir.cpp index 98efdcb4c0b..46c10e40008 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir.cpp @@ -80,7 +80,7 @@ bool NirLowerInstruction::run(nir_shader *shader) ShaderFromNir::ShaderFromNir():sh(nullptr), - chip_class(CLASS_UNKNOWN), + gfx_level(CLASS_UNKNOWN), m_current_if_id(0), m_current_loop_id(0), scratch_size(0) @@ -89,35 +89,35 @@ ShaderFromNir::ShaderFromNir():sh(nullptr), bool ShaderFromNir::lower(const nir_shader *shader, r600_pipe_shader *pipe_shader, r600_pipe_shader_selector *sel, r600_shader_key& key, - struct r600_shader* gs_shader, enum chip_class _chip_class) + struct r600_shader* gs_shader, enum amd_gfx_level _chip_class) { sh = shader; - chip_class = _chip_class; + gfx_level = _chip_class; assert(sh); switch (shader->info.stage) { case MESA_SHADER_VERTEX: - impl.reset(new VertexShaderFromNir(pipe_shader, *sel, key, gs_shader, chip_class)); + impl.reset(new VertexShaderFromNir(pipe_shader, *sel, key, gs_shader, gfx_level)); break; case MESA_SHADER_TESS_CTRL: sfn_log << SfnLog::trans << "Start TCS\n"; - impl.reset(new TcsShaderFromNir(pipe_shader, *sel, key, chip_class)); + impl.reset(new TcsShaderFromNir(pipe_shader, *sel, key, gfx_level)); break; case MESA_SHADER_TESS_EVAL: sfn_log << SfnLog::trans << "Start TESS_EVAL\n"; - impl.reset(new TEvalShaderFromNir(pipe_shader, *sel, key, gs_shader, chip_class)); + impl.reset(new TEvalShaderFromNir(pipe_shader, *sel, key, gs_shader, gfx_level)); break; case MESA_SHADER_GEOMETRY: sfn_log << SfnLog::trans << "Start GS\n"; - impl.reset(new GeometryShaderFromNir(pipe_shader, *sel, key, chip_class)); + impl.reset(new GeometryShaderFromNir(pipe_shader, *sel, key, gfx_level)); break; case MESA_SHADER_FRAGMENT: sfn_log << SfnLog::trans << "Start FS\n"; - impl.reset(new FragmentShaderFromNir(*shader, pipe_shader->shader, *sel, key, chip_class)); + impl.reset(new FragmentShaderFromNir(*shader, pipe_shader->shader, *sel, key, gfx_level)); break; case MESA_SHADER_COMPUTE: sfn_log << SfnLog::trans << "Start CS\n"; - impl.reset(new ComputeShaderFromNir(pipe_shader, *sel, key, chip_class)); + impl.reset(new ComputeShaderFromNir(pipe_shader, *sel, key, gfx_level)); break; default: return false; @@ -813,7 +813,7 @@ int r600_shader_from_nir(struct r600_context *rctx, /* Cayman seems very crashy about accessing images that don't exists or are * accessed out of range, this lowering seems to help (but it can also be * another problem */ - if (sel->nir->info.num_images > 0 && rctx->b.chip_class == CAYMAN) + if (sel->nir->info.num_images > 0 && rctx->b.gfx_level == CAYMAN) NIR_PASS_V(sel->nir, r600_legalize_image_load_store); NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa); @@ -980,7 +980,7 @@ int r600_shader_from_nir(struct r600_context *rctx, gs_shader = &rctx->gs_shader->current->shader; r600_screen *rscreen = rctx->screen; - bool r = convert.lower(sh, pipeshader, sel, *key, gs_shader, rscreen->b.chip_class); + bool r = convert.lower(sh, pipeshader, sel, *key, gs_shader, rscreen->b.gfx_level); if (!r || rctx->screen->b.debug_flags & DBG_ALL_SHADERS) { static int shnr = 0; @@ -1002,7 +1002,7 @@ int r600_shader_from_nir(struct r600_context *rctx, auto shader = convert.shader(); - r600_bytecode_init(&pipeshader->shader.bc, rscreen->b.chip_class, rscreen->b.family, + r600_bytecode_init(&pipeshader->shader.bc, rscreen->b.gfx_level, rscreen->b.family, rscreen->has_compressed_msaa_texturing); r600::sfn_log << r600::SfnLog::shader_info diff --git a/src/gallium/drivers/r600/sfn/sfn_nir.h b/src/gallium/drivers/r600/sfn/sfn_nir.h index 4cec83314e4..ee9ace613f9 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir.h +++ b/src/gallium/drivers/r600/sfn/sfn_nir.h @@ -79,7 +79,7 @@ public: bool lower(const nir_shader *shader, r600_pipe_shader *sh, r600_pipe_shader_selector *sel, r600_shader_key &key, - r600_shader *gs_shader, enum chip_class chip_class); + r600_shader *gs_shader, enum amd_gfx_level gfx_level); bool process_declaration(); @@ -101,7 +101,7 @@ private: std::unique_ptr<ShaderFromNirProcessor> impl; const nir_shader *sh; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; int m_current_if_id; int m_current_loop_id; std::stack<int> m_if_stack; diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp index 3f8ef12db9f..a25b04b1620 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp @@ -59,14 +59,14 @@ using namespace std; ShaderFromNirProcessor::ShaderFromNirProcessor(pipe_shader_type ptype, r600_pipe_shader_selector& sel, r600_shader &sh_info, int scratch_size, - enum chip_class chip_class, + enum amd_gfx_level gfx_level, int atomic_base): m_processor_type(ptype), m_nesting_depth(0), m_block_number(0), m_export_output(0, -1), m_sh_info(sh_info), - m_chip_class(chip_class), + m_chip_class(gfx_level), m_tex_instr(*this), m_alu_instr(*this), m_ssbo_instr(*this), @@ -149,7 +149,7 @@ bool ShaderFromNirProcessor::scan_instruction(nir_instr *instr) return scan_sysvalue_access(instr); } -enum chip_class ShaderFromNirProcessor::get_chip_class(void) const +enum amd_gfx_level ShaderFromNirProcessor::get_chip_class(void) const { return m_chip_class; } diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_base.h b/src/gallium/drivers/r600/sfn/sfn_shader_base.h index df1eff42835..4fbf136a69b 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_base.h +++ b/src/gallium/drivers/r600/sfn/sfn_shader_base.h @@ -57,7 +57,7 @@ extern SfnLog sfn_log; class ShaderFromNirProcessor : public ValuePool { public: ShaderFromNirProcessor(pipe_shader_type ptype, r600_pipe_shader_selector& sel, - r600_shader& sh_info, int scratch_size, enum chip_class _chip_class, + r600_shader& sh_info, int scratch_size, enum amd_gfx_level _chip_class, int atomic_base); virtual ~ShaderFromNirProcessor(); @@ -84,7 +84,7 @@ public: const GPRVector *output_register(unsigned location) const; void evaluate_spi_sid(r600_shader_io &io); - enum chip_class get_chip_class() const; + enum amd_gfx_level get_chip_class() const; int remap_atomic_base(int base) { return m_atomic_base_map[base]; @@ -204,7 +204,7 @@ private: unsigned m_block_number; InstructionBlock m_export_output; r600_shader& m_sh_info; - enum chip_class m_chip_class; + enum amd_gfx_level m_chip_class; EmitTexInstruction m_tex_instr; EmitAluInstruction m_alu_instr; EmitSSBOInstruction m_ssbo_instr; diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_compute.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_compute.cpp index 7abb4144095..0977fe20721 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_compute.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_shader_compute.cpp @@ -32,9 +32,9 @@ namespace r600 { ComputeShaderFromNir::ComputeShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector& sel, UNUSED const r600_shader_key& key, - enum chip_class chip_class): + enum amd_gfx_level gfx_level): ShaderFromNirProcessor (PIPE_SHADER_COMPUTE, sel, sh->shader, - sh->scratch_space_needed, chip_class, 0), + sh->scratch_space_needed, gfx_level, 0), m_reserved_registers(0) { } diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_compute.h b/src/gallium/drivers/r600/sfn/sfn_shader_compute.h index b70cbad754a..98cbc637fc6 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_compute.h +++ b/src/gallium/drivers/r600/sfn/sfn_shader_compute.h @@ -39,7 +39,7 @@ public: ComputeShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector& sel, const r600_shader_key &key, - enum chip_class chip_class); + enum amd_gfx_level gfx_level); bool scan_sysvalue_access(nir_instr *instr) override; diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_fragment.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_fragment.cpp index aa46d4d967f..02d5adde543 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_fragment.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_shader_fragment.cpp @@ -35,8 +35,8 @@ FragmentShaderFromNir::FragmentShaderFromNir(const nir_shader& nir, r600_shader& sh, r600_pipe_shader_selector &sel, const r600_shader_key &key, - enum chip_class chip_class): - ShaderFromNirProcessor(PIPE_SHADER_FRAGMENT, sel, sh, nir.scratch_size, chip_class, 0), + enum amd_gfx_level gfx_level): + ShaderFromNirProcessor(PIPE_SHADER_FRAGMENT, sel, sh, nir.scratch_size, gfx_level, 0), m_max_color_exports(MAX2(key.ps.nr_cbufs,1)), m_max_counted_color_exports(0), m_two_sided_color(key.ps.color_two_side), diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_fragment.h b/src/gallium/drivers/r600/sfn/sfn_shader_fragment.h index 4755afbfef6..6c6fb2bf8d3 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_fragment.h +++ b/src/gallium/drivers/r600/sfn/sfn_shader_fragment.h @@ -37,7 +37,7 @@ class FragmentShaderFromNir : public ShaderFromNirProcessor { public: FragmentShaderFromNir(const nir_shader& nir, r600_shader& sh_info, r600_pipe_shader_selector &sel, const r600_shader_key &key, - enum chip_class chip_class); + enum amd_gfx_level gfx_level); bool scan_sysvalue_access(nir_instr *instr) override; private: diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_geometry.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_geometry.cpp index acc1125adc8..a0ab219d4d9 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_geometry.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_shader_geometry.cpp @@ -34,9 +34,9 @@ namespace r600 { GeometryShaderFromNir::GeometryShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector &sel, const r600_shader_key &key, - enum chip_class chip_class): + enum amd_gfx_level gfx_level): VertexStage(PIPE_SHADER_GEOMETRY, sel, sh->shader, - sh->scratch_space_needed, chip_class, key.gs.first_atomic_counter), + sh->scratch_space_needed, gfx_level, key.gs.first_atomic_counter), m_pipe_shader(sh), m_so_info(&sel.so), m_first_vertex_emitted(false), diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_geometry.h b/src/gallium/drivers/r600/sfn/sfn_shader_geometry.h index b557b8f5806..de7501c0ec9 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_geometry.h +++ b/src/gallium/drivers/r600/sfn/sfn_shader_geometry.h @@ -35,7 +35,7 @@ namespace r600 { class GeometryShaderFromNir : public VertexStage { public: - GeometryShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector& sel, const r600_shader_key& key, enum chip_class chip_class); + GeometryShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector& sel, const r600_shader_key& key, enum amd_gfx_level gfx_level); bool scan_sysvalue_access(nir_instr *instr) override; PValue primitive_id() override {return m_primitive_id;} diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_tcs.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_tcs.cpp index fb76695c6fe..d26f24d27cd 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_tcs.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_shader_tcs.cpp @@ -7,9 +7,9 @@ namespace r600 { TcsShaderFromNir::TcsShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector& sel, const r600_shader_key& key, - enum chip_class chip_class): + enum amd_gfx_level gfx_level): ShaderFromNirProcessor (PIPE_SHADER_TESS_CTRL, sel, sh->shader, - sh->scratch_space_needed, chip_class, key.tcs.first_atomic_counter), + sh->scratch_space_needed, gfx_level, key.tcs.first_atomic_counter), m_reserved_registers(0) { sh_info().tcs_prim_mode = key.tcs.prim_mode; diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_tcs.h b/src/gallium/drivers/r600/sfn/sfn_shader_tcs.h index 05107810488..886791eaef5 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_tcs.h +++ b/src/gallium/drivers/r600/sfn/sfn_shader_tcs.h @@ -8,7 +8,7 @@ namespace r600 { class TcsShaderFromNir : public ShaderFromNirProcessor { public: - TcsShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector& sel, const r600_shader_key& key, enum chip_class chip_class); + TcsShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector& sel, const r600_shader_key& key, enum amd_gfx_level gfx_level); bool scan_sysvalue_access(nir_instr *instr) override; private: diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_tess_eval.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_tess_eval.cpp index d1c75515a9b..20a3f85328b 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_tess_eval.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_shader_tess_eval.cpp @@ -5,9 +5,9 @@ namespace r600 { TEvalShaderFromNir::TEvalShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector& sel, const r600_shader_key& key, r600_shader *gs_shader, - enum chip_class chip_class): + enum amd_gfx_level gfx_level): VertexStage(PIPE_SHADER_TESS_EVAL, sel, sh->shader, - sh->scratch_space_needed, chip_class, key.tes.first_atomic_counter), + sh->scratch_space_needed, gfx_level, key.tes.first_atomic_counter), m_reserved_registers(0), m_key(key) diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_tess_eval.h b/src/gallium/drivers/r600/sfn/sfn_shader_tess_eval.h index a1b7d3a9cb0..4ae572ff12e 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_tess_eval.h +++ b/src/gallium/drivers/r600/sfn/sfn_shader_tess_eval.h @@ -11,7 +11,7 @@ class TEvalShaderFromNir : public VertexStage public: TEvalShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector& sel, const r600_shader_key& key, r600_shader *gs_shader, - enum chip_class chip_class); + enum amd_gfx_level gfx_level); bool scan_sysvalue_access(nir_instr *instr) override; PValue primitive_id() override {return m_primitive_id;} private: diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_vertex.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_vertex.cpp index f2c4de3fa68..dbce6f9d5c4 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_vertex.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_shader_vertex.cpp @@ -41,9 +41,9 @@ VertexShaderFromNir::VertexShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector& sel, const r600_shader_key& key, struct r600_shader* gs_shader, - enum chip_class chip_class): + enum amd_gfx_level gfx_level): VertexStage(PIPE_SHADER_VERTEX, sel, sh->shader, - sh->scratch_space_needed, chip_class, key.vs.first_atomic_counter), + sh->scratch_space_needed, gfx_level, key.vs.first_atomic_counter), m_num_clip_dist(0), m_last_param_export(nullptr), m_last_pos_export(nullptr), diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_vertex.h b/src/gallium/drivers/r600/sfn/sfn_shader_vertex.h index c1ba251deb9..a6577c2e456 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_vertex.h +++ b/src/gallium/drivers/r600/sfn/sfn_shader_vertex.h @@ -37,7 +37,7 @@ public: VertexShaderFromNir(r600_pipe_shader *sh, r600_pipe_shader_selector &sel, const r600_shader_key &key, r600_shader *gs_shader, - enum chip_class chip_class); + enum amd_gfx_level gfx_level); bool scan_sysvalue_access(nir_instr *instr) override; diff --git a/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py b/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py index 9f545235e5f..086bbd02f5d 100755 --- a/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py +++ b/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py @@ -213,7 +213,7 @@ env["WAFFLE_GBM_DEVICE"] = available_gpus[args.gpu][0] # Use piglit's glinfo to determine the GPU name gpu_name = "unknown" gpu_name_full = "" -chip_class = -1 +gfx_level = -1 env["AMD_DEBUG"] = "info" p = subprocess.run( @@ -230,8 +230,8 @@ for line in p.stdout.decode().split("\n"): gpu_name_full = "(".join(line.split("(")[:-1]).strip() gpu_name = line.replace("(TM)", "").split("(")[1].split(",")[0].lower() break - elif "chip_class" in line: - chip_class = int(line.split("=")[1]) + elif "gfx_level" in line: + gfx_level = int(line.split("=")[1]) output_folder = args.output_folder print_green("Tested GPU: '{}' ({}) {}".format(gpu_name_full, gpu_name, gpu_device)) @@ -251,7 +251,7 @@ logfile = open(os.path.join(output_folder, "{}-run-tests.log".format(gpu_name)), spin = itertools.cycle("-\\|/") -def chip_class_to_str(cl): +def gfx_level_to_str(cl): supported = ["gfx6", "gfx7", "gfx8", "gfx9", "gfx10", "gfx10_3", "gfx11"] if 8 <= cl and cl < 8 + len(supported): return supported[cl - 8] @@ -320,31 +320,31 @@ def parse_test_filters(include_tests): return cmd -def select_baseline(basepath, chip_class, gpu_name): - chip_class_str = chip_class_to_str(chip_class) +def select_baseline(basepath, gfx_level, gpu_name): + gfx_level_str = gfx_level_to_str(gfx_level) # select the best baseline we can find # 1. exact match - exact = os.path.join(base, "{}-{}-fail.csv".format(chip_class_str, gpu_name)) + exact = os.path.join(base, "{}-{}-fail.csv".format(gfx_level_str, gpu_name)) if os.path.exists(exact): return exact - # 2. any baseline with the same chip_class - while chip_class >= 8: + # 2. any baseline with the same gfx_level + while gfx_level >= 8: for subdir, dirs, files in os.walk(basepath): for file in files: - if file.find(chip_class_str) == 0 and file.endswith("-fail.csv"): + if file.find(gfx_level_str) == 0 and file.endswith("-fail.csv"): return os.path.join(base, file) # No match. Try an earlier class - chip_class = chip_class - 1 - chip_class_str = chip_class_to_str(chip_class) + gfx_level = gfx_level - 1 + gfx_level_str = gfx_level_to_str(gfx_level) return exact filters_args = parse_test_filters(args.include_tests) -baseline = select_baseline(base, chip_class, gpu_name) +baseline = select_baseline(base, gfx_level, gpu_name) flakes = os.path.join( - base, "{}-{}-flakes.csv".format(chip_class_to_str(chip_class), gpu_name) + base, "{}-{}-flakes.csv".format(gfx_level_to_str(gfx_level), gpu_name) ) if os.path.exists(baseline): diff --git a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c index 1f0bfce52f8..05034684ee0 100644 --- a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c +++ b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c @@ -1339,7 +1339,7 @@ void gfx10_ngg_culling_build_end(struct si_shader_context *ctx) ret = LLVMBuildInsertValue(ctx->ac.builder, ret, new_merged_wave_info, 3, ""); if (ctx->stage == MESA_SHADER_TESS_EVAL) ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 4); - if (ctx->ac.chip_class >= GFX11) + if (ctx->ac.gfx_level >= GFX11) ret = si_insert_input_ret(ctx, ret, ctx->args.gs_attr_offset, 5); ret = si_insert_input_ptr(ctx, ret, ctx->internal_bindings, 8 + SI_SGPR_INTERNAL_BINDINGS); @@ -1349,7 +1349,7 @@ void gfx10_ngg_culling_build_end(struct si_shader_context *ctx) 8 + SI_SGPR_CONST_AND_SHADER_BUFFERS); ret = si_insert_input_ptr(ctx, ret, ctx->samplers_and_images, 8 + SI_SGPR_SAMPLERS_AND_IMAGES); ret = si_insert_input_ptr(ctx, ret, ctx->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS); - if (ctx->ac.chip_class >= GFX11) + if (ctx->ac.gfx_level >= GFX11) ret = si_insert_input_ptr(ctx, ret, ctx->gs_attr_address, 8 + GFX9_SGPR_ATTRIBUTE_RING_ADDR); if (ctx->stage == MESA_SHADER_VERTEX) { @@ -2282,7 +2282,7 @@ bool gfx10_ngg_calculate_subgroup_info(struct si_shader *shader) /* All these are per subgroup: */ const unsigned min_esverts = - gs_sel->screen->info.chip_class >= GFX10_3 ? 29 : (24 - 1 + max_verts_per_prim); + gs_sel->screen->info.gfx_level >= GFX10_3 ? 29 : (24 - 1 + max_verts_per_prim); bool max_vert_out_per_gs_instance = false; unsigned max_gsprims_base = gs_sel->screen->ngg_subgroup_size; /* default prim group size clamp */ unsigned max_esverts_base = gs_sel->screen->ngg_subgroup_size; diff --git a/src/gallium/drivers/radeonsi/radeon_uvd_enc.c b/src/gallium/drivers/radeonsi/radeon_uvd_enc.c index bd08bc9e8af..07b75fa7743 100644 --- a/src/gallium/drivers/radeonsi/radeon_uvd_enc.c +++ b/src/gallium/drivers/radeonsi/radeon_uvd_enc.c @@ -321,7 +321,7 @@ struct pipe_video_codec *radeon_uvd_create_encoder(struct pipe_context *context, get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf); - cpb_size = (sscreen->info.chip_class < GFX9) + cpb_size = (sscreen->info.gfx_level < GFX9) ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * align(tmp_surf->u.legacy.level[0].nblk_y, 32) : align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * diff --git a/src/gallium/drivers/radeonsi/radeon_uvd_enc_1_1.c b/src/gallium/drivers/radeonsi/radeon_uvd_enc_1_1.c index 5d420d04a11..7678e954b8f 100644 --- a/src/gallium/drivers/radeonsi/radeon_uvd_enc_1_1.c +++ b/src/gallium/drivers/radeonsi/radeon_uvd_enc_1_1.c @@ -756,7 +756,7 @@ static void radeon_uvd_enc_ctx(struct radeon_uvd_encoder *enc) struct si_screen *sscreen = (struct si_screen *)enc->screen; enc->enc_pic.ctx_buf.swizzle_mode = 0; - if (sscreen->info.chip_class < GFX9) { + if (sscreen->info.gfx_level < GFX9) { enc->enc_pic.ctx_buf.rec_luma_pitch = (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); enc->enc_pic.ctx_buf.rec_chroma_pitch = (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); @@ -874,7 +874,7 @@ static void radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc) } enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size; - if (sscreen->info.chip_class < GFX9) { + if (sscreen->info.gfx_level < GFX9) { enc->enc_pic.enc_params.input_pic_luma_pitch = (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); enc->enc_pic.enc_params.input_pic_chroma_pitch = @@ -897,7 +897,7 @@ static void radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc) RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type); RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size); - if (sscreen->info.chip_class < GFX9) { + if (sscreen->info.gfx_level < GFX9) { RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); } else { diff --git a/src/gallium/drivers/radeonsi/radeon_vce.c b/src/gallium/drivers/radeonsi/radeon_vce.c index d8e853d0a09..74fce82d09e 100644 --- a/src/gallium/drivers/radeonsi/radeon_vce.c +++ b/src/gallium/drivers/radeonsi/radeon_vce.c @@ -219,7 +219,7 @@ void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot, s struct si_screen *sscreen = (struct si_screen *)enc->screen; unsigned pitch, vpitch, fsize; - if (sscreen->info.chip_class < GFX9) { + if (sscreen->info.gfx_level < GFX9) { pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128); vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16); } else { @@ -449,7 +449,7 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context, get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf); - cpb_size = (sscreen->info.chip_class < GFX9) + cpb_size = (sscreen->info.gfx_level < GFX9) ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * align(tmp_surf->u.legacy.level[0].nblk_y, 32) : diff --git a/src/gallium/drivers/radeonsi/radeon_vce_52.c b/src/gallium/drivers/radeonsi/radeon_vce_52.c index 5dc6f733a38..b52e3ee6264 100644 --- a/src/gallium/drivers/radeonsi/radeon_vce_52.c +++ b/src/gallium/drivers/radeonsi/radeon_vce_52.c @@ -190,7 +190,7 @@ static void create(struct rvce_encoder *enc) RVCE_CS(enc->base.width); // encImageWidth RVCE_CS(enc->base.height); // encImageHeight - if (sscreen->info.chip_class < GFX9) { + if (sscreen->info.gfx_level < GFX9) { RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw @@ -261,7 +261,7 @@ static void encode(struct rvce_encoder *enc) RVCE_CS(enc->enc_pic.eo.end_of_sequence); RVCE_CS(enc->enc_pic.eo.end_of_stream); - if (sscreen->info.chip_class < GFX9) { + if (sscreen->info.gfx_level < GFX9) { RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_dec.c b/src/gallium/drivers/radeonsi/radeon_vcn_dec.c index 8df5b2989ab..cd4158f4d7b 100755 --- a/src/gallium/drivers/radeonsi/radeon_vcn_dec.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_dec.c @@ -2770,7 +2770,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context, dec->ws = ws; if (u_reduce_video_profile(templ->profile) != PIPE_VIDEO_FORMAT_JPEG && - sctx->chip_class >= GFX11) + sctx->gfx_level >= GFX11) dec->vcn_dec_sw_ring = true; if (!ws->cs_create(&dec->cs, sctx->ctx, ring, NULL, NULL, false)) { diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c index 242a4b8c5f1..b02bda50395 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c @@ -477,7 +477,7 @@ static void radeon_enc_get_feedback(struct pipe_video_codec *encoder, void *feed } static int setup_dpb(struct radeon_encoder *enc, enum pipe_format buffer_format, - enum chip_class chip_class) + enum amd_gfx_level gfx_level) { uint32_t aligned_width = align(enc->base.width, 16); uint32_t aligned_height = align(enc->base.height, 16); @@ -494,7 +494,7 @@ static int setup_dpb(struct radeon_encoder *enc, enum pipe_format buffer_format, int i; for (i = 0; i < num_reconstructed_pictures; i++) { - if (chip_class >= GFX11) { + if (gfx_level >= GFX11) { enc->enc_pic.ctx_buf.reconstructed_pictures_v4_0[i].luma_offset = offset; offset += luma_size; enc->enc_pic.ctx_buf.reconstructed_pictures_v4_0[i].chroma_offset = offset; @@ -572,7 +572,7 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context, get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf); - cpb_size = (sscreen->info.chip_class < GFX9) + cpb_size = (sscreen->info.gfx_level < GFX9) ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * align(tmp_surf->u.legacy.level[0].nblk_y, 32) : align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * @@ -582,14 +582,14 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context, cpb_size = cpb_size * enc->cpb_num; tmp_buf->destroy(tmp_buf); - cpb_size += setup_dpb(enc, templat.buffer_format, sscreen->info.chip_class); + cpb_size += setup_dpb(enc, templat.buffer_format, sscreen->info.gfx_level); if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) { RVID_ERR("Can't create CPB buffer.\n"); goto error; } - if (sscreen->info.chip_class >= GFX11) + if (sscreen->info.gfx_level >= GFX11) radeon_enc_4_0_init(enc); else if (sscreen->info.family >= CHIP_SIENNA_CICHLID) radeon_enc_3_0_init(enc); diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index 25a897985ff..cbf4e63a890 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -99,7 +99,7 @@ void si_blitter_end(struct si_context *sctx) * non-global VS user SGPRs. */ sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX); - if (sctx->chip_class >= GFX11) + if (sctx->gfx_level >= GFX11) sctx->gs_attribute_ring_pointer_dirty = true; /* Reset SI_SGPR_SMALL_PRIM_CULL_INFO: */ @@ -451,7 +451,7 @@ static void si_blit_decompress_color(struct si_context *sctx, struct si_texture goto expand_fmask; /* No color decompression is needed on GFX11. */ - assert(sctx->chip_class < GFX11 || need_dcc_decompress); + assert(sctx->gfx_level < GFX11 || need_dcc_decompress); if (unlikely(sctx->log)) u_log_printf(sctx->log, @@ -460,7 +460,7 @@ static void si_blit_decompress_color(struct si_context *sctx, struct si_texture first_level, last_level, level_mask); if (need_dcc_decompress) { - assert(sctx->chip_class == GFX8 || tex->buffer.b.b.nr_storage_samples >= 2); + assert(sctx->gfx_level == GFX8 || tex->buffer.b.b.nr_storage_samples >= 2); custom_blend = sctx->custom_blend_dcc_decompress; assert(vi_dcc_enabled(tex, first_level)); @@ -540,7 +540,7 @@ static void si_blit_decompress_color(struct si_context *sctx, struct si_texture expand_fmask: if (need_fmask_expand && tex->surface.fmask_offset && !tex->fmask_is_identity) { - assert(sctx->chip_class < GFX11); /* no FMASK on gfx11 */ + assert(sctx->gfx_level < GFX11); /* no FMASK on gfx11 */ si_compute_expand_fmask(&sctx->b, &tex->buffer.b.b); tex->fmask_is_identity = true; } @@ -804,7 +804,7 @@ void si_decompress_textures(struct si_context *sctx, unsigned shader_mask) } } - if (sctx->chip_class == GFX10_3 && need_flush) { + if (sctx->gfx_level == GFX10_3 && need_flush) { /* This fixes a corruption with the following sequence: * - fast clear depth * - decompress depth @@ -903,7 +903,7 @@ static bool si_can_use_compute_blit(struct si_context *sctx, enum pipe_format fo return false; /* Image stores support DCC since GFX10. */ - if (has_dcc && is_store && sctx->chip_class < GFX10) + if (has_dcc && is_store && sctx->gfx_level < GFX10) return false; return true; @@ -1168,7 +1168,7 @@ resolve_to_temp: SI_RESOURCE_FLAG_DISABLE_DCC | SI_RESOURCE_FLAG_DRIVER_INTERNAL; /* The src and dst microtile modes must be the same. */ - if (sctx->chip_class <= GFX8 && src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY) + if (sctx->gfx_level <= GFX8 && src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY) templ.bind = PIPE_BIND_SCANOUT; else templ.bind = 0; @@ -1206,11 +1206,11 @@ static void si_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) /* Gfx11 doesn't have CB_RESOLVE. */ /* TODO: Use compute-based resolving instead. */ - if (sctx->chip_class < GFX11 && do_hardware_msaa_resolve(ctx, info)) + if (sctx->gfx_level < GFX11 && do_hardware_msaa_resolve(ctx, info)) return; if ((info->dst.resource->bind & PIPE_BIND_PRIME_BLIT_DST) && sdst->surface.is_linear && - sctx->chip_class >= GFX7) { + sctx->gfx_level >= GFX7) { struct si_texture *ssrc = (struct si_texture *)info->src.resource; /* Use SDMA or async compute when copying to a DRI_PRIME imported linear surface. */ bool async_copy = info->dst.box.x == 0 && info->dst.box.y == 0 && info->dst.box.z == 0 && @@ -1345,7 +1345,7 @@ void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex) if (!tex->surface.meta_offset || !sctx->has_graphics) return; - if (sctx->chip_class == GFX8 || tex->buffer.b.b.nr_storage_samples >= 2) { + if (sctx->gfx_level == GFX8 || tex->buffer.b.b.nr_storage_samples >= 2) { si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level, 0, util_max_layer(&tex->buffer.b.b, 0), true, false); } else { diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c index d382916741e..682967aa345 100644 --- a/src/gallium/drivers/radeonsi/si_buffer.c +++ b/src/gallium/drivers/radeonsi/si_buffer.c @@ -143,7 +143,7 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, * Only CP DMA and optimized compute benefit from this. * GFX8 and older don't support RADEON_FLAG_UNCACHED. */ - if (sscreen->info.chip_class >= GFX9 && + if (sscreen->info.gfx_level >= GFX9 && res->b.b.flags & SI_RESOURCE_FLAG_UNCACHED) res->flags |= RADEON_FLAG_UNCACHED; diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h index a37ab1ba6ef..f0ba9317ed8 100644 --- a/src/gallium/drivers/radeonsi/si_build_pm4.h +++ b/src/gallium/drivers/radeonsi/si_build_pm4.h @@ -151,13 +151,13 @@ radeon_emit(value); \ } while (0) -#define radeon_set_uconfig_reg_idx(screen, chip_class, reg, idx, value) do { \ +#define radeon_set_uconfig_reg_idx(screen, gfx_level, reg, idx, value) do { \ SI_CHECK_SHADOWED_REGS(reg, 1); \ assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \ assert((idx) != 0); \ unsigned __opcode = PKT3_SET_UCONFIG_REG_INDEX; \ - if ((chip_class) < GFX9 || \ - ((chip_class) == GFX9 && (screen)->info.me_fw_version < 26)) \ + if ((gfx_level) < GFX9 || \ + ((gfx_level) == GFX9 && (screen)->info.me_fw_version < 26)) \ __opcode = PKT3_SET_UCONFIG_REG; \ radeon_emit(PKT3(__opcode, 1, 0)); \ radeon_emit(((reg) - CIK_UCONFIG_REG_OFFSET) >> 2 | ((idx) << 28)); \ @@ -263,7 +263,7 @@ unsigned __value = val; \ if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \ sctx->tracked_regs.reg_value[reg] != __value) { \ - if (sctx->chip_class >= GFX10) \ + if (sctx->gfx_level >= GFX10) \ radeon_set_sh_reg_idx3(offset, __value); \ else \ radeon_set_sh_reg(offset, __value); \ @@ -323,7 +323,7 @@ static inline void radeon_set_sh_reg_idx3_func(struct radeon_cmdbuf *cs, unsigne /* This should be evaluated at compile time if all parameters are constants. */ static ALWAYS_INLINE unsigned -si_get_user_data_base(enum chip_class chip_class, enum si_has_tess has_tess, +si_get_user_data_base(enum amd_gfx_level gfx_level, enum si_has_tess has_tess, enum si_has_gs has_gs, enum si_has_ngg ngg, enum pipe_shader_type shader) { @@ -331,14 +331,14 @@ si_get_user_data_base(enum chip_class chip_class, enum si_has_tess has_tess, case PIPE_SHADER_VERTEX: /* VS can be bound as VS, ES, or LS. */ if (has_tess) { - if (chip_class >= GFX10) { + if (gfx_level >= GFX10) { return R_00B430_SPI_SHADER_USER_DATA_HS_0; - } else if (chip_class == GFX9) { + } else if (gfx_level == GFX9) { return R_00B430_SPI_SHADER_USER_DATA_LS_0; } else { return R_00B530_SPI_SHADER_USER_DATA_LS_0; } - } else if (chip_class >= GFX10) { + } else if (gfx_level >= GFX10) { if (ngg || has_gs) { return R_00B230_SPI_SHADER_USER_DATA_GS_0; } else { @@ -351,7 +351,7 @@ si_get_user_data_base(enum chip_class chip_class, enum si_has_tess has_tess, } case PIPE_SHADER_TESS_CTRL: - if (chip_class == GFX9) { + if (gfx_level == GFX9) { return R_00B430_SPI_SHADER_USER_DATA_LS_0; } else { return R_00B430_SPI_SHADER_USER_DATA_HS_0; @@ -360,7 +360,7 @@ si_get_user_data_base(enum chip_class chip_class, enum si_has_tess has_tess, case PIPE_SHADER_TESS_EVAL: /* TES can be bound as ES, VS, or not bound. */ if (has_tess) { - if (chip_class >= GFX10) { + if (gfx_level >= GFX10) { if (ngg || has_gs) { return R_00B230_SPI_SHADER_USER_DATA_GS_0; } else { @@ -376,7 +376,7 @@ si_get_user_data_base(enum chip_class chip_class, enum si_has_tess has_tess, } case PIPE_SHADER_GEOMETRY: - if (chip_class == GFX9) { + if (gfx_level == GFX9) { return R_00B330_SPI_SHADER_USER_DATA_ES_0; } else { return R_00B230_SPI_SHADER_USER_DATA_GS_0; diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 93e15450714..fcf9fc78917 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -71,7 +71,7 @@ void si_execute_clears(struct si_context *sctx, struct si_clear_info *info, sctx->flags |= SI_CONTEXT_INV_VCACHE; /* GFX6-8: CB and DB don't use L2. */ - if (sctx->chip_class <= GFX8) + if (sctx->gfx_level <= GFX8) sctx->flags |= SI_CONTEXT_INV_L2; /* Execute clears. */ @@ -100,13 +100,13 @@ void si_execute_clears(struct si_context *sctx, struct si_clear_info *info, sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH; /* GFX6-8: CB and DB don't use L2. */ - if (sctx->chip_class <= GFX8) + if (sctx->gfx_level <= GFX8) sctx->flags |= SI_CONTEXT_WB_L2; } static bool si_alloc_separate_cmask(struct si_screen *sscreen, struct si_texture *tex) { - assert(sscreen->info.chip_class < GFX11); + assert(sscreen->info.gfx_level < GFX11); /* CMASK for MSAA is allocated in advance or always disabled * by "nofmask" option. @@ -171,7 +171,7 @@ bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format) { format = si_simplify_cb_format(format); const struct util_format_description *desc = util_format_description(format); - unsigned comp_swap = si_translate_colorswap(sscreen->info.chip_class, format, false); + unsigned comp_swap = si_translate_colorswap(sscreen->info.gfx_level, format, false); /* The following code matches the hw behavior. */ if (desc->nr_channels == 1) { @@ -426,11 +426,11 @@ bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsi assert(vi_dcc_enabled(tex, level)); - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { /* 4x and 8x MSAA needs a sophisticated compute shader for * the clear. GFX11 doesn't need that. */ - if (sctx->chip_class < GFX11 && tex->buffer.b.b.nr_storage_samples >= 4) + if (sctx->gfx_level < GFX11 && tex->buffer.b.b.nr_storage_samples >= 4) return false; unsigned num_layers = util_num_layers(&tex->buffer.b.b, level); @@ -448,7 +448,7 @@ bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsi */ return false; } - } else if (sctx->chip_class == GFX9) { + } else if (sctx->gfx_level == GFX9) { /* TODO: Implement DCC fast clear for level 0 of mipmapped textures. Mipmapped * DCC has to clear a rectangular area of DCC for level 0 (because the whole miptree * is organized in a 2D plane). @@ -493,16 +493,16 @@ bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsi */ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_texture *tex) { - if (sscreen->info.chip_class >= GFX10 || tex->buffer.b.is_shared || + if (sscreen->info.gfx_level >= GFX10 || tex->buffer.b.is_shared || tex->buffer.b.b.nr_samples <= 1 || tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode) return; - assert(sscreen->info.chip_class >= GFX9 || + assert(sscreen->info.gfx_level >= GFX9 || tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D); assert(tex->buffer.b.b.last_level == 0); - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */ assert(tex->surface.u.gfx9.swizzle_mode >= 4); @@ -533,7 +533,7 @@ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_ assert(!"unexpected micro mode"); return; } - } else if (sscreen->info.chip_class >= GFX7) { + } else if (sscreen->info.gfx_level >= GFX7) { /* These magic numbers were copied from addrlib. It doesn't use * any definitions for them either. They are all 2D_TILED_THIN1 * modes with different bpp and micro tile mode. @@ -713,7 +713,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers, continue; } - if (sctx->chip_class <= GFX8 && tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D && + if (sctx->gfx_level <= GFX8 && tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D && !sctx->screen->info.htile_cmask_support_1d_tiling) continue; @@ -735,7 +735,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers, if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR)) continue; - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { if (!gfx11_get_dcc_clear_parameters(sctx->screen, fb->cbufs[i]->format, color, &reset_value)) continue; @@ -783,7 +783,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers, /* DCC fast clear with MSAA should clear CMASK to 0xC. */ if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) { - assert(sctx->chip_class < GFX11); /* no FMASK/CMASK on GFX11 */ + assert(sctx->gfx_level < GFX11); /* no FMASK/CMASK on GFX11 */ assert(num_clears < ARRAY_SIZE(info)); si_init_buffer_clear(&info[num_clears++], &tex->cmask_buffer->b.b, tex->surface.cmask_offset, tex->surface.cmask_size, 0xCCCCCCCC); @@ -792,7 +792,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers, } } else { /* No CMASK on GFX11. */ - if (sctx->chip_class >= GFX11) + if (sctx->gfx_level >= GFX11) continue; if (level > 0) @@ -824,7 +824,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers, uint64_t cmask_offset = 0; unsigned clear_size = 0; - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { assert(level == 0); /* Clearing CMASK with both multiple levels and multiple layers is not @@ -847,7 +847,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers, } else { assert(0); /* this is prevented above */ } - } else if (sctx->chip_class == GFX9) { + } else if (sctx->gfx_level == GFX9) { /* TODO: Implement CMASK fast clear for level 0 of mipmapped textures. Mipmapped * CMASK has to clear a rectangular area of CMASK for level 0 (because the whole * miptree is organized in a 2D plane). @@ -879,7 +879,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers, if ((eliminate_needed || fmask_decompress_needed) && !(tex->dirty_level_mask & (1 << level))) { - assert(sctx->chip_class < GFX11); /* no decompression needed on GFX11 */ + assert(sctx->gfx_level < GFX11); /* no decompression needed on GFX11 */ tex->dirty_level_mask |= 1 << level; si_set_sampler_depth_decompress_mask(sctx, tex); p_atomic_inc(&sctx->screen->compressed_colortex_counter); @@ -894,7 +894,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers, continue; /* There are no clear color registers on GFX11. */ - assert(sctx->chip_class < GFX11); + assert(sctx->gfx_level < GFX11); if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) { sctx->framebuffer.dirty_cbufs |= 1 << i; @@ -973,7 +973,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers, clear_value = !zstex->htile_stencil_disabled ? 0xfffff30f : 0xfffc000f; } - zstex->need_flush_after_depth_decompression = sctx->chip_class == GFX10_3; + zstex->need_flush_after_depth_decompression = sctx->gfx_level == GFX10_3; assert(num_clears < ARRAY_SIZE(info)); si_init_buffer_clear(&info[num_clears++], &zstex->buffer.b.b, @@ -992,7 +992,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers, unsigned htile_size = 0; /* Determine the HTILE subset to clear. */ - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { /* This can only clear a layered texture with 1 level or a mipmap texture * with 1 layer. Other cases are unimplemented. */ @@ -1080,7 +1080,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers, } } - zstex->need_flush_after_depth_decompression = update_db_depth_clear && sctx->chip_class == GFX10_3; + zstex->need_flush_after_depth_decompression = update_db_depth_clear && sctx->gfx_level == GFX10_3; /* Update DB_DEPTH_CLEAR. */ if (update_db_depth_clear && @@ -1273,7 +1273,7 @@ static void si_clear_render_target(struct pipe_context *ctx, struct pipe_surface return; if (dst->texture->nr_samples <= 1 && - (sctx->chip_class >= GFX10 || !vi_dcc_enabled(sdst, dst->u.tex.level))) { + (sctx->gfx_level >= GFX10 || !vi_dcc_enabled(sdst, dst->u.tex.level))) { si_compute_clear_render_target(ctx, dst, color, dstx, dsty, width, height, render_condition_enabled); return; diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index c19e0d4746d..7c17341dd76 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -155,7 +155,7 @@ static void si_create_compute_state_async(void *job, void *gdata, int thread_ind /* Remove images with FMASK from the bitmask. We only care about the first * 3 anyway, so we can take msaa_images[0] and ignore the rest. */ - if (sscreen->info.chip_class < GFX11) + if (sscreen->info.gfx_level < GFX11) non_fmask_images &= ~sel->info.base.msaa_images[0]; for (unsigned i = 0; i < 3 && non_fmask_images & (1 << i); i++) { @@ -200,10 +200,10 @@ static void si_create_compute_state_async(void *job, void *gdata, int thread_ind sscreen->info.wave64_vgpr_alloc_granularity == 8) ? 8 : 4)) | S_00B848_DX10_CLAMP(1) | S_00B848_MEM_ORDERED(si_shader_mem_ordered(shader)) | - S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) | + S_00B848_WGP_MODE(sscreen->info.gfx_level >= GFX10) | S_00B848_FLOAT_MODE(shader->config.float_mode); - if (sscreen->info.chip_class < GFX10) { + if (sscreen->info.gfx_level < GFX10) { shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8); } @@ -385,7 +385,7 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); - if (sctx->chip_class == GFX6) { + if (sctx->gfx_level == GFX6) { /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID * and is now per pipe, so it should be handled in the * kernel if we want to use something other than the default value. @@ -402,7 +402,7 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf } } - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */ radeon_set_sh_reg_seq(R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2); radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); @@ -428,10 +428,10 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf /* cs_preamble_state initializes this for the gfx queue, so only do this * if we are on a compute queue. */ - if (sctx->chip_class >= GFX9 && sctx->chip_class < GFX11 && + if (sctx->gfx_level >= GFX9 && sctx->gfx_level < GFX11 && (cs != &sctx->gfx_cs || !sctx->screen->info.has_graphics)) { radeon_set_uconfig_reg(R_0301EC_CP_COHER_START_DELAY, - sctx->chip_class >= GFX10 ? 0x20 : 0); + sctx->gfx_level >= GFX10 ? 0x20 : 0); } if (!info->has_graphics && info->family >= CHIP_ARCTURUS) { @@ -442,7 +442,7 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf radeon_emit(S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en)); } - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { radeon_set_sh_reg_seq(R_00B890_COMPUTE_USER_ACCUM_0, 4); radeon_emit(0); /* R_00B890_COMPUTE_USER_ACCUM_0 */ radeon_emit(0); /* R_00B894_COMPUTE_USER_ACCUM_1 */ @@ -451,11 +451,11 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf radeon_set_sh_reg(R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0); - if (sctx->chip_class < GFX11) + if (sctx->gfx_level < GFX11) radeon_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3, 0); } - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { radeon_set_sh_reg_seq(R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4, 4); radeon_emit(S_00B8AC_SA0_CU_EN(info->spi_cu_en) | S_00B8AC_SA1_CU_EN(info->spi_cu_en)); /* SE4 */ radeon_emit(S_00B8AC_SA0_CU_EN(info->spi_cu_en) | S_00B8AC_SA1_CU_EN(info->spi_cu_en)); /* SE5 */ @@ -490,7 +490,7 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_s } if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) { - if (sctx->chip_class < GFX11) { + if (sctx->gfx_level < GFX11) { uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) @@ -530,7 +530,7 @@ static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute * allocated in the shader and 4 bytes allocated by the state * tracker, then we will set LDS_SIZE to 512 bytes rather than 256. */ - if (sctx->chip_class <= GFX6) { + if (sctx->gfx_level <= GFX6) { lds_blocks += align(program->sel.info.base.shared_size, 256) >> 8; } else { lds_blocks += align(program->sel.info.base.shared_size, 512) >> 9; @@ -569,12 +569,12 @@ static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute radeon_begin(cs); radeon_set_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8); - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { radeon_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3, S_00B8A0_INST_PREF_SIZE(si_calc_inst_pref_size(shader))); } - if (sctx->chip_class >= GFX11 && shader->scratch_bo) { + if (sctx->gfx_level >= GFX11 && shader->scratch_bo) { radeon_set_sh_reg_seq(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO, 4); radeon_emit(sctx->compute_scratch_buffer->gpu_address >> 8); radeon_emit(sctx->compute_scratch_buffer->gpu_address >> 40); @@ -612,7 +612,7 @@ static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx, uint32_t scratch_dword0 = scratch_va & 0xffffffff; uint32_t scratch_dword1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32); - if (sctx->chip_class >= GFX11) + if (sctx->gfx_level >= GFX11) scratch_dword1 |= S_008F04_SWIZZLE_ENABLE_GFX11(1); else scratch_dword1 |= S_008F04_SWIZZLE_ENABLE_GFX6(1); @@ -621,12 +621,12 @@ static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx, uint32_t scratch_dword2 = 0xffffffff; uint32_t scratch_dword3 = S_008F0C_INDEX_STRIDE(3) | S_008F0C_ADD_TID_ENABLE(1); - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { assert(max_private_element_size == 1); /* only 4 bytes on GFX9 */ } else { scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size); - if (sctx->chip_class < GFX8) { + if (sctx->gfx_level < GFX8) { /* BUF_DATA_FORMAT is ignored, but it cannot be * BUF_DATA_FORMAT_INVALID. */ scratch_dword3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8); @@ -811,7 +811,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_ DIV_ROUND_UP(threads_per_threadgroup, sctx->cs_shader_state.program->shader.wave_size); unsigned threadgroups_per_cu = 1; - if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1) + if (sctx->gfx_level >= GFX10 && waves_per_threadgroup == 1) threadgroups_per_cu = 2; if (unlikely(sctx->thread_trace_enabled)) { @@ -829,7 +829,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_ unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) | S_00B800_FORCE_START_AT_000(1) | /* If the KMD allows it (there is a KMD hw register for it), * allow launching waves out-of-order. (same as Vulkan) */ - S_00B800_ORDER_MODE(sctx->chip_class >= GFX7) | + S_00B800_ORDER_MODE(sctx->gfx_level >= GFX7) | S_00B800_CS_W32_EN(sctx->cs_shader_state.program->shader.wave_size == 32); const uint *last_block = info->last_block; @@ -881,7 +881,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_ radeon_emit(dispatch_initiator); } - if (unlikely(sctx->thread_trace_enabled && sctx->chip_class >= GFX9)) { + if (unlikely(sctx->thread_trace_enabled && sctx->gfx_level >= GFX9)) { radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0)); } @@ -969,7 +969,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info si_context_add_resource_size(sctx, info->indirect); /* Indirect buffers use TC L2 on GFX9, but not older hw. */ - if (sctx->chip_class <= GFX8 && si_resource(info->indirect)->TC_L2_dirty) { + if (sctx->gfx_level <= GFX8 && si_resource(info->indirect)->TC_L2_dirty) { sctx->flags |= SI_CONTEXT_WB_L2; si_resource(info->indirect)->TC_L2_dirty = false; } @@ -1029,7 +1029,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info } /* Prefetch the compute shader to L2. */ - if (sctx->chip_class >= GFX7 && prefetch) + if (sctx->gfx_level >= GFX7 && prefetch) si_cp_dma_prefetch(sctx, &program->shader.bo->b.b, 0, program->shader.bo->b.b.width0); if (program->ir_type != PIPE_SHADER_IR_NATIVE) diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index 9387dc458c2..9a800adb3b5 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -32,10 +32,10 @@ static enum si_cache_policy get_cache_policy(struct si_context *sctx, enum si_coherency coher, uint64_t size) { - if ((sctx->chip_class >= GFX9 && (coher == SI_COHERENCY_CB_META || + if ((sctx->gfx_level >= GFX9 && (coher == SI_COHERENCY_CB_META || coher == SI_COHERENCY_DB_META || coher == SI_COHERENCY_CP)) || - (sctx->chip_class >= GFX7 && coher == SI_COHERENCY_SHADER)) + (sctx->gfx_level >= GFX7 && coher == SI_COHERENCY_SHADER)) return L2_LRU; /* it's faster if L2 doesn't evict anything */ return L2_BYPASS; @@ -152,7 +152,7 @@ void si_launch_grid_internal(struct si_context *sctx, struct pipe_grid_info *inf if (flags & SI_OP_CS_IMAGE) { /* Make sure image stores are visible to CB, which doesn't use L2 on GFX6-8. */ - sctx->flags |= sctx->chip_class <= GFX8 ? SI_CONTEXT_WB_L2 : 0; + sctx->flags |= sctx->gfx_level <= GFX8 ? SI_CONTEXT_WB_L2 : 0; /* Make sure image stores are visible to all CUs. */ sctx->flags |= SI_CONTEXT_INV_VCACHE; } else { @@ -386,7 +386,7 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, if (aligned_size >= 4) { uint64_t compute_min_size; - if (sctx->chip_class <= GFX8) { + if (sctx->gfx_level <= GFX8) { /* CP DMA clears are terribly slow with GTT on GFX6-8, which can always * happen due to BO evictions. */ @@ -604,7 +604,7 @@ void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, u /* src and dst have the same number of samples. */ si_make_CB_shader_coherent(sctx, src->nr_samples, true, ssrc->surface.u.gfx9.color.dcc.pipe_aligned); - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { /* GFX10+ uses DCC stores so si_make_CB_shader_coherent is required for dst too */ si_make_CB_shader_coherent(sctx, dst->nr_samples, true, sdst->surface.u.gfx9.color.dcc.pipe_aligned); @@ -631,7 +631,7 @@ void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, u if (is_dcc_decompress) image[1].access |= SI_IMAGE_ACCESS_DCC_OFF; - else if (sctx->chip_class >= GFX10) + else if (sctx->gfx_level >= GFX10) image[1].access |= SI_IMAGE_ACCESS_ALLOW_DCC_STORE; ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 2, 0, image); @@ -759,7 +759,7 @@ void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uin { struct si_texture *tex = (struct si_texture*)res; - assert(sctx->chip_class < GFX11); + assert(sctx->gfx_level < GFX11); /* Set the DCC buffer. */ assert(tex->surface.meta_offset && tex->surface.meta_offset <= UINT_MAX); @@ -813,7 +813,7 @@ void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex unsigned log_samples = util_logbase2(tex->nr_samples); assert(tex->nr_samples >= 2); - assert(sctx->chip_class < GFX11); + assert(sctx->gfx_level < GFX11); /* EQAA FMASK expansion is unimplemented. */ if (tex->nr_samples != tex->nr_storage_samples) diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index 88a495c3f0f..04f5a663397 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -43,8 +43,8 @@ static inline unsigned cp_dma_max_byte_count(struct si_context *sctx) { unsigned max = - sctx->chip_class >= GFX11 ? 32767 : - sctx->chip_class >= GFX9 ? S_415_BYTE_COUNT_GFX9(~0u) : S_415_BYTE_COUNT_GFX6(~0u); + sctx->gfx_level >= GFX11 ? 32767 : + sctx->gfx_level >= GFX9 ? S_415_BYTE_COUNT_GFX9(~0u) : S_415_BYTE_COUNT_GFX6(~0u); /* make it aligned for optimal performance */ return max & ~(SI_CPDMA_ALIGNMENT - 1); @@ -61,9 +61,9 @@ static void si_emit_cp_dma(struct si_context *sctx, struct radeon_cmdbuf *cs, ui uint32_t header = 0, command = 0; assert(size <= cp_dma_max_byte_count(sctx)); - assert(sctx->chip_class != GFX6 || cache_policy == L2_BYPASS); + assert(sctx->gfx_level != GFX6 || cache_policy == L2_BYPASS); - if (sctx->chip_class >= GFX9) + if (sctx->gfx_level >= GFX9) command |= S_415_BYTE_COUNT_GFX9(size); else command |= S_415_BYTE_COUNT_GFX6(size); @@ -76,13 +76,13 @@ static void si_emit_cp_dma(struct si_context *sctx, struct radeon_cmdbuf *cs, ui command |= S_415_RAW_WAIT(1); /* Src and dst flags. */ - if (sctx->chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) && src_va == dst_va) { + if (sctx->gfx_level >= GFX9 && !(flags & CP_DMA_CLEAR) && src_va == dst_va) { header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */ } else if (flags & CP_DMA_DST_IS_GDS) { header |= S_411_DST_SEL(V_411_GDS); /* GDS increments the address, not CP. */ command |= S_415_DAS(V_415_REGISTER) | S_415_DAIC(V_415_NO_INCREMENT); - } else if (sctx->chip_class >= GFX7 && cache_policy != L2_BYPASS) { + } else if (sctx->gfx_level >= GFX7 && cache_policy != L2_BYPASS) { header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2) | S_500_DST_CACHE_POLICY(cache_policy == L2_STREAM); } @@ -93,14 +93,14 @@ static void si_emit_cp_dma(struct si_context *sctx, struct radeon_cmdbuf *cs, ui header |= S_411_SRC_SEL(V_411_GDS); /* Both of these are required for GDS. It does increment the address. */ command |= S_415_SAS(V_415_REGISTER) | S_415_SAIC(V_415_NO_INCREMENT); - } else if (sctx->chip_class >= GFX7 && cache_policy != L2_BYPASS) { + } else if (sctx->gfx_level >= GFX7 && cache_policy != L2_BYPASS) { header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) | S_500_SRC_CACHE_POLICY(cache_policy == L2_STREAM); } radeon_begin(cs); - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { radeon_emit(PKT3(PKT3_DMA_DATA, 5, 0)); radeon_emit(header); radeon_emit(src_va); /* SRC_ADDR_LO [31:0] */ @@ -451,7 +451,7 @@ void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned assert(offset % 4 == 0); assert(size % 4 == 0); - if (sctx->chip_class == GFX6 && dst_sel == V_370_MEM) + if (sctx->gfx_level == GFX6 && dst_sel == V_370_MEM) dst_sel = V_370_MEM_GRBM; radeon_add_to_buffer_list(sctx, cs, buf, RADEON_USAGE_WRITE | RADEON_PRIO_CP_DMA); diff --git a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c index ca6b41d9c0b..71b83d3223c 100644 --- a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c +++ b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c @@ -35,7 +35,7 @@ static void si_build_load_reg(struct si_screen *sscreen, struct si_pm4_state *pm unsigned packet, num_ranges, offset; const struct ac_reg_range *ranges; - ac_get_reg_ranges(sscreen->info.chip_class, sscreen->info.family, + ac_get_reg_ranges(sscreen->info.gfx_level, sscreen->info.family, type, &num_ranges, &ranges); switch (type) { @@ -90,7 +90,7 @@ si_create_shadowing_ib_preamble(struct si_context *sctx) si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { unsigned gcr_cntl = S_586_GL2_INV(1) | S_586_GL2_WB(1) | S_586_GLM_INV(1) | S_586_GLM_WB(1) | S_586_GL1_INV(1) | S_586_GLV_INV(1) | @@ -104,7 +104,7 @@ si_create_shadowing_ib_preamble(struct si_context *sctx) si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE_HI */ si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */ si_pm4_cmd_add(pm4, gcr_cntl); /* GCR_CNTL */ - } else if (sctx->chip_class == GFX9) { + } else if (sctx->gfx_level == GFX9) { unsigned cp_coher_cntl = S_0301F0_SH_ICACHE_ACTION_ENA(1) | S_0301F0_SH_KCACHE_ACTION_ENA(1) | S_0301F0_TC_ACTION_ENA(1) | diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c index 5e0e84b6a64..c53d2f589b9 100644 --- a/src/gallium/drivers/radeonsi/si_debug.c +++ b/src/gallium/drivers/radeonsi/si_debug.c @@ -297,7 +297,7 @@ static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f, unsigned offse uint32_t value; if (ws->read_registers(ws, offset, 1, &value)) - ac_dump_reg(f, sctx->chip_class, offset, value, ~0); + ac_dump_reg(f, sctx->gfx_level, offset, value, ~0); } static void si_dump_debug_registers(struct si_context *sctx, FILE *f) @@ -321,7 +321,7 @@ static void si_dump_debug_registers(struct si_context *sctx, FILE *f) si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3); si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG); si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG); - if (sctx->chip_class <= GFX8) { + if (sctx->gfx_level <= GFX8) { si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS); si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2); si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3); @@ -355,7 +355,7 @@ static void si_log_chunk_type_cs_destroy(void *data) static void si_parse_current_ib(FILE *f, struct radeon_cmdbuf *cs, unsigned begin, unsigned end, int *last_trace_id, unsigned trace_id_count, const char *name, - enum chip_class chip_class) + enum amd_gfx_level gfx_level) { unsigned orig_end = end; @@ -368,7 +368,7 @@ static void si_parse_current_ib(FILE *f, struct radeon_cmdbuf *cs, unsigned begi if (begin < chunk->cdw) { ac_parse_ib_chunk(f, chunk->buf + begin, MIN2(end, chunk->cdw) - begin, last_trace_id, - trace_id_count, chip_class, NULL, NULL); + trace_id_count, gfx_level, NULL, NULL); } if (end <= chunk->cdw) @@ -384,7 +384,7 @@ static void si_parse_current_ib(FILE *f, struct radeon_cmdbuf *cs, unsigned begi assert(end <= cs->current.cdw); ac_parse_ib_chunk(f, cs->current.buf + begin, end - begin, last_trace_id, trace_id_count, - chip_class, NULL, NULL); + gfx_level, NULL, NULL); fprintf(f, "------------------- %s end (dw = %u) -------------------\n\n", name, orig_end); } @@ -392,7 +392,7 @@ static void si_parse_current_ib(FILE *f, struct radeon_cmdbuf *cs, unsigned begi void si_print_current_ib(struct si_context *sctx, FILE *f) { si_parse_current_ib(f, &sctx->gfx_cs, 0, sctx->gfx_cs.prev_dw + sctx->gfx_cs.current.cdw, - NULL, 0, "GFX", sctx->chip_class); + NULL, 0, "GFX", sctx->gfx_level); } static void si_log_chunk_type_cs_print(void *data, FILE *f) @@ -415,19 +415,19 @@ static void si_log_chunk_type_cs_print(void *data, FILE *f) if (chunk->gfx_begin == 0) { if (ctx->cs_preamble_state) ac_parse_ib(f, ctx->cs_preamble_state->pm4, ctx->cs_preamble_state->ndw, NULL, 0, - "IB2: Init config", ctx->chip_class, NULL, NULL); + "IB2: Init config", ctx->gfx_level, NULL, NULL); if (ctx->cs_preamble_gs_rings) ac_parse_ib(f, ctx->cs_preamble_gs_rings->pm4, ctx->cs_preamble_gs_rings->ndw, NULL, 0, - "IB2: Init GS rings", ctx->chip_class, NULL, NULL); + "IB2: Init GS rings", ctx->gfx_level, NULL, NULL); } if (scs->flushed) { ac_parse_ib(f, scs->gfx.ib + chunk->gfx_begin, chunk->gfx_end - chunk->gfx_begin, - &last_trace_id, map ? 1 : 0, "IB", ctx->chip_class, NULL, NULL); + &last_trace_id, map ? 1 : 0, "IB", ctx->gfx_level, NULL, NULL); } else { si_parse_current_ib(f, &ctx->gfx_cs, chunk->gfx_begin, chunk->gfx_end, &last_trace_id, - map ? 1 : 0, "IB", ctx->chip_class); + map ? 1 : 0, "IB", ctx->gfx_level); } } @@ -621,7 +621,7 @@ struct si_log_chunk_desc_list { const char *shader_name; const char *elem_name; slot_remap_func slot_remap; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; unsigned element_dw_size; unsigned num_elements; @@ -639,7 +639,7 @@ static void si_log_chunk_desc_list_print(void *data, FILE *f) { struct si_log_chunk_desc_list *chunk = data; unsigned sq_img_rsrc_word0 = - chunk->chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0 : R_008F10_SQ_IMG_RSRC_WORD0; + chunk->gfx_level >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0 : R_008F10_SQ_IMG_RSRC_WORD0; for (unsigned i = 0; i < chunk->num_elements; i++) { unsigned cpu_dw_offset = i * chunk->element_dw_size; @@ -654,35 +654,35 @@ static void si_log_chunk_desc_list_print(void *data, FILE *f) switch (chunk->element_dw_size) { case 4: for (unsigned j = 0; j < 4; j++) - ac_dump_reg(f, chunk->chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, gpu_list[j], + ac_dump_reg(f, chunk->gfx_level, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, gpu_list[j], 0xffffffff); break; case 8: for (unsigned j = 0; j < 8; j++) - ac_dump_reg(f, chunk->chip_class, sq_img_rsrc_word0 + j * 4, gpu_list[j], 0xffffffff); + ac_dump_reg(f, chunk->gfx_level, sq_img_rsrc_word0 + j * 4, gpu_list[j], 0xffffffff); fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n"); for (unsigned j = 0; j < 4; j++) - ac_dump_reg(f, chunk->chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, gpu_list[4 + j], + ac_dump_reg(f, chunk->gfx_level, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, gpu_list[4 + j], 0xffffffff); break; case 16: for (unsigned j = 0; j < 8; j++) - ac_dump_reg(f, chunk->chip_class, sq_img_rsrc_word0 + j * 4, gpu_list[j], 0xffffffff); + ac_dump_reg(f, chunk->gfx_level, sq_img_rsrc_word0 + j * 4, gpu_list[j], 0xffffffff); fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n"); for (unsigned j = 0; j < 4; j++) - ac_dump_reg(f, chunk->chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, gpu_list[4 + j], + ac_dump_reg(f, chunk->gfx_level, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, gpu_list[4 + j], 0xffffffff); fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n"); for (unsigned j = 0; j < 8; j++) - ac_dump_reg(f, chunk->chip_class, sq_img_rsrc_word0 + j * 4, gpu_list[8 + j], + ac_dump_reg(f, chunk->gfx_level, sq_img_rsrc_word0 + j * 4, gpu_list[8 + j], 0xffffffff); fprintf(f, COLOR_CYAN " Sampler state:" COLOR_RESET "\n"); for (unsigned j = 0; j < 4; j++) - ac_dump_reg(f, chunk->chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4, gpu_list[12 + j], + ac_dump_reg(f, chunk->gfx_level, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4, gpu_list[12 + j], 0xffffffff); break; } @@ -732,7 +732,7 @@ static void si_dump_descriptor_list(struct si_screen *screen, struct si_descript chunk->element_dw_size = element_dw_size; chunk->num_elements = num_elements; chunk->slot_remap = slot_remap; - chunk->chip_class = screen->info.chip_class; + chunk->gfx_level = screen->info.gfx_level; si_resource_reference(&chunk->buf, desc->buffer); chunk->gpu_list = desc->gpu_list; @@ -976,7 +976,7 @@ static void si_print_annotated_shader(struct si_shader *shader, struct ac_wave_i static void si_dump_annotated_shaders(struct si_context *sctx, FILE *f) { struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP]; - unsigned num_waves = ac_get_wave_info(sctx->chip_class, waves); + unsigned num_waves = ac_get_wave_info(sctx->gfx_level, waves); fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET "\n\n", num_waves); @@ -1083,7 +1083,7 @@ void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved, uint64_t addr; char cmd_line[4096]; - if (!ac_vm_fault_occured(sctx->chip_class, &sctx->dmesg_timestamp, &addr)) + if (!ac_vm_fault_occured(sctx->gfx_level, &sctx->dmesg_timestamp, &addr)) return; f = dd_get_debug_file(false); @@ -1133,5 +1133,5 @@ void si_init_debug_functions(struct si_context *sctx) * only new messages will be checked for VM faults. */ if (sctx->screen->debug_flags & DBG(CHECK_VM)) - ac_vm_fault_occured(sctx->chip_class, &sctx->dmesg_timestamp, NULL); + ac_vm_fault_occured(sctx->gfx_level, &sctx->dmesg_timestamp, NULL); } diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 1985fa37743..698ac5f4691 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -299,7 +299,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture va = tex->buffer.gpu_address; - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { /* Only stencil_offset needs to be added here. */ if (is_stencil) va += tex->surface.u.gfx9.zs.stencil_offset; @@ -315,14 +315,14 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture /* Only macrotiled modes can set tile swizzle. * GFX9 doesn't use (legacy) base_level_info. */ - if (sscreen->info.chip_class >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D) + if (sscreen->info.gfx_level >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D) state[0] |= tex->surface.tile_swizzle; - if (sscreen->info.chip_class >= GFX8) { + if (sscreen->info.gfx_level >= GFX8) { if (!(access & SI_IMAGE_ACCESS_DCC_OFF) && vi_dcc_enabled(tex, first_level)) { meta_va = tex->buffer.gpu_address + tex->surface.meta_offset; - if (sscreen->info.chip_class == GFX8) { + if (sscreen->info.gfx_level == GFX8) { meta_va += tex->surface.u.legacy.color.dcc_level[base_level].dcc_offset; assert(base_level_info->mode == RADEON_SURF_MODE_2D); } @@ -339,10 +339,10 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture state[6] |= S_008F28_COMPRESSION_EN(1); } - if (sscreen->info.chip_class >= GFX8 && sscreen->info.chip_class <= GFX9) + if (sscreen->info.gfx_level >= GFX8 && sscreen->info.gfx_level <= GFX9) state[7] = meta_va >> 8; - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { if (is_stencil) { state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode); } else { @@ -369,7 +369,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture * The same limitations apply to SDMA compressed stores because * SDMA uses the same DCC codec. */ - S_00A018_WRITE_COMPRESS_ENABLE(ac_surface_supports_dcc_image_stores(sscreen->info.chip_class, &tex->surface) && + S_00A018_WRITE_COMPRESS_ENABLE(ac_surface_supports_dcc_image_stores(sscreen->info.gfx_level, &tex->surface) && (access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE)); /* TC-compatible MSAA HTILE requires ITERATE_256. */ @@ -378,7 +378,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture } state[7] = meta_va >> 16; - } else if (sscreen->info.chip_class == GFX9) { + } else if (sscreen->info.gfx_level == GFX9) { if (is_stencil) { state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode); state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.zs.stencil_epitch); @@ -789,7 +789,7 @@ static void si_set_shader_image_desc(struct si_context *ctx, const struct pipe_i unsigned depth = res->b.b.depth0; unsigned hw_level = level; - if (ctx->chip_class <= GFX8) { + if (ctx->gfx_level <= GFX8) { /* Always force the base level to the selected level. * * This is required for 3D textures, where otherwise @@ -803,7 +803,7 @@ static void si_set_shader_image_desc(struct si_context *ctx, const struct pipe_i } if (access & SI_IMAGE_ACCESS_BLOCK_FORMAT_AS_UINT) { - if (ctx->chip_class >= GFX9) { + if (ctx->gfx_level >= GFX9) { /* Since the aligned width and height are derived from the width and height * by the hw, set them directly as the width and height, so that UINT formats * get exactly the same layout as BCn formats. @@ -1080,10 +1080,10 @@ static void si_init_buffer_resources(struct si_context *sctx, desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); - } else if (sctx->chip_class >= GFX10) { + } else if (sctx->gfx_level >= GFX10) { desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -1213,7 +1213,7 @@ static void si_set_constant_buffer(struct si_context *sctx, struct si_buffer_res /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy * with a NULL buffer). We need to use a dummy buffer instead. */ - if (sctx->chip_class == GFX7 && (!input || (!input->buffer && !input->user_buffer))) + if (sctx->gfx_level == GFX7 && (!input || (!input->buffer && !input->user_buffer))) input = &sctx->null_const_buf; if (input && (input->buffer || input->user_buffer)) { @@ -1529,7 +1529,7 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource break; } - if (sctx->chip_class >= GFX8 && stride) + if (sctx->gfx_level >= GFX8 && stride) num_records *= stride; /* Set the descriptor. */ @@ -1541,10 +1541,10 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | S_008F0C_INDEX_STRIDE(index_stride) | S_008F0C_ADD_TID_ENABLE(add_tid); - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { assert(!swizzle || element_size == 1 || element_size == 3); /* 4 or 16 bytes */ desc[1] |= S_008F04_SWIZZLE_ENABLE_GFX11(swizzle ? element_size : 0); - } else if (sctx->chip_class >= GFX9) { + } else if (sctx->gfx_level >= GFX9) { assert(!swizzle || element_size == 1); /* only 4 bytes on GFX9 */ desc[1] |= S_008F04_SWIZZLE_ENABLE_GFX6(swizzle); } else { @@ -1552,10 +1552,10 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource desc[3] |= S_008F0C_ELEMENT_SIZE(element_size); } - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED); - } else if (sctx->chip_class >= GFX10) { + } else if (sctx->gfx_level >= GFX10) { desc[3] |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else { @@ -2072,7 +2072,7 @@ void si_shader_pointers_mark_dirty(struct si_context *sctx) sctx->compute_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL; sctx->compute_shaderbuf_sgprs_dirty = true; sctx->compute_image_sgprs_dirty = true; - if (sctx->chip_class >= GFX11) + if (sctx->gfx_level >= GFX11) sctx->gs_attribute_ring_pointer_dirty = true; } @@ -2105,14 +2105,14 @@ static void si_set_user_data_base(struct si_context *sctx, unsigned shader, uint void si_shader_change_notify(struct si_context *sctx) { si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, - si_get_user_data_base(sctx->chip_class, + si_get_user_data_base(sctx->gfx_level, sctx->shader.tes.cso ? TESS_ON : TESS_OFF, sctx->shader.gs.cso ? GS_ON : GS_OFF, sctx->ngg ? NGG_ON : NGG_OFF, PIPE_SHADER_VERTEX)); si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, - si_get_user_data_base(sctx->chip_class, + si_get_user_data_base(sctx->gfx_level, sctx->shader.tes.cso ? TESS_ON : TESS_OFF, sctx->shader.gs.cso ? GS_ON : GS_OFF, sctx->ngg ? NGG_ON : NGG_OFF, @@ -2172,13 +2172,13 @@ static void si_emit_global_shader_pointers(struct si_context *sctx, struct si_de { radeon_begin(&sctx->gfx_cs); - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { radeon_emit_one_32bit_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0); radeon_emit_one_32bit_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0); radeon_emit_one_32bit_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0); radeon_end(); return; - } else if (sctx->chip_class >= GFX10) { + } else if (sctx->gfx_level >= GFX10) { radeon_emit_one_32bit_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0); /* HW VS stage only used in non-NGG mode. */ radeon_emit_one_32bit_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0); @@ -2186,7 +2186,7 @@ static void si_emit_global_shader_pointers(struct si_context *sctx, struct si_de radeon_emit_one_32bit_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0); radeon_end(); return; - } else if (sctx->chip_class == GFX9 && sctx->shadowed_regs) { + } else if (sctx->gfx_level == GFX9 && sctx->shadowed_regs) { /* We can't use the COMMON registers with register shadowing. */ radeon_emit_one_32bit_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0); radeon_emit_one_32bit_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0); @@ -2194,7 +2194,7 @@ static void si_emit_global_shader_pointers(struct si_context *sctx, struct si_de radeon_emit_one_32bit_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_LS_0); radeon_end(); return; - } else if (sctx->chip_class == GFX9) { + } else if (sctx->gfx_level == GFX9) { /* Broadcast it to all shader stages. */ radeon_emit_one_32bit_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_COMMON_0); radeon_end(); @@ -2231,7 +2231,7 @@ void si_emit_graphics_shader_pointers(struct si_context *sctx) sh_base[PIPE_SHADER_GEOMETRY]); if (sctx->gs_attribute_ring_pointer_dirty) { - assert(sctx->chip_class >= GFX11); + assert(sctx->gfx_level >= GFX11); radeon_set_sh_reg(R_00B230_SPI_SHADER_USER_DATA_GS_0 + GFX9_SGPR_ATTRIBUTE_RING_ADDR * 4, sctx->screen->attribute_ring->gpu_address); sctx->gs_attribute_ring_pointer_dirty = false; @@ -2700,7 +2700,7 @@ void si_init_all_descriptors(struct si_context *sctx) unsigned first_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE; unsigned hs_sgpr0, gs_sgpr0; - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { hs_sgpr0 = R_00B420_SPI_SHADER_PGM_LO_HS; gs_sgpr0 = R_00B220_SPI_SHADER_PGM_LO_GS; } else { @@ -2710,7 +2710,7 @@ void si_init_all_descriptors(struct si_context *sctx) for (i = first_shader; i < SI_NUM_SHADERS; i++) { bool is_2nd = - sctx->chip_class >= GFX9 && (i == PIPE_SHADER_TESS_CTRL || i == PIPE_SHADER_GEOMETRY); + sctx->gfx_level >= GFX9 && (i == PIPE_SHADER_TESS_CTRL || i == PIPE_SHADER_GEOMETRY); unsigned num_sampler_slots = SI_NUM_IMAGE_SLOTS / 2 + SI_NUM_SAMPLERS; unsigned num_buffer_slots = SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS; int rel_dw_offset; @@ -2720,7 +2720,7 @@ void si_init_all_descriptors(struct si_context *sctx) if (i == PIPE_SHADER_TESS_CTRL) { rel_dw_offset = (hs_sgpr0 - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4; - } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */ + } else if (sctx->gfx_level >= GFX10) { /* PIPE_SHADER_GEOMETRY */ rel_dw_offset = (gs_sgpr0 - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4; } else { @@ -2740,7 +2740,7 @@ void si_init_all_descriptors(struct si_context *sctx) if (i == PIPE_SHADER_TESS_CTRL) { rel_dw_offset = (hs_sgpr0 + 4 - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4; - } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */ + } else if (sctx->gfx_level >= GFX10) { /* PIPE_SHADER_GEOMETRY */ rel_dw_offset = (gs_sgpr0 + 4 - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4; } else { @@ -2800,13 +2800,13 @@ void si_init_all_descriptors(struct si_context *sctx) /* Set default and immutable mappings. */ si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, - si_get_user_data_base(sctx->chip_class, TESS_OFF, GS_OFF, + si_get_user_data_base(sctx->gfx_level, TESS_OFF, GS_OFF, sctx->ngg, PIPE_SHADER_VERTEX)); si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, - si_get_user_data_base(sctx->chip_class, TESS_OFF, GS_OFF, + si_get_user_data_base(sctx->gfx_level, TESS_OFF, GS_OFF, NGG_OFF, PIPE_SHADER_TESS_CTRL)); si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, - si_get_user_data_base(sctx->chip_class, TESS_OFF, GS_OFF, + si_get_user_data_base(sctx->gfx_level, TESS_OFF, GS_OFF, NGG_OFF, PIPE_SHADER_GEOMETRY)); si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0); diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c index e6e4dca082c..87d0cdcd571 100644 --- a/src/gallium/drivers/radeonsi/si_fence.c +++ b/src/gallium/drivers/radeonsi/si_fence.c @@ -77,7 +77,7 @@ void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigne radeon_begin(cs); - if (ctx->chip_class >= GFX9 || (compute_ib && ctx->chip_class >= GFX7)) { + if (ctx->gfx_level >= GFX9 || (compute_ib && ctx->gfx_level >= GFX7)) { /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion * counters) must immediately precede every timestamp event to * prevent a GPU hang on GFX9. @@ -85,7 +85,7 @@ void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigne * Occlusion queries don't need to do it here, because they * always do ZPASS_DONE before the timestamp. */ - if (ctx->chip_class == GFX9 && !compute_ib && query_type != PIPE_QUERY_OCCLUSION_COUNTER && + if (ctx->gfx_level == GFX9 && !compute_ib && query_type != PIPE_QUERY_OCCLUSION_COUNTER && query_type != PIPE_QUERY_OCCLUSION_PREDICATE && query_type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) { struct si_screen *sscreen = ctx->screen; @@ -116,17 +116,17 @@ void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigne RADEON_USAGE_WRITE | RADEON_PRIO_QUERY); } - radeon_emit(PKT3(PKT3_RELEASE_MEM, ctx->chip_class >= GFX9 ? 6 : 5, 0)); + radeon_emit(PKT3(PKT3_RELEASE_MEM, ctx->gfx_level >= GFX9 ? 6 : 5, 0)); radeon_emit(op); radeon_emit(sel); radeon_emit(va); /* address lo */ radeon_emit(va >> 32); /* address hi */ radeon_emit(new_fence); /* immediate data lo */ radeon_emit(0); /* immediate data hi */ - if (ctx->chip_class >= GFX9) + if (ctx->gfx_level >= GFX9) radeon_emit(0); /* unused */ } else { - if (ctx->chip_class == GFX7 || ctx->chip_class == GFX8) { + if (ctx->gfx_level == GFX7 || ctx->gfx_level == GFX8) { struct si_resource *scratch = ctx->eop_bug_scratch; uint64_t va = scratch->gpu_address; @@ -164,7 +164,7 @@ unsigned si_cp_write_fence_dwords(struct si_screen *screen) { unsigned dwords = 6; - if (screen->info.chip_class == GFX7 || screen->info.chip_class == GFX8) + if (screen->info.gfx_level == GFX7 || screen->info.gfx_level == GFX8) dwords *= 2; return dwords; diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index 07d0a2457d6..f183b64529a 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -49,7 +49,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) struct si_screen *sscreen = (struct si_screen *)pscreen; /* Gfx8 (Polaris11) hangs, so don't enable this on Gfx8 and older chips. */ - bool enable_sparse = sscreen->info.chip_class >= GFX9 && + bool enable_sparse = sscreen->info.gfx_level >= GFX9 && sscreen->info.has_sparse_vm_mappings; switch (param) { @@ -174,7 +174,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return !(sscreen->debug_flags & DBG(NO_FAST_DISPLAY_LIST)); case PIPE_CAP_SHADER_SAMPLES_IDENTICAL: - return sscreen->info.chip_class < GFX11; + return sscreen->info.gfx_level < GFX11; case PIPE_CAP_GLSL_ZERO_INIT: return 2; @@ -189,7 +189,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return !sscreen->use_ngg_streamout; case PIPE_CAP_POST_DEPTH_COVERAGE: - return sscreen->info.chip_class >= GFX10; + return sscreen->info.gfx_level >= GFX10; case PIPE_CAP_GRAPHICS: return sscreen->info.has_graphics; @@ -275,7 +275,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 32; case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: - return sscreen->info.chip_class <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0; + return sscreen->info.gfx_level <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0; /* Stream output. */ case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: @@ -307,12 +307,12 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: if (!sscreen->info.has_3d_cube_border_color_mipmap) return 0; - if (sscreen->info.chip_class >= GFX10) + if (sscreen->info.gfx_level >= GFX10) return 14; /* textures support 8192, but layered rendering supports 2048 */ return 12; case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: - if (sscreen->info.chip_class >= GFX10) + if (sscreen->info.gfx_level >= GFX10) return 8192; /* textures support 8192, but layered rendering supports 2048 */ return 2048; @@ -612,12 +612,12 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil switch (codec) { case PIPE_VIDEO_FORMAT_MPEG12: - if (sscreen->info.chip_class >= GFX11) + if (sscreen->info.gfx_level >= GFX11) return false; else return profile != PIPE_VIDEO_PROFILE_MPEG1; case PIPE_VIDEO_FORMAT_MPEG4: - if (sscreen->info.chip_class >= GFX11) + if (sscreen->info.gfx_level >= GFX11) return false; else return true; @@ -629,7 +629,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil } return true; case PIPE_VIDEO_FORMAT_VC1: - if (sscreen->info.chip_class >= GFX11) + if (sscreen->info.gfx_level >= GFX11) return false; else return true; @@ -1026,7 +1026,7 @@ void si_init_screen_get_functions(struct si_screen *sscreen) /* fma32 is too slow for gpu < gfx9, so force it only when gpu >= gfx9 */ bool force_fma32 = - sscreen->info.chip_class >= GFX9 && sscreen->options.force_use_fma32; + sscreen->info.gfx_level >= GFX9 && sscreen->options.force_use_fma32; const struct nir_shader_compiler_options nir_options = { .lower_scmp = true, @@ -1055,11 +1055,11 @@ void si_init_screen_get_functions(struct si_screen *sscreen) * gfx9 and newer prefer FMA for F16 because of the packed instruction. * gfx10 and older prefer MAD for F32 because of the legacy instruction. */ - .lower_ffma16 = sscreen->info.chip_class < GFX9, - .lower_ffma32 = sscreen->info.chip_class < GFX10_3 && !force_fma32, + .lower_ffma16 = sscreen->info.gfx_level < GFX9, + .lower_ffma32 = sscreen->info.gfx_level < GFX10_3 && !force_fma32, .lower_ffma64 = false, - .fuse_ffma16 = sscreen->info.chip_class >= GFX9, - .fuse_ffma32 = sscreen->info.chip_class >= GFX10_3 || force_fma32, + .fuse_ffma16 = sscreen->info.gfx_level >= GFX9, + .fuse_ffma32 = sscreen->info.gfx_level >= GFX10_3 || force_fma32, .fuse_ffma64 = true, .lower_fmod = true, .lower_pack_snorm_4x8 = true, diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index 233280130eb..5fb7eef195e 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -57,7 +57,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h if (!sscreen->info.kernel_flushes_tc_l2_after_ib) { wait_flags |= wait_ps_cs | SI_CONTEXT_INV_L2; - } else if (ctx->chip_class == GFX6) { + } else if (ctx->gfx_level == GFX6) { /* The kernel flushes L2 before shaders are finished. */ wait_flags |= wait_ps_cs; } else if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW) || @@ -112,13 +112,13 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h /* Make sure CP DMA is idle at the end of IBs after L2 prefetches * because the kernel doesn't wait for it. */ - if (ctx->chip_class >= GFX7) + if (ctx->gfx_level >= GFX7) si_cp_dma_wait_for_idle(ctx, &ctx->gfx_cs); /* If we use s_sendmsg to set tess factors to all 0 or all 1 instead of writing to the tess * factor buffer, we need this at the end of command buffers: */ - if (ctx->chip_class == GFX11 && ctx->tess_rings) { + if (ctx->gfx_level == GFX11 && ctx->tess_rings) { radeon_begin(cs); radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0)); @@ -490,7 +490,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs) if (!has_clear_state || ctx->blend_color_any_nonzeros) si_mark_atom_dirty(ctx, &ctx->atoms.s.blend_color); si_mark_atom_dirty(ctx, &ctx->atoms.s.db_render_state); - if (ctx->chip_class >= GFX9) + if (ctx->gfx_level >= GFX9) si_mark_atom_dirty(ctx, &ctx->atoms.s.dpbb_state); si_mark_atom_dirty(ctx, &ctx->atoms.s.stencil_ref); si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_map); @@ -574,15 +574,15 @@ void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs, uns { bool compute_ib = !sctx->has_graphics; - assert(sctx->chip_class <= GFX9); + assert(sctx->gfx_level <= GFX9); /* This seems problematic with GFX7 (see #4764) */ - if (sctx->chip_class != GFX7) + if (sctx->gfx_level != GFX7) cp_coher_cntl |= 1u << 31; /* don't sync PFP, i.e. execute the sync in ME */ radeon_begin(cs); - if (sctx->chip_class == GFX9 || compute_ib) { + if (sctx->gfx_level == GFX9 || compute_ib) { /* Flush caches and wait for the caches to assert idle. */ radeon_emit(PKT3(PKT3_ACQUIRE_MEM, 5, 0)); radeon_emit(cp_coher_cntl); /* CP_COHER_CNTL */ @@ -695,7 +695,7 @@ void gfx10_emit_cache_flush(struct si_context *ctx, struct radeon_cmdbuf *cs) } /* Gfx11 can't flush DB_META and should use a TS event instead. */ - if (ctx->chip_class != GFX11 && flags & SI_CONTEXT_FLUSH_AND_INV_DB) { + if (ctx->gfx_level != GFX11 && flags & SI_CONTEXT_FLUSH_AND_INV_DB) { /* Flush HTILE. Will wait for idle later. */ radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); @@ -710,7 +710,7 @@ void gfx10_emit_cache_flush(struct si_context *ctx, struct radeon_cmdbuf *cs) } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) { cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS; } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) { - if (ctx->chip_class == GFX11) + if (ctx->gfx_level == GFX11) cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT; else cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS; @@ -843,7 +843,7 @@ void si_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs) uint32_t cp_coher_cntl = 0; const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB); - assert(sctx->chip_class <= GFX9); + assert(sctx->gfx_level <= GFX9); if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) sctx->num_cb_cache_flushes++; @@ -863,7 +863,7 @@ void si_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs) if (flags & SI_CONTEXT_INV_SCACHE) cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1); - if (sctx->chip_class <= GFX8) { + if (sctx->gfx_level <= GFX8) { if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) { cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) | S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) | S_0085F0_CB2_DEST_BASE_ENA(1) | @@ -872,7 +872,7 @@ void si_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs) S_0085F0_CB7_DEST_BASE_ENA(1); /* Necessary for DCC */ - if (sctx->chip_class == GFX8) + if (sctx->gfx_level == GFX8) si_cp_release_mem(sctx, cs, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE, EOP_DATA_SEL_DISCARD, NULL, 0, 0, SI_NOT_QUERY); } @@ -935,7 +935,7 @@ void si_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs) /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't * wait for idle on GFX9. We have to use a TS event. */ - if (sctx->chip_class == GFX9 && flush_cb_db) { + if (sctx->gfx_level == GFX9 && flush_cb_db) { uint64_t va; unsigned tc_flags, cb_db_event; @@ -1011,13 +1011,13 @@ void si_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs) * * GFX6-GFX7 don't support L2 write-back. */ - if (flags & SI_CONTEXT_INV_L2 || (sctx->chip_class <= GFX7 && (flags & SI_CONTEXT_WB_L2))) { + if (flags & SI_CONTEXT_INV_L2 || (sctx->gfx_level <= GFX7 && (flags & SI_CONTEXT_WB_L2))) { /* Invalidate L1 & L2. (L1 is always invalidated on GFX6) * WB must be set on GFX8+ when TC_ACTION is set. */ si_emit_surface_sync(sctx, cs, cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | S_0085F0_TCL1_ACTION_ENA(1) | - S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8)); + S_0301F0_TC_WB_ACTION_ENA(sctx->gfx_level >= GFX8)); cp_coher_cntl = 0; sctx->num_L2_invalidates++; } else { diff --git a/src/gallium/drivers/radeonsi/si_gpu_load.c b/src/gallium/drivers/radeonsi/si_gpu_load.c index 0cc347c86f2..b6cd976a404 100644 --- a/src/gallium/drivers/radeonsi/si_gpu_load.c +++ b/src/gallium/drivers/radeonsi/si_gpu_load.c @@ -101,7 +101,7 @@ static void si_update_mmio_counters(struct si_screen *sscreen, union si_mmio_cou UPDATE_COUNTER(gui, GUI_ACTIVE); gui_busy = GUI_ACTIVE(value); - if (sscreen->info.chip_class == GFX7 || sscreen->info.chip_class == GFX8) { + if (sscreen->info.gfx_level == GFX7 || sscreen->info.gfx_level == GFX8) { /* SRBM_STATUS2 */ sscreen->ws->read_registers(sscreen->ws, SRBM_STATUS2, 1, &value); @@ -109,7 +109,7 @@ static void si_update_mmio_counters(struct si_screen *sscreen, union si_mmio_cou sdma_busy = SDMA_BUSY(value); } - if (sscreen->info.chip_class >= GFX8) { + if (sscreen->info.gfx_level >= GFX8) { /* CP_STAT */ sscreen->ws->read_registers(sscreen->ws, CP_STAT, 1, &value); diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c index a0e62ae7534..4097f7904e2 100644 --- a/src/gallium/drivers/radeonsi/si_perfcounter.c +++ b/src/gallium/drivers/radeonsi/si_perfcounter.c @@ -69,7 +69,7 @@ static void si_pc_emit_instance(struct si_context *sctx, int se, int instance) value |= S_030800_SE_BROADCAST_WRITES(1); } - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { /* TODO: Expose counters from each shader array separately if needed. */ value |= S_030800_SA_BROADCAST_WRITES(1); } @@ -276,15 +276,15 @@ static void si_pc_query_destroy(struct si_context *sctx, struct si_query *squery void si_inhibit_clockgating(struct si_context *sctx, struct radeon_cmdbuf *cs, bool inhibit) { - if (sctx->chip_class >= GFX11) + if (sctx->gfx_level >= GFX11) return; radeon_begin(&sctx->gfx_cs); - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { radeon_set_uconfig_reg(R_037390_RLC_PERFMON_CLK_CNTL, S_037390_PERFMON_CLOCK_STATE(inhibit)); - } else if (sctx->chip_class >= GFX8) { + } else if (sctx->gfx_level >= GFX8) { radeon_set_uconfig_reg(R_0372FC_RLC_PERFMON_CLK_CNTL, S_0372FC_PERFMON_CLOCK_STATE(inhibit)); } @@ -908,7 +908,7 @@ si_spm_init(struct si_context *sctx) /* L2 cache hit */ {GL2C, 0, 0x3}, /* Number of GL2C requests. */ - {GL2C, 0, info->chip_class >= GFX10_3 ? 0x2b : 0x23}, /* Number of GL2C misses. */ + {GL2C, 0, info->gfx_level >= GFX10_3 ? 0x2b : 0x23}, /* Number of GL2C misses. */ }; if (!ac_init_perfcounters(info, false, false, pc)) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 48d7844732c..8b8836ae57c 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -139,7 +139,7 @@ bool si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compil /* Only create the less-optimizing version of the compiler on APUs * predating Ryzen (Raven). */ bool create_low_opt_compiler = - !sscreen->info.has_dedicated_vram && sscreen->info.chip_class <= GFX8; + !sscreen->info.has_dedicated_vram && sscreen->info.gfx_level <= GFX8; enum ac_target_machine_options tm_options = (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) | @@ -199,7 +199,7 @@ static void si_destroy_context(struct pipe_context *context) si_release_all_descriptors(sctx); - if (sctx->chip_class >= GFX10 && sctx->has_graphics) + if (sctx->gfx_level >= GFX10 && sctx->has_graphics) gfx10_destroy_query(sctx); if (sctx->thread_trace) @@ -470,7 +470,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign if (!sctx) return NULL; - sctx->has_graphics = sscreen->info.chip_class == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY); + sctx->has_graphics = sscreen->info.gfx_level == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY); if (flags & PIPE_CONTEXT_DEBUG) sscreen->record_llvm_ir = true; /* racy but not critical */ @@ -487,9 +487,9 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign sctx->ws = sscreen->ws; sctx->family = sscreen->info.family; - sctx->chip_class = sscreen->info.chip_class; + sctx->gfx_level = sscreen->info.gfx_level; - if (sctx->chip_class == GFX7 || sctx->chip_class == GFX8 || sctx->chip_class == GFX9) { + if (sctx->gfx_level == GFX7 || sctx->gfx_level == GFX8 || sctx->gfx_level == GFX9) { sctx->eop_bug_scratch = si_aligned_buffer_create( &sscreen->b, SI_RESOURCE_FLAG_DRIVER_INTERNAL, PIPE_USAGE_DEFAULT, 16 * sscreen->info.max_render_backends, 256); @@ -560,7 +560,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign si_shader_change_notify(sctx); /* Initialize context functions used by graphics and compute. */ - if (sctx->chip_class >= GFX10) + if (sctx->gfx_level >= GFX10) sctx->emit_cache_flush = gfx10_emit_cache_flush; else sctx->emit_cache_flush = si_emit_cache_flush; @@ -587,7 +587,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign /* Initialize graphics-only context functions. */ if (sctx->has_graphics) { - if (sctx->chip_class >= GFX10) + if (sctx->gfx_level >= GFX10) gfx10_init_query(sctx); si_init_msaa_functions(sctx); si_init_shader_functions(sctx); @@ -614,7 +614,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign sctx->discard_rasterizer_state = util_blitter_get_discard_rasterizer_state(sctx->blitter); sctx->queued.named.rasterizer = sctx->discard_rasterizer_state; - switch (sctx->chip_class) { + switch (sctx->gfx_level) { case GFX6: si_init_draw_functions_GFX6(sctx); break; @@ -637,7 +637,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign si_init_draw_functions_GFX11(sctx); break; default: - unreachable("unhandled chip class"); + unreachable("unhandled gfx level"); } } @@ -656,7 +656,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign sctx->b.create_video_buffer = vl_video_buffer_create; } - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { sctx->wait_mem_scratch = si_aligned_buffer_create(screen, PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL, @@ -668,7 +668,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */ - if (sctx->chip_class == GFX7) { + if (sctx->gfx_level == GFX7) { sctx->null_const_buf.buffer = pipe_aligned_buffer_create(screen, SI_RESOURCE_FLAG_32BIT | SI_RESOURCE_FLAG_DRIVER_INTERNAL, @@ -714,7 +714,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign } /* Set immutable fields of shader keys. */ - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { /* The LS output / HS input layout can be communicated * directly instead of via user SGPRs for merged LS-HS. * This also enables jumping over the VS prolog for HS-only waves. @@ -741,7 +741,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign si_cp_write_data(sctx, sctx->wait_mem_scratch_tmz, 0, 4, V_370_MEM, V_370_ME, &sctx->wait_mem_number); - if (sctx->chip_class == GFX7) { + if (sctx->gfx_level == GFX7) { /* Clear the NULL constant buffer, because loads should return zeros. * Note that this forces CP DMA to be used, because clover deadlocks * for some reason when the compute codepath is used. @@ -814,7 +814,7 @@ static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, v ctx = si_create_context(screen, flags); - if (ctx && sscreen->info.chip_class >= GFX9 && sscreen->debug_flags & DBG(SQTT)) { + if (ctx && sscreen->info.gfx_level >= GFX9 && sscreen->debug_flags & DBG(SQTT)) { if (ac_check_profile_state(&sscreen->info)) { fprintf(stderr, "radeonsi: Canceling RGP trace request as a hang condition has been " "detected. Force the GPU into a profiling mode with e.g. " @@ -942,7 +942,7 @@ static void si_destroy_screen(struct pipe_screen *pscreen) static void si_init_gs_info(struct si_screen *sscreen) { - sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class, sscreen->info.family); + sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.gfx_level, sscreen->info.family); } static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags) @@ -1068,7 +1068,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, sscreen->options.enable_sam, sscreen->options.disable_sam); - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { sscreen->se_tile_repeat = 32 * sscreen->info.max_se; } else { ac_get_raster_config(&sscreen->info, &sscreen->pa_sc_raster_config, @@ -1151,7 +1151,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, return NULL; } - if (sscreen->info.chip_class < GFX10_3) + if (sscreen->info.gfx_level < GFX10_3) sscreen->options.vrs2x2 = false; si_disk_cache_create(sscreen); @@ -1229,17 +1229,17 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, sscreen->has_draw_indirect_multi = (sscreen->info.family >= CHIP_POLARIS10) || - (sscreen->info.chip_class == GFX8 && sscreen->info.pfp_fw_version >= 121 && + (sscreen->info.gfx_level == GFX8 && sscreen->info.pfp_fw_version >= 121 && sscreen->info.me_fw_version >= 87) || - (sscreen->info.chip_class == GFX7 && sscreen->info.pfp_fw_version >= 211 && + (sscreen->info.gfx_level == GFX7 && sscreen->info.pfp_fw_version >= 211 && sscreen->info.me_fw_version >= 173) || - (sscreen->info.chip_class == GFX6 && sscreen->info.pfp_fw_version >= 79 && + (sscreen->info.gfx_level == GFX6 && sscreen->info.pfp_fw_version >= 79 && sscreen->info.me_fw_version >= 142); sscreen->has_out_of_order_rast = sscreen->info.has_out_of_order_rast && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER)); - if (sscreen->info.chip_class >= GFX11) { + if (sscreen->info.gfx_level >= GFX11) { sscreen->use_ngg = true; sscreen->use_ngg_streamout = true; /* TODO: Disable for now. Investigate if it helps. */ @@ -1247,7 +1247,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, !(sscreen->debug_flags & DBG(NO_NGG_CULLING)); } else { sscreen->use_ngg = !(sscreen->debug_flags & DBG(NO_NGG)) && - sscreen->info.chip_class >= GFX10 && + sscreen->info.gfx_level >= GFX10 && (sscreen->info.family != CHIP_NAVI14 || sscreen->info.is_pro_graphics); sscreen->use_ngg_streamout = false; @@ -1260,10 +1260,10 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, /* Only set this for the cases that are known to work, which are: * - GFX9 if bpp >= 4 (in bytes) */ - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { memset(sscreen->allow_dcc_msaa_clear_to_reg_for_bpp, true, sizeof(sscreen->allow_dcc_msaa_clear_to_reg_for_bpp)); - } else if (sscreen->info.chip_class == GFX9) { + } else if (sscreen->info.gfx_level == GFX9) { for (unsigned bpp_log2 = util_logbase2(1); bpp_log2 <= util_logbase2(16); bpp_log2++) sscreen->allow_dcc_msaa_clear_to_reg_for_bpp[bpp_log2] = true; } @@ -1273,14 +1273,14 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, */ sscreen->always_allow_dcc_stores = !(sscreen->debug_flags & DBG(NO_DCC_STORE)) && (sscreen->debug_flags & DBG(DCC_STORE) || - sscreen->info.chip_class >= GFX11 || /* always enabled on gfx11 */ - (sscreen->info.chip_class >= GFX10_3 && + sscreen->info.gfx_level >= GFX11 || /* always enabled on gfx11 */ + (sscreen->info.gfx_level >= GFX10_3 && !sscreen->info.has_dedicated_vram)); sscreen->dpbb_allowed = !(sscreen->debug_flags & DBG(NO_DPBB)) && - (sscreen->info.chip_class >= GFX10 || + (sscreen->info.gfx_level >= GFX10 || /* Only enable primitive binning on gfx9 APUs by default. */ - (sscreen->info.chip_class == GFX9 && !sscreen->info.has_dedicated_vram) || + (sscreen->info.gfx_level == GFX9 && !sscreen->info.has_dedicated_vram) || sscreen->debug_flags & DBG(DPBB)); if (sscreen->dpbb_allowed) { @@ -1312,7 +1312,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0; sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE; - if (sscreen->info.chip_class <= GFX8) { + if (sscreen->info.gfx_level <= GFX8) { sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2; sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2; } @@ -1347,7 +1347,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, sscreen->ngg_subgroup_size = 128; - if (sscreen->info.chip_class >= GFX11) { + if (sscreen->info.gfx_level >= GFX11) { /* TODO: tweak this */ unsigned attr_ring_size_per_se = align(1400000, 64 * 1024); unsigned attr_ring_size = attr_ring_size_per_se * sscreen->info.max_se; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 42756da8347..bf107bfaffa 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -940,7 +940,7 @@ struct si_context { struct pipe_context b; /* base class */ enum radeon_family family; - enum chip_class chip_class; + enum amd_gfx_level gfx_level; struct radeon_winsys *ws; struct radeon_winsys_ctx *ctx; @@ -1600,7 +1600,7 @@ bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level, enum pipe_format view_format); void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex, unsigned level, enum pipe_format view_format); -unsigned si_translate_colorswap(enum chip_class chip_class, enum pipe_format format, +unsigned si_translate_colorswap(enum amd_gfx_level gfx_level, enum pipe_format format, bool do_endian_swap); bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex); void si_init_screen_texture_functions(struct si_screen *sscreen); @@ -1788,12 +1788,12 @@ static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_VCACHE; sctx->force_cb_shader_coherent = false; - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { if (sctx->screen->info.tcc_rb_non_coherent) sctx->flags |= SI_CONTEXT_INV_L2; else if (shaders_read_metadata) sctx->flags |= SI_CONTEXT_INV_L2_METADATA; - } else if (sctx->chip_class == GFX9) { + } else if (sctx->gfx_level == GFX9) { /* Single-sample color is coherent with shaders on GFX9, but * L2 metadata must be flushed if shaders read metadata. * (DCC, CMASK). @@ -1813,12 +1813,12 @@ static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned { sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE; - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { if (sctx->screen->info.tcc_rb_non_coherent) sctx->flags |= SI_CONTEXT_INV_L2; else if (shaders_read_metadata) sctx->flags |= SI_CONTEXT_INV_L2_METADATA; - } else if (sctx->chip_class == GFX9) { + } else if (sctx->gfx_level == GFX9) { /* Single-sample depth (not stencil) is coherent with shaders * on GFX9, but L2 metadata must be flushed if shaders read * metadata. @@ -1847,7 +1847,7 @@ static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsi return false; struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen; - if (sscreen->info.chip_class >= GFX8) { + if (sscreen->info.gfx_level >= GFX8) { return level < tex->surface.num_meta_levels; } else { /* GFX6-7 don't have TC-compatible HTILE, which means they have to run @@ -2037,17 +2037,17 @@ static inline unsigned si_get_num_coverage_samples(struct si_context *sctx) } static unsigned ALWAYS_INLINE -si_num_vbos_in_user_sgprs_inline(enum chip_class chip_class) +si_num_vbos_in_user_sgprs_inline(enum amd_gfx_level gfx_level) { /* This decreases CPU overhead if all descriptors are in user SGPRs because we don't * have to allocate and count references for the upload buffer. */ - return chip_class >= GFX9 ? 5 : 1; + return gfx_level >= GFX9 ? 5 : 1; } static inline unsigned si_num_vbos_in_user_sgprs(struct si_screen *sscreen) { - return si_num_vbos_in_user_sgprs_inline(sscreen->info.chip_class); + return si_num_vbos_in_user_sgprs_inline(sscreen->info.gfx_level); } #define PRINT_ERR(fmt, args...) \ diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c index 7977192e37e..7dd488d9980 100644 --- a/src/gallium/drivers/radeonsi/si_query.c +++ b/src/gallium/drivers/radeonsi/si_query.c @@ -731,7 +731,7 @@ static struct pipe_query *si_query_hw_create(struct si_screen *sscreen, unsigned query->b.num_cs_dw_suspend = 6 + si_cp_write_fence_dwords(sscreen); query->index = index; if ((index == PIPE_STAT_QUERY_GS_PRIMITIVES || index == PIPE_STAT_QUERY_GS_INVOCATIONS) && - sscreen->use_ngg && (sscreen->info.chip_class >= GFX10 && sscreen->info.chip_class <= GFX10_3)) + sscreen->use_ngg && (sscreen->info.gfx_level >= GFX10 && sscreen->info.gfx_level <= GFX10_3)) query->flags |= SI_QUERY_EMULATE_GS_COUNTERS; break; default: @@ -803,7 +803,7 @@ static void si_query_hw_do_emit_start(struct si_context *sctx, struct si_query_h case PIPE_QUERY_OCCLUSION_PREDICATE: case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: { radeon_begin(cs); - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { uint64_t rb_mask = BITFIELD64_MASK(sctx->screen->info.max_render_backends); radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); @@ -815,7 +815,7 @@ static void si_query_hw_do_emit_start(struct si_context *sctx, struct si_query_h } radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); - if (sctx->chip_class >= GFX11) + if (sctx->gfx_level >= GFX11) radeon_emit(EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_DUMP) | EVENT_INDEX(1)); else radeon_emit(EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1)); @@ -926,7 +926,7 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx, struct si_query_hw va += 8; radeon_begin(cs); radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); - if (sctx->chip_class >= GFX11) + if (sctx->gfx_level >= GFX11) radeon_emit(EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_DUMP) | EVENT_INDEX(1)); else radeon_emit(EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1)); @@ -1031,7 +1031,7 @@ static void emit_set_predicate(struct si_context *ctx, struct si_resource *buf, radeon_begin(cs); - if (ctx->chip_class >= GFX9) { + if (ctx->gfx_level >= GFX9) { radeon_emit(PKT3(PKT3_SET_PREDICATION, 2, 0)); radeon_emit(op); radeon_emit(va); @@ -1668,8 +1668,8 @@ static void si_render_condition(struct pipe_context *ctx, struct pipe_query *que * SET_PREDICATION packets to give the wrong answer for * non-inverted stream overflow predication. */ - if (((sctx->chip_class == GFX8 && sctx->screen->info.pfp_fw_feature < 49) || - (sctx->chip_class == GFX9 && sctx->screen->info.pfp_fw_feature < 38)) && + if (((sctx->gfx_level == GFX8 && sctx->screen->info.pfp_fw_feature < 49) || + (sctx->gfx_level == GFX9 && sctx->screen->info.pfp_fw_feature < 38)) && !condition && (squery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE || (squery->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE && @@ -1837,7 +1837,7 @@ static unsigned si_get_num_queries(struct si_screen *sscreen) { /* amdgpu */ if (sscreen->info.is_amdgpu) { - if (sscreen->info.chip_class >= GFX8) + if (sscreen->info.gfx_level >= GFX8) return ARRAY_SIZE(si_driver_query_list); else return ARRAY_SIZE(si_driver_query_list) - 7; @@ -1845,7 +1845,7 @@ static unsigned si_get_num_queries(struct si_screen *sscreen) /* radeon */ if (sscreen->info.has_read_registers_query) { - if (sscreen->info.chip_class == GFX7) + if (sscreen->info.gfx_level == GFX7) return ARRAY_SIZE(si_driver_query_list) - 6; else return ARRAY_SIZE(si_driver_query_list) - 7; diff --git a/src/gallium/drivers/radeonsi/si_sdma_copy_image.c b/src/gallium/drivers/radeonsi/si_sdma_copy_image.c index 8171d4917a7..46bc46f7d67 100644 --- a/src/gallium/drivers/radeonsi/si_sdma_copy_image.c +++ b/src/gallium/drivers/radeonsi/si_sdma_copy_image.c @@ -74,7 +74,7 @@ static bool si_translate_format_to_hw(struct si_context *sctx, enum pipe_format format, unsigned *hw_fmt, unsigned *hw_type) { const struct util_format_description *desc = util_format_description(format); - *hw_fmt = si_translate_colorformat(sctx->chip_class, format); + *hw_fmt = si_translate_colorformat(sctx->gfx_level, format); int firstchan; for (firstchan = 0; firstchan < 4; firstchan++) { @@ -258,7 +258,7 @@ bool cik_sdma_copy_texture(struct si_context *sctx, struct si_texture *sdst, str src_pitch <= (1 << 14) && dst_pitch <= (1 << 14) && src_slice_pitch <= (1 << 28) && dst_slice_pitch <= (1 << 28) && copy_width <= (1 << 14) && copy_height <= (1 << 14) && /* HW limitation - GFX7: */ - (sctx->chip_class != GFX7 || + (sctx->gfx_level != GFX7 || (copy_width < (1 << 14) && copy_height < (1 << 14))) && /* HW limitation - some GFX7 parts: */ ((sctx->family != CHIP_BONAIRE && sctx->family != CHIP_KAVERI) || @@ -278,7 +278,7 @@ bool cik_sdma_copy_texture(struct si_context *sctx, struct si_texture *sdst, str radeon_emit(0); radeon_emit((dst_pitch - 1) << 16); radeon_emit(dst_slice_pitch - 1); - if (sctx->chip_class == GFX7) { + if (sctx->gfx_level == GFX7) { radeon_emit(copy_width | (copy_height << 16)); radeon_emit(0); } else { @@ -402,7 +402,7 @@ bool cik_sdma_copy_texture(struct si_context *sctx, struct si_texture *sdst, str radeon_emit(0); radeon_emit(((linear_pitch - 1) << 16)); radeon_emit(linear_slice_pitch - 1); - if (sctx->chip_class == GFX7) { + if (sctx->gfx_level == GFX7) { radeon_emit(copy_width_aligned | (copy_height << 16)); radeon_emit(1); } else { @@ -422,7 +422,7 @@ bool si_sdma_copy_image(struct si_context *sctx, struct si_texture *dst, struct struct radeon_winsys *ws = sctx->ws; if (!sctx->sdma_cs) { - if (sctx->screen->debug_flags & DBG(NO_DMA) || sctx->chip_class < GFX7) + if (sctx->screen->debug_flags & DBG(NO_DMA) || sctx->gfx_level < GFX7) return false; sctx->sdma_cs = CALLOC_STRUCT(radeon_cmdbuf); @@ -435,7 +435,7 @@ bool si_sdma_copy_image(struct si_context *sctx, struct si_texture *dst, struct return false; /* Decompress DCC on older chips */ - if (vi_dcc_enabled(src, 0) && sctx->chip_class < GFX10) + if (vi_dcc_enabled(src, 0) && sctx->gfx_level < GFX10) si_decompress_dcc(sctx, src); /* TODO: DCC compression is possible on GFX10+. See si_set_mutable_tex_desc_fields for * additional constraints. @@ -447,7 +447,7 @@ bool si_sdma_copy_image(struct si_context *sctx, struct si_texture *dst, struct /* Always flush the gfx queue to get the winsys to handle the dependencies for us. */ si_flush_gfx_cs(sctx, 0, NULL); - switch (sctx->chip_class) { + switch (sctx->gfx_level) { case GFX7: case GFX8: if (!cik_sdma_copy_texture(sctx, dst, src)) @@ -456,7 +456,7 @@ bool si_sdma_copy_image(struct si_context *sctx, struct si_texture *dst, struct case GFX9: case GFX10: case GFX10_3: - if (!si_sdma_v4_v5_copy_texture(sctx, dst, src, sctx->chip_class >= GFX10)) + if (!si_sdma_v4_v5_copy_texture(sctx, dst, src, sctx->gfx_level >= GFX10)) return false; break; default: diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 1777f73fb46..4b1c3f7f7ce 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -46,7 +46,7 @@ static void si_dump_shader_key(const struct si_shader *shader, FILE *f); /** Whether the shader runs as a combination of multiple API shaders */ bool si_is_multi_part_shader(struct si_shader *shader) { - if (shader->selector->screen->info.chip_class <= GFX8 || + if (shader->selector->screen->info.gfx_level <= GFX8 || shader->selector->stage > MESA_SHADER_GEOMETRY) return false; @@ -220,10 +220,10 @@ unsigned si_get_max_workgroup_size(const struct si_shader *shader) case MESA_SHADER_TESS_CTRL: /* Return this so that LLVM doesn't remove s_barrier * instructions on chips where we use s_barrier. */ - return shader->selector->screen->info.chip_class >= GFX7 ? 128 : 0; + return shader->selector->screen->info.gfx_level >= GFX7 ? 128 : 0; case MESA_SHADER_GEOMETRY: - return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 0; + return shader->selector->screen->info.gfx_level >= GFX9 ? 128 : 0; case MESA_SHADER_COMPUTE: break; /* see below */ @@ -306,11 +306,11 @@ static void declare_vs_input_vgprs(struct si_shader_context *ctx, unsigned *num_ ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.vertex_id); if (shader->key.ge.as_ls) { - if (ctx->screen->info.chip_class >= GFX11) { + if (ctx->screen->info.gfx_level >= GFX11) { ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user VGPR */ ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user VGPR */ ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.instance_id); - } else if (ctx->screen->info.chip_class >= GFX10) { + } else if (ctx->screen->info.gfx_level >= GFX10) { ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.vs_rel_patch_id); ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user VGPR */ ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.instance_id); @@ -319,7 +319,7 @@ static void declare_vs_input_vgprs(struct si_shader_context *ctx, unsigned *num_ ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.instance_id); ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* unused */ } - } else if (ctx->screen->info.chip_class >= GFX10) { + } else if (ctx->screen->info.gfx_level >= GFX10) { ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* user VGPR */ ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.vs_prim_id); /* user vgpr or PrimID (legacy) */ @@ -394,7 +394,7 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader) memset(&ctx->args, 0, sizeof(ctx->args)); /* Set MERGED shaders. */ - if (ctx->screen->info.chip_class >= GFX9 && stage <= MESA_SHADER_GEOMETRY) { + if (ctx->screen->info.gfx_level >= GFX9 && stage <= MESA_SHADER_GEOMETRY) { if (shader->key.ge.as_ls || stage == MESA_SHADER_TESS_CTRL) stage = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */ else if (shader->key.ge.as_es || shader->key.ge.as_ngg || stage == MESA_SHADER_GEOMETRY) @@ -471,7 +471,7 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader) ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.merged_wave_info); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tcs_factor_offset); - if (ctx->screen->info.chip_class >= GFX11) + if (ctx->screen->info.gfx_level >= GFX11) ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tcs_wave_id); else ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.scratch_offset); @@ -544,7 +544,7 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader) ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.merged_wave_info); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); - if (ctx->screen->info.chip_class >= GFX11) + if (ctx->screen->info.gfx_level >= GFX11) ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.gs_attr_offset); else ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.scratch_offset); @@ -578,7 +578,7 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader) } ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &ctx->small_prim_cull_info); - if (ctx->screen->info.chip_class >= GFX11) + if (ctx->screen->info.gfx_level >= GFX11) ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->gs_attr_address); else ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); /* unused */ @@ -777,7 +777,7 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader) /* Hardware VGPRs. */ /* Thread IDs are packed in VGPR0, 10 bits per component or stored in 3 separate VGPRs */ - if (ctx->screen->info.chip_class >= GFX11 || + if (ctx->screen->info.gfx_level >= GFX11 || (!ctx->screen->info.has_graphics && ctx->screen->info.family >= CHIP_ALDEBARAN)) ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.local_invocation_ids); else @@ -801,8 +801,8 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader) static unsigned get_lds_granularity(struct si_screen *screen, gl_shader_stage stage) { - return screen->info.chip_class >= GFX11 && stage == MESA_SHADER_FRAGMENT ? 1024 : - screen->info.chip_class >= GFX7 ? 512 : 256; + return screen->info.gfx_level >= GFX11 && stage == MESA_SHADER_FRAGMENT ? 1024 : + screen->info.gfx_level >= GFX7 ? 512 : 256; } static bool si_shader_binary_open(struct si_screen *screen, struct si_shader *shader, @@ -830,7 +830,7 @@ static bool si_shader_binary_open(struct si_screen *screen, struct si_shader *sh struct ac_rtld_symbol lds_symbols[2]; unsigned num_lds_symbols = 0; - if (sel && screen->info.chip_class >= GFX9 && !shader->is_gs_copy_shader && + if (sel && screen->info.gfx_level >= GFX9 && !shader->is_gs_copy_shader && (sel->stage == MESA_SHADER_GEOMETRY || (sel->stage <= MESA_SHADER_GEOMETRY && shader->key.ge.as_ngg))) { struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++]; @@ -877,7 +877,7 @@ static unsigned si_get_shader_binary_size(struct si_screen *screen, struct si_sh return size; } -static bool si_get_external_symbol(enum chip_class chip_class, void *data, const char *name, +static bool si_get_external_symbol(enum amd_gfx_level gfx_level, void *data, const char *name, uint64_t *value) { uint64_t *scratch_va = data; @@ -890,7 +890,7 @@ static bool si_get_external_symbol(enum chip_class chip_class, void *data, const /* Enable scratch coalescing. */ *value = S_008F04_BASE_ADDRESS_HI(*scratch_va >> 32); - if (chip_class >= GFX11) + if (gfx_level >= GFX11) *value |= S_008F04_SWIZZLE_ENABLE_GFX11(1); else *value |= S_008F04_SWIZZLE_ENABLE_GFX6(1); @@ -1234,7 +1234,7 @@ static void si_dump_shader_key(const struct si_shader *shader, FILE *f) break; case MESA_SHADER_TESS_CTRL: - if (shader->selector->screen->info.chip_class >= GFX9) { + if (shader->selector->screen->info.gfx_level >= GFX9) { si_dump_shader_key_vs(key, &key->ge.part.tcs.ls_prolog, "part.tcs.ls_prolog", f); } fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->ge.part.tcs.epilog.prim_mode); @@ -1254,7 +1254,7 @@ static void si_dump_shader_key(const struct si_shader *shader, FILE *f) if (shader->is_gs_copy_shader) break; - if (shader->selector->screen->info.chip_class >= GFX9 && + if (shader->selector->screen->info.gfx_level >= GFX9 && key->ge.part.gs.es->stage == MESA_SHADER_VERTEX) { si_dump_shader_key_vs(key, &key->ge.part.gs.vs_prolog, "part.gs.vs_prolog", f); } @@ -1601,7 +1601,7 @@ struct nir_shader *si_get_nir_shader(struct si_shader_selector *sel, /* Loop unrolling caused by uniform inlining can help eliminate indirect indexing, so * this should be done after that. */ - progress2 |= ac_nir_lower_indirect_derefs(nir, sel->screen->info.chip_class); + progress2 |= ac_nir_lower_indirect_derefs(nir, sel->screen->info.gfx_level); if (progress2) si_nir_opts(sel->screen, nir, false); @@ -1825,7 +1825,7 @@ bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compi } /* Add the scratch offset to input SGPRs. */ - if (sel->screen->info.chip_class < GFX11 && + if (sel->screen->info.gfx_level < GFX11 && shader->config.scratch_bytes_per_wave && !si_is_merged_shader(shader)) shader->info.num_input_sgprs += 1; /* scratch byte offset */ @@ -1987,7 +1987,7 @@ void si_get_tcs_epilog_key(struct si_shader *shader, union si_shader_part_key *k static bool si_shader_select_tcs_parts(struct si_screen *sscreen, struct ac_llvm_compiler *compiler, struct si_shader *shader, struct util_debug_callback *debug) { - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { struct si_shader *ls_main_part = shader->key.ge.part.tcs.ls->main_shader_part_ls; if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part, @@ -2013,7 +2013,7 @@ static bool si_shader_select_tcs_parts(struct si_screen *sscreen, struct ac_llvm static bool si_shader_select_gs_parts(struct si_screen *sscreen, struct ac_llvm_compiler *compiler, struct si_shader *shader, struct util_debug_callback *debug) { - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { struct si_shader *es_main_part; if (shader->key.ge.as_ngg) @@ -2445,7 +2445,7 @@ bool si_create_shader_variant(struct si_screen *sscreen, struct ac_llvm_compiler fprintf(stderr, "Failed to compute subgroup info\n"); return false; } - } else if (sscreen->info.chip_class >= GFX9 && sel->stage == MESA_SHADER_GEOMETRY) { + } else if (sscreen->info.gfx_level >= GFX9 && sel->stage == MESA_SHADER_GEOMETRY) { gfx9_get_gs_info(shader->previous_stage_sel, sel, &shader->gs_info); } diff --git a/src/gallium/drivers/radeonsi/si_shader_info.c b/src/gallium/drivers/radeonsi/si_shader_info.c index b6eb7574ef3..497b090a175 100644 --- a/src/gallium/drivers/radeonsi/si_shader_info.c +++ b/src/gallium/drivers/radeonsi/si_shader_info.c @@ -773,7 +773,7 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir, if (nir->info.stage == MESA_SHADER_VERTEX) { info->num_vs_inputs = nir->info.stage == MESA_SHADER_VERTEX && !info->base.vs.blit_sgprs_amd ? info->num_inputs : 0; - unsigned num_vbos_in_sgprs = si_num_vbos_in_user_sgprs_inline(sscreen->info.chip_class); + unsigned num_vbos_in_sgprs = si_num_vbos_in_user_sgprs_inline(sscreen->info.gfx_level); info->num_vbos_in_user_sgprs = MIN2(info->num_vs_inputs, num_vbos_in_sgprs); /* The prolog is a no-op if there are no inputs. */ @@ -795,7 +795,7 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir, /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank * conflicts, i.e. each vertex will start at a different bank. */ - if (sscreen->info.chip_class >= GFX9) + if (sscreen->info.gfx_level >= GFX9) info->esgs_itemsize += 4; assert(((info->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0); diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c index f9d6cb980a3..7229abf78b7 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c @@ -132,7 +132,7 @@ void si_llvm_context_init(struct si_shader_context *ctx, struct si_screen *sscre ctx->screen = sscreen; ctx->compiler = compiler; - ac_llvm_context_init(&ctx->ac, compiler, sscreen->info.chip_class, sscreen->info.family, + ac_llvm_context_init(&ctx->ac, compiler, sscreen->info.gfx_level, sscreen->info.family, &sscreen->info, AC_FLOAT_MODE_DEFAULT_OPENGL, wave_size, 64); } @@ -150,7 +150,7 @@ void si_llvm_create_func(struct si_shader_context *ctx, const char *name, LLVMTy gl_shader_stage real_stage = ctx->stage; /* LS is merged into HS (TCS), and ES is merged into GS. */ - if (ctx->screen->info.chip_class >= GFX9 && ctx->stage <= MESA_SHADER_GEOMETRY) { + if (ctx->screen->info.gfx_level >= GFX9 && ctx->stage <= MESA_SHADER_GEOMETRY) { if (ctx->shader->key.ge.as_ls) real_stage = MESA_SHADER_TESS_CTRL; else if (ctx->shader->key.ge.as_es || ctx->shader->key.ge.as_ngg) @@ -927,7 +927,7 @@ bool si_llvm_translate_nir(struct si_shader_context *ctx, struct si_shader *shad } /* For merged shaders (VS-TCS, VS-GS, TES-GS): */ - if (ctx->screen->info.chip_class >= GFX9 && si_is_merged_shader(shader)) { + if (ctx->screen->info.gfx_level >= GFX9 && si_is_merged_shader(shader)) { /* TES is special because it has only 1 shader part if NGG shader culling is disabled, * and therefore it doesn't use the wrapper function. */ @@ -950,7 +950,7 @@ bool si_llvm_translate_nir(struct si_shader_context *ctx, struct si_shader *shad if ((ctx->stage == MESA_SHADER_VERTEX || ctx->stage == MESA_SHADER_TESS_EVAL) && shader->key.ge.as_ngg && !shader->key.ge.as_es && !shader->key.ge.opt.ngg_culling) { /* GFX10 requires a barrier before gs_alloc_req due to a hw bug. */ - if (ctx->screen->info.chip_class == GFX10) + if (ctx->screen->info.gfx_level == GFX10) ac_build_s_barrier(&ctx->ac, ctx->stage); gfx10_ngg_build_sendmsg_gs_alloc_req(ctx); @@ -1033,7 +1033,7 @@ bool si_llvm_translate_nir(struct si_shader_context *ctx, struct si_shader *shad if (nir->info.stage == MESA_SHADER_GEOMETRY) { /* Unpack GS vertex offsets. */ for (unsigned i = 0; i < 6; i++) { - if (ctx->screen->info.chip_class >= GFX9) { + if (ctx->screen->info.gfx_level >= GFX9) { ctx->gs_vtx_offset[i] = si_unpack_param(ctx, ctx->args.gs_vtx_offset[i / 2], (i & 1) * 16, 16); } else { ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args.gs_vtx_offset[i]); @@ -1041,7 +1041,7 @@ bool si_llvm_translate_nir(struct si_shader_context *ctx, struct si_shader *shad } /* Apply the hw bug workaround for triangle strips with adjacency. */ - if (ctx->screen->info.chip_class <= GFX9 && + if (ctx->screen->info.gfx_level <= GFX9 && ctx->shader->key.ge.mono.u.gs_tri_strip_adj_fix) { LLVMValueRef prim_id = ac_get_arg(&ctx->ac, ctx->args.gs_prim_id); /* Remap GS vertex offsets for every other primitive. */ @@ -1136,7 +1136,7 @@ static bool si_should_optimize_less(struct ac_llvm_compiler *compiler, return false; /* Assume a slow CPU. */ - assert(!sel->screen->info.has_dedicated_vram && sel->screen->info.chip_class <= GFX8); + assert(!sel->screen->info.has_dedicated_vram && sel->screen->info.gfx_level <= GFX8); /* For a crazy dEQP test containing 2597 memory opcodes, mostly * buffer stores. */ @@ -1221,7 +1221,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler * si_build_wrapper_function(&ctx, parts, 3, 0, 0, false); } else if (shader->is_monolithic && sel->stage == MESA_SHADER_TESS_CTRL) { - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { struct si_shader_selector *ls = shader->key.ge.part.tcs.ls; LLVMValueRef parts[4]; bool vs_needs_prolog = @@ -1289,7 +1289,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler * si_build_wrapper_function(&ctx, parts, 2, 0, 0, false); } } else if (shader->is_monolithic && sel->stage == MESA_SHADER_GEOMETRY) { - if (ctx.screen->info.chip_class >= GFX9) { + if (ctx.screen->info.gfx_level >= GFX9) { struct si_shader_selector *es = shader->key.ge.part.gs.es; LLVMValueRef es_prolog = NULL; LLVMValueRef es_main = NULL; diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c b/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c index 19e09e481f4..c5396c2c936 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm_gs.c @@ -57,7 +57,7 @@ static LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi, unsigned in param = si_shader_io_get_unique_index(info->input[input_index].semantic, false); /* GFX9 has the ESGS ring in LDS. */ - if (ctx->screen->info.chip_class >= GFX9) { + if (ctx->screen->info.gfx_level >= GFX9) { unsigned offset = param * 4 + swizzle; vtx_offset = LLVMBuildAdd(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param], @@ -111,7 +111,7 @@ static void si_set_es_return_value_for_gs(struct si_shader_context *ctx) else ret = si_insert_input_ret(ctx, ret, ctx->args.gs2vs_offset, 2); ret = si_insert_input_ret(ctx, ret, ctx->args.merged_wave_info, 3); - if (ctx->screen->info.chip_class >= GFX11) + if (ctx->screen->info.gfx_level >= GFX11) ret = si_insert_input_ret(ctx, ret, ctx->args.gs_attr_offset, 5); else ret = si_insert_input_ret(ctx, ret, ctx->args.scratch_offset, 5); @@ -121,7 +121,7 @@ static void si_set_es_return_value_for_gs(struct si_shader_context *ctx) if (ctx->screen->use_ngg) { ret = si_insert_input_ptr(ctx, ret, ctx->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS); ret = si_insert_input_ptr(ctx, ret, ctx->small_prim_cull_info, 8 + GFX9_SGPR_SMALL_PRIM_CULL_INFO); - if (ctx->screen->info.chip_class >= GFX11) + if (ctx->screen->info.gfx_level >= GFX11) ret = si_insert_input_ptr(ctx, ret, ctx->gs_attr_address, 8 + GFX9_SGPR_ATTRIBUTE_RING_ADDR); } @@ -144,7 +144,7 @@ void si_llvm_es_build_end(struct si_shader_context *ctx) unsigned chan; int i; - if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) { + if (ctx->screen->info.gfx_level >= GFX9 && info->num_outputs) { unsigned itemsize_dw = es->selector->info.esgs_itemsize / 4; LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac); LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->args.merged_wave_info, 24, 4); @@ -174,7 +174,7 @@ void si_llvm_es_build_end(struct si_shader_context *ctx) out_val = ac_to_integer(&ctx->ac, out_val); /* GFX9 has the ESGS ring in LDS. */ - if (ctx->screen->info.chip_class >= GFX9) { + if (ctx->screen->info.gfx_level >= GFX9) { LLVMValueRef idx = LLVMConstInt(ctx->ac.i32, param * 4 + chan, false); idx = LLVMBuildAdd(ctx->ac.builder, lds_base, idx, ""); ac_build_indexed_store(&ctx->ac, ctx->esgs_ring, idx, out_val); @@ -188,13 +188,13 @@ void si_llvm_es_build_end(struct si_shader_context *ctx) } } - if (ctx->screen->info.chip_class >= GFX9) + if (ctx->screen->info.gfx_level >= GFX9) si_set_es_return_value_for_gs(ctx); } static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx) { - if (ctx->screen->info.chip_class >= GFX9) + if (ctx->screen->info.gfx_level >= GFX9) return si_unpack_param(ctx, ctx->args.merged_wave_info, 16, 8); else return ac_get_arg(&ctx->ac, ctx->args.gs_wave_id); @@ -214,7 +214,7 @@ void si_llvm_gs_build_end(struct si_shader_context *ctx) assert(info->num_outputs <= AC_LLVM_MAX_OUTPUTS); - if (ctx->screen->info.chip_class >= GFX10) + if (ctx->screen->info.gfx_level >= GFX10) ac_build_waitcnt(&ctx->ac, AC_WAIT_VSTORE); if (ctx->screen->use_ngg) { @@ -265,7 +265,7 @@ void si_llvm_gs_build_end(struct si_shader_context *ctx) ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, si_get_gs_wave_id(ctx)); - if (ctx->screen->info.chip_class >= GFX9) + if (ctx->screen->info.gfx_level >= GFX9) ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label); } @@ -366,7 +366,7 @@ void si_preload_esgs_ring(struct si_shader_context *ctx) { LLVMBuilderRef builder = ctx->ac.builder; - if (ctx->screen->info.chip_class <= GFX8) { + if (ctx->screen->info.gfx_level <= GFX8) { LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, SI_RING_ESGS, 0); LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->internal_bindings); @@ -384,7 +384,7 @@ void si_preload_esgs_ring(struct si_shader_context *ctx) S_008F0C_ADD_TID_ENABLE(1), 0), ""); /* If MUBUF && ADD_TID_ENABLE, DATA_FORMAT means STRIDE[14:17] on gfx8-9, so set 0. */ - if (ctx->screen->info.chip_class == GFX8) { + if (ctx->screen->info.gfx_level == GFX8) { desc3 = LLVMBuildAnd(builder, desc3, LLVMConstInt(ctx->ac.i32, C_008F0C_DATA_FORMAT, 0), ""); } @@ -406,7 +406,7 @@ void si_preload_esgs_ring(struct si_shader_context *ctx) void si_preload_gs_rings(struct si_shader_context *ctx) { - if (ctx->ac.chip_class >= GFX11) + if (ctx->ac.gfx_level >= GFX11) return; const struct si_shader_selector *sel = ctx->shader->selector; @@ -464,12 +464,12 @@ void si_preload_gs_rings(struct si_shader_context *ctx) S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */ S_008F0C_ADD_TID_ENABLE(1); - if (ctx->ac.chip_class >= GFX10) { + if (ctx->ac.gfx_level >= GFX10) { rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1); } else { /* If MUBUF && ADD_TID_ENABLE, DATA_FORMAT means STRIDE[14:17] on gfx8-9, so set 0. */ - unsigned data_format = ctx->ac.chip_class == GFX8 || ctx->ac.chip_class == GFX9 ? + unsigned data_format = ctx->ac.gfx_level == GFX8 || ctx->ac.gfx_level == GFX9 ? 0 : V_008F0C_BUF_DATA_FORMAT_32; rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_ps.c b/src/gallium/drivers/radeonsi/si_shader_llvm_ps.c index 79a32a2774f..a3f4c7fd184 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm_ps.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm_ps.c @@ -85,7 +85,7 @@ static LLVMValueRef si_nir_emit_fbfetch(struct ac_shader_abi *abi) if (ctx->shader->key.ps.mono.fbfetch_msaa) args.coords[chan++] = si_get_sample_id(ctx); - if (ctx->screen->info.chip_class < GFX11 && + if (ctx->screen->info.gfx_level < GFX11 && ctx->shader->key.ps.mono.fbfetch_msaa && !(ctx->screen->debug_flags & DBG(NO_FMASK))) { fmask = ac_build_load_to_sgpr(&ctx->ac, ptr, @@ -296,7 +296,7 @@ static bool si_llvm_init_ps_export_args(struct si_shader_context *ctx, LLVMValue if (key->ps.part.epilog.dual_src_blend_swizzle && (compacted_mrt_index == 0 || compacted_mrt_index == 1)) { - assert(ctx->ac.chip_class >= GFX11); + assert(ctx->ac.gfx_level >= GFX11); args->target += 21; } @@ -323,7 +323,7 @@ static bool si_llvm_init_ps_export_args(struct si_shader_context *ctx, LLVMValue break; case V_028714_SPI_SHADER_32_AR: - if (ctx->screen->info.chip_class >= GFX10) { + if (ctx->screen->info.gfx_level >= GFX10) { args->enabled_channels = 0x3; /* writemask */ args->out[0] = get_color_32bit(ctx, color_type, values[0]); args->out[1] = get_color_32bit(ctx, color_type, values[3]); @@ -397,7 +397,7 @@ static bool si_llvm_init_ps_export_args(struct si_shader_context *ctx, LLVMValue } } if (packf || packi) { - if (ctx->screen->info.chip_class >= GFX11) + if (ctx->screen->info.gfx_level >= GFX11) args->enabled_channels = 0x3; else args->compr = 1; /* COMPR flag */ @@ -937,7 +937,7 @@ void si_llvm_build_ps_epilog(struct si_shader_context *ctx, union si_shader_part exp.args[exp.num - 1].done = 1; /* DONE bit */ if (key->ps_epilog.states.dual_src_blend_swizzle) { - assert(ctx->ac.chip_class >= GFX11); + assert(ctx->ac.gfx_level >= GFX11); assert((key->ps_epilog.colors_written & 0x3) == 0x3); ac_build_dual_src_blend_swizzle(&ctx->ac, &exp.args[first_color_export], &exp.args[first_color_export + 1]); diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_resources.c b/src/gallium/drivers/radeonsi/si_shader_llvm_resources.c index bb857d79dd6..5a0ab62250a 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm_resources.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm_resources.c @@ -72,10 +72,10 @@ static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *c uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (ctx->screen->info.chip_class >= GFX11) + if (ctx->screen->info.gfx_level >= GFX11) rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); - else if (ctx->screen->info.chip_class >= GFX10) + else if (ctx->screen->info.gfx_level >= GFX10) rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); else @@ -138,7 +138,7 @@ static LLVMValueRef load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, boo */ static LLVMValueRef force_dcc_off(struct si_shader_context *ctx, LLVMValueRef rsrc) { - if (ctx->screen->info.chip_class <= GFX7) { + if (ctx->screen->info.gfx_level <= GFX7) { return rsrc; } else { LLVMValueRef i32_6 = LLVMConstInt(ctx->ac.i32, 6, 0); @@ -165,7 +165,7 @@ static LLVMValueRef force_write_compress_off(struct si_shader_context *ctx, LLVM static LLVMValueRef fixup_image_desc(struct si_shader_context *ctx, LLVMValueRef rsrc, bool uses_store) { - if (uses_store && ctx->ac.chip_class <= GFX9) + if (uses_store && ctx->ac.gfx_level <= GFX9) rsrc = force_dcc_off(ctx, rsrc); if (!uses_store && ctx->screen->info.has_image_load_dcc_bug && @@ -222,7 +222,7 @@ static LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx, LLVMValu break; case AC_DESC_FMASK: /* The FMASK is at [8:15]. */ - assert(ctx->screen->info.chip_class < GFX11); + assert(ctx->screen->info.gfx_level < GFX11); index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->ac.i32, 2, 0), ctx->ac.i32_1); break; case AC_DESC_SAMPLER: diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c index 925b9e156a0..df228eed990 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c @@ -159,7 +159,7 @@ static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx) return LLVMConstInt(ctx->ac.i32, stride, 0); case MESA_SHADER_TESS_CTRL: - if (ctx->screen->info.chip_class >= GFX9 && ctx->shader->is_monolithic) { + if (ctx->screen->info.gfx_level >= GFX9 && ctx->shader->is_monolithic) { stride = ctx->shader->key.ge.part.tcs.ls->info.lshs_vertex_stride / 4; return LLVMConstInt(ctx->ac.i32, stride, 0); } @@ -357,10 +357,10 @@ static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx, enum uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (ctx->screen->info.chip_class >= GFX11) + if (ctx->screen->info.gfx_level >= GFX11) rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW); - else if (ctx->screen->info.chip_class >= GFX10) + else if (ctx->screen->info.gfx_level >= GFX10) rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1); else @@ -706,7 +706,7 @@ static void si_write_tess_factors(struct si_shader_context *ctx, union si_shader offset = 0; /* Store the dynamic HS control word. */ - if (ctx->screen->info.chip_class <= GFX8) { + if (ctx->screen->info.gfx_level <= GFX8) { ac_build_ifcc(&ctx->ac, LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, rel_patch_id, ctx->ac.i32_0, ""), 6504); ac_build_buffer_store_dword(&ctx->ac, buffer, LLVMConstInt(ctx->ac.i32, 0x80000000, 0), @@ -770,7 +770,7 @@ void si_llvm_tcs_build_end(struct si_shader_context *ctx) invocation_id = si_unpack_param(ctx, ctx->args.tcs_rel_ids, 8, 5); tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx); - if (ctx->screen->info.chip_class >= GFX9 && !ctx->shader->is_monolithic) { + if (ctx->screen->info.gfx_level >= GFX9 && !ctx->shader->is_monolithic) { LLVMBasicBlockRef blocks[2] = {LLVMGetInsertBlock(builder), ctx->merged_wrap_if_entry_block}; LLVMValueRef values[2]; @@ -793,7 +793,7 @@ void si_llvm_tcs_build_end(struct si_shader_context *ctx) LLVMValueRef ret = ctx->return_value; unsigned vgpr; - if (ctx->screen->info.chip_class >= GFX9) { + if (ctx->screen->info.gfx_level >= GFX9) { ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_layout, 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT); ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_layout, 8 + GFX9_SGPR_TCS_OUT_LAYOUT); @@ -850,7 +850,7 @@ static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx) ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); ret = si_insert_input_ret(ctx, ret, ctx->args.merged_wave_info, 3); ret = si_insert_input_ret(ctx, ret, ctx->args.tcs_factor_offset, 4); - if (ctx->screen->info.chip_class <= GFX10_3) + if (ctx->screen->info.gfx_level <= GFX10_3) ret = si_insert_input_ret(ctx, ret, ctx->args.scratch_offset, 5); ret = si_insert_input_ptr(ctx, ret, ctx->internal_bindings, 8 + SI_SGPR_INTERNAL_BINDINGS); @@ -879,7 +879,7 @@ void si_llvm_ls_build_end(struct si_shader_context *ctx) struct si_shader_info *info = &shader->selector->info; unsigned i, chan; LLVMValueRef vertex_id; - if (ctx->screen->info.chip_class >= GFX11) { + if (ctx->screen->info.gfx_level >= GFX11) { vertex_id = ac_build_imad(&ctx->ac, si_unpack_param(ctx, ctx->args.tcs_wave_id, 0, 5), LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, 0), ac_get_thread_id(&ctx->ac)); @@ -935,7 +935,7 @@ void si_llvm_ls_build_end(struct si_shader_context *ctx) } } - if (ctx->screen->info.chip_class >= GFX9) + if (ctx->screen->info.gfx_level >= GFX9) si_set_ls_return_value_for_tcs(ctx); } @@ -947,7 +947,7 @@ void si_llvm_build_tcs_epilog(struct si_shader_context *ctx, union si_shader_par { memset(&ctx->args, 0, sizeof(ctx->args)); - if (ctx->screen->info.chip_class >= GFX9) { + if (ctx->screen->info.gfx_level >= GFX9) { ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); @@ -995,7 +995,7 @@ void si_llvm_build_tcs_epilog(struct si_shader_context *ctx, union si_shader_par ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &tess_factors[i]); /* Create the function. */ - si_llvm_create_func(ctx, "tcs_epilog", NULL, 0, ctx->screen->info.chip_class >= GFX7 ? 128 : 0); + si_llvm_create_func(ctx, "tcs_epilog", NULL, 0, ctx->screen->info.gfx_level >= GFX7 ? 128 : 0); ac_declare_lds_as_pointer(&ctx->ac); LLVMValueRef invoc0_tess_factors[6]; diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c b/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c index 103fb64356a..bae47468d1c 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c @@ -602,7 +602,7 @@ void si_llvm_build_vs_exports(struct si_shader_context *ctx, if (writes_vrs) { LLVMValueRef rates; - if (ctx->screen->info.chip_class >= GFX11) { + if (ctx->screen->info.gfx_level >= GFX11) { /* Bits [2:5] = VRS rate * * The range is [0, 15]. @@ -637,7 +637,7 @@ void si_llvm_build_vs_exports(struct si_shader_context *ctx, pos_args[1].out[1] = ac_to_float(&ctx->ac, v); } - if (ctx->screen->info.chip_class >= GFX9) { + if (ctx->screen->info.gfx_level >= GFX9) { /* GFX9 has the layer in out.z[10:0] and the viewport * index in out.z[19:16]. */ @@ -671,7 +671,7 @@ void si_llvm_build_vs_exports(struct si_shader_context *ctx, /* GFX10 (Navi1x) skip POS0 exports if EXEC=0 and DONE=0, causing a hang. * Setting valid_mask=1 prevents it and has no other effect. */ - if (ctx->screen->info.chip_class == GFX10) + if (ctx->screen->info.gfx_level == GFX10) pos_args[0].valid_mask = 1; pos_idx = 0; @@ -692,7 +692,7 @@ void si_llvm_build_vs_exports(struct si_shader_context *ctx, * * VLOAD is for atomics with return. */ - if (ctx->screen->info.chip_class >= GFX10 && + if (ctx->screen->info.gfx_level >= GFX10 && !shader->info.nr_param_exports && shader->selector->info.base.writes_memory) ac_build_waitcnt(&ctx->ac, AC_WAIT_VLOAD | AC_WAIT_VSTORE); @@ -721,7 +721,7 @@ void si_llvm_build_vs_exports(struct si_shader_context *ctx, ¶m_exports[offset]); } - if (ctx->screen->info.chip_class >= GFX11) { + if (ctx->screen->info.gfx_level >= GFX11) { /* Get the attribute ring address and descriptor. */ LLVMValueRef attr_address; if (ctx->stage == MESA_SHADER_VERTEX && shader->selector->info.base.vs.blit_sgprs_amd) { @@ -910,7 +910,7 @@ void si_llvm_build_vs_prolog(struct si_shader_context *ctx, union si_shader_part } unsigned vertex_id_vgpr = first_vs_vgpr; - unsigned instance_id_vgpr = ctx->screen->info.chip_class >= GFX10 + unsigned instance_id_vgpr = ctx->screen->info.gfx_level >= GFX10 ? first_vs_vgpr + 3 : first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1); diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c index 10815770d9b..d3bbc864b6e 100644 --- a/src/gallium/drivers/radeonsi/si_shader_nir.c +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c @@ -160,7 +160,7 @@ static void si_late_optimize_16bit_samplers(struct si_screen *sscreen, nir_shade * based on those two. */ /* TODO: The constraints can't represent the ddx constraint. */ - /*bool has_g16 = sscreen->info.chip_class >= GFX10 && LLVM_VERSION_MAJOR >= 12;*/ + /*bool has_g16 = sscreen->info.gfx_level >= GFX10 && LLVM_VERSION_MAJOR >= 12;*/ bool has_g16 = false; nir_tex_src_type_constraints tex_constraints = { [nir_tex_src_comparator] = {true, 32}, diff --git a/src/gallium/drivers/radeonsi/si_sqtt.c b/src/gallium/drivers/radeonsi/si_sqtt.c index de5cf86923f..5e4e03c2bfa 100644 --- a/src/gallium/drivers/radeonsi/si_sqtt.c +++ b/src/gallium/drivers/radeonsi/si_sqtt.c @@ -103,7 +103,7 @@ si_emit_thread_trace_start(struct si_context* sctx, /* Select the first active CUs */ int first_active_cu = ffs(sctx->screen->info.cu_mask[se][0]); - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { /* Order seems important for the following 2 registers. */ radeon_set_privileged_config_reg(R_008D04_SQ_THREAD_TRACE_BUF0_SIZE, S_008D04_SIZE(shifted_size) | @@ -139,7 +139,7 @@ si_emit_thread_trace_start(struct si_context* sctx, S_008D1C_SQ_STALL_EN(1) | S_008D1C_REG_DROP_ON_STALL(0) | S_008D1C_LOWATER_OFFSET( - sctx->chip_class >= GFX10_3 ? 4 : 0) | + sctx->gfx_level >= GFX10_3 ? 4 : 0) | S_008D1C_AUTO_FLUSH_MODE(sctx->screen->info.has_sqtt_auto_flush_mode_bug)); } else { /* Order seems important for the following 4 registers. */ @@ -181,7 +181,7 @@ si_emit_thread_trace_start(struct si_context* sctx, radeon_set_uconfig_reg(R_030CEC_SQ_THREAD_TRACE_HIWATER, S_030CEC_HIWATER(4)); - if (sctx->chip_class == GFX9) { + if (sctx->gfx_level == GFX9) { /* Reset thread trace status errors. */ radeon_set_uconfig_reg(R_030CE8_SQ_THREAD_TRACE_STATUS, S_030CE8_UTC_ERROR(0)); @@ -199,7 +199,7 @@ si_emit_thread_trace_start(struct si_context* sctx, S_030CD8_AUTOFLUSH_EN(1) | /* periodically flush SQTT data to memory */ S_030CD8_MODE(1); - if (sctx->chip_class == GFX9) { + if (sctx->gfx_level == GFX9) { /* Count SQTT traffic in TCC perf counters. */ thread_trace_mode |= S_030CD8_TC_PERF_EN(1); } @@ -247,7 +247,7 @@ si_copy_thread_trace_info_regs(struct si_context* sctx, { const uint32_t *thread_trace_info_regs = NULL; - switch (sctx->chip_class) { + switch (sctx->gfx_level) { case GFX10_3: case GFX10: thread_trace_info_regs = gfx10_thread_trace_info_regs; @@ -256,7 +256,7 @@ si_copy_thread_trace_info_regs(struct si_context* sctx, thread_trace_info_regs = gfx9_thread_trace_info_regs; break; default: - unreachable("Unsupported chip_class"); + unreachable("Unsupported gfx_level"); } /* Get the VA where the info struct is stored for this SE. */ @@ -323,7 +323,7 @@ si_emit_thread_trace_stop(struct si_context *sctx, S_030800_SH_INDEX(0) | S_030800_INSTANCE_BROADCAST_WRITES(1)); - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { if (!sctx->screen->info.has_sqtt_rb_harvest_bug) { /* Make sure to wait for the trace buffer. */ radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, 0)); @@ -577,7 +577,7 @@ si_get_thread_trace(struct si_context *sctx, /* For GFX10+ compute_unit really means WGP */ thread_trace_se.compute_unit = - sctx->screen->info.chip_class >= GFX10 ? (first_active_cu / 2) : first_active_cu; + sctx->screen->info.gfx_level >= GFX10 ? (first_active_cu / 2) : first_active_cu; thread_trace->traces[se] = thread_trace_se; } @@ -600,14 +600,14 @@ si_init_thread_trace(struct si_context *sctx) sctx->thread_trace = CALLOC_STRUCT(ac_thread_trace_data); - if (sctx->chip_class < GFX8) { + if (sctx->gfx_level < GFX8) { fprintf(stderr, "GPU hardware not supported: refer to " "the RGP documentation for the list of " "supported GPUs!\n"); return false; } - if (sctx->chip_class > GFX10_3) { + if (sctx->gfx_level > GFX10_3) { fprintf(stderr, "radeonsi: Thread trace is not supported " "for that GPU!\n"); return false; @@ -639,7 +639,7 @@ si_init_thread_trace(struct si_context *sctx) list_inithead(&sctx->thread_trace->rgp_code_object.record); simple_mtx_init(&sctx->thread_trace->rgp_code_object.lock, mtx_plain); - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { /* Limit SPM counters to GFX10+ for now */ ASSERTED bool r = si_spm_init(sctx); assert(r); @@ -700,7 +700,7 @@ si_destroy_thread_trace(struct si_context *sctx) free(sctx->thread_trace); sctx->thread_trace = NULL; - if (sctx->chip_class >= GFX10) + if (sctx->gfx_level >= GFX10) si_spm_finish(sctx); } @@ -753,7 +753,7 @@ si_handle_thread_trace(struct si_context *sctx, struct radeon_cmdbuf *rcs) if (sctx->ws->fence_wait(sctx->ws, sctx->last_sqtt_fence, PIPE_TIMEOUT_INFINITE) && si_get_thread_trace(sctx, &thread_trace)) { /* Map the SPM counter buffer */ - if (sctx->chip_class >= GFX10) + if (sctx->gfx_level >= GFX10) sctx->spm_trace.ptr = sctx->ws->buffer_map(sctx->ws, sctx->spm_trace.bo, NULL, PIPE_MAP_READ | RADEON_MAP_TEMPORARY); @@ -784,7 +784,7 @@ si_emit_thread_trace_userdata(struct si_context* sctx, /* Without the perfctr bit the CP might not always pass the * write on correctly. */ - radeon_set_uconfig_reg_seq(R_030D08_SQ_THREAD_TRACE_USERDATA_2, count, sctx->chip_class >= GFX10); + radeon_set_uconfig_reg_seq(R_030D08_SQ_THREAD_TRACE_USERDATA_2, count, sctx->gfx_level >= GFX10); radeon_emit_array(dwords, count); @@ -800,13 +800,13 @@ si_emit_spi_config_cntl(struct si_context* sctx, { radeon_begin(cs); - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { uint32_t spi_config_cntl = S_031100_GPR_WRITE_PRIORITY(0x2c688) | S_031100_EXP_PRIORITY_ORDER(3) | S_031100_ENABLE_SQG_TOP_EVENTS(enable) | S_031100_ENABLE_SQG_BOP_EVENTS(enable); - if (sctx->chip_class >= GFX10) + if (sctx->gfx_level >= GFX10) spi_config_cntl |= S_031100_PS_PKR_PRIORITY_CNTL(3); radeon_set_uconfig_reg(R_031100_SPI_CONFIG_CNTL, spi_config_cntl); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index d28a4010fbf..69d3cd859b2 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -103,7 +103,7 @@ static void si_emit_cb_render_state(struct si_context *sctx) radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK, cb_target_mask); - if (sctx->chip_class >= GFX8) { + if (sctx->gfx_level >= GFX8) { /* DCC MSAA workaround. * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_- * COMBINER_DISABLE, but that would be more complicated. @@ -112,17 +112,17 @@ static void si_emit_cb_render_state(struct si_context *sctx) blend->dcc_msaa_corruption_4bit & cb_target_mask && sctx->framebuffer.nr_samples >= 2; unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark; - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { radeon_opt_set_context_reg(sctx, R_028424_CB_FDCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL, S_028424_SAMPLE_MASK_TRACKER_DISABLE(oc_disable) | S_028424_SAMPLE_MASK_TRACKER_WATERMARK(watermark)); } else { radeon_opt_set_context_reg( sctx, R_028424_CB_DCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL, - S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) | + S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->gfx_level <= GFX9) | S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) | S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) | - S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->chip_class < GFX11 && + S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->gfx_level < GFX11 && sctx->screen->info.has_dcc_constant_encode)); } } @@ -151,14 +151,14 @@ static void si_emit_cb_render_state(struct si_context *sctx) continue; } - format = sctx->chip_class >= GFX11 ? G_028C70_FORMAT_GFX11(surf->cb_color_info): + format = sctx->gfx_level >= GFX11 ? G_028C70_FORMAT_GFX11(surf->cb_color_info): G_028C70_FORMAT_GFX6(surf->cb_color_info); swap = G_028C70_COMP_SWAP(surf->cb_color_info); spi_format = (spi_shader_col_format >> (i * 4)) & 0xf; colormask = (cb_target_mask >> (i * 4)) & 0xf; /* Set if RGB and A are present. */ - has_alpha = !(sctx->chip_class >= GFX11 ? G_028C74_FORCE_DST_ALPHA_1_GFX11(surf->cb_color_attrib): + has_alpha = !(sctx->gfx_level >= GFX11 ? G_028C74_FORCE_DST_ALPHA_1_GFX11(surf->cb_color_attrib): G_028C74_FORCE_DST_ALPHA_1_GFX6(surf->cb_color_attrib)); if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_16 || @@ -298,7 +298,7 @@ static uint32_t si_translate_blend_function(int blend_func) return 0; } -static uint32_t si_translate_blend_factor(enum chip_class chip_class, int blend_fact) +static uint32_t si_translate_blend_factor(enum amd_gfx_level gfx_level, int blend_fact) { switch (blend_fact) { case PIPE_BLENDFACTOR_ONE: @@ -314,10 +314,10 @@ static uint32_t si_translate_blend_factor(enum chip_class chip_class, int blend_ case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: return V_028780_BLEND_SRC_ALPHA_SATURATE; case PIPE_BLENDFACTOR_CONST_COLOR: - return chip_class >= GFX11 ? V_028780_BLEND_CONSTANT_COLOR_GFX11: + return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_COLOR_GFX11: V_028780_BLEND_CONSTANT_COLOR_GFX6; case PIPE_BLENDFACTOR_CONST_ALPHA: - return chip_class >= GFX11 ? V_028780_BLEND_CONSTANT_ALPHA_GFX11 : + return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_ALPHA_GFX11 : V_028780_BLEND_CONSTANT_ALPHA_GFX6; case PIPE_BLENDFACTOR_ZERO: return V_028780_BLEND_ZERO; @@ -330,22 +330,22 @@ static uint32_t si_translate_blend_factor(enum chip_class chip_class, int blend_ case PIPE_BLENDFACTOR_INV_DST_COLOR: return V_028780_BLEND_ONE_MINUS_DST_COLOR; case PIPE_BLENDFACTOR_INV_CONST_COLOR: - return chip_class >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX11: + return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX11: V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX6; case PIPE_BLENDFACTOR_INV_CONST_ALPHA: - return chip_class >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX11: + return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX11: V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX6; case PIPE_BLENDFACTOR_SRC1_COLOR: - return chip_class >= GFX11 ? V_028780_BLEND_SRC1_COLOR_GFX11: + return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_COLOR_GFX11: V_028780_BLEND_SRC1_COLOR_GFX6; case PIPE_BLENDFACTOR_SRC1_ALPHA: - return chip_class >= GFX11 ? V_028780_BLEND_SRC1_ALPHA_GFX11: + return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_ALPHA_GFX11: V_028780_BLEND_SRC1_ALPHA_GFX6; case PIPE_BLENDFACTOR_INV_SRC1_COLOR: - return chip_class >= GFX11 ? V_028780_BLEND_INV_SRC1_COLOR_GFX11: + return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_COLOR_GFX11: V_028780_BLEND_INV_SRC1_COLOR_GFX6; case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: - return chip_class >= GFX11 ? V_028780_BLEND_INV_SRC1_ALPHA_GFX11: + return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_ALPHA_GFX11: V_028780_BLEND_INV_SRC1_ALPHA_GFX6; default: PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact); @@ -515,7 +515,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx, /* Only set dual source blending for MRT0 to avoid a hang. */ if (i >= 1 && blend->dual_src_blend) { if (i == 1) { - if (sctx->chip_class >= GFX11) + if (sctx->gfx_level >= GFX11) blend_cntl = last_blend_cntl; else blend_cntl = S_028780_ENABLE(1); @@ -588,21 +588,21 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx, /* Set blend state. */ blend_cntl |= S_028780_ENABLE(1); blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); - blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(sctx->chip_class, srcRGB)); - blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(sctx->chip_class, dstRGB)); + blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(sctx->gfx_level, srcRGB)); + blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(sctx->gfx_level, dstRGB)); if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); - blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(sctx->chip_class, srcA)); - blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(sctx->chip_class, dstA)); + blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(sctx->gfx_level, srcA)); + blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(sctx->gfx_level, dstA)); } si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); last_blend_cntl = blend_cntl; blend->blend_enable_4bit |= 0xfu << (i * 4); - if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10) + if (sctx->gfx_level >= GFX8 && sctx->gfx_level <= GFX10) blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4); /* This is only important for formats without alpha. */ @@ -613,7 +613,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx, blend->need_src_alpha_4bit |= 0xfu << (i * 4); } - if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10 && logicop_enable) + if (sctx->gfx_level >= GFX8 && sctx->gfx_level <= GFX10 && logicop_enable) blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit; if (blend->cb_target_mask) { @@ -638,7 +638,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx, /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */ if (blend->dual_src_blend || logicop_enable || mode == V_028808_CB_RESOLVE || - (sctx->chip_class == GFX11 && blend->blend_enable_4bit)) + (sctx->gfx_level == GFX11 && blend->blend_enable_4bit)) color_control |= S_028808_DISABLE_DUAL_QUAD(1); } @@ -861,9 +861,9 @@ static void si_emit_clip_regs(struct si_context *sctx) clipdist_mask &= rs->clip_plane_enable; culldist_mask |= clipdist_mask; - unsigned pa_cl_cntl = S_02881C_BYPASS_VTX_RATE_COMBINER(sctx->chip_class >= GFX10_3 && + unsigned pa_cl_cntl = S_02881C_BYPASS_VTX_RATE_COMBINER(sctx->gfx_level >= GFX10_3 && !sctx->screen->options.vrs2x2) | - S_02881C_BYPASS_PRIM_RATE_COMBINER(sctx->chip_class >= GFX10_3) | + S_02881C_BYPASS_PRIM_RATE_COMBINER(sctx->gfx_level >= GFX10_3) | clipdist_mask | (culldist_mask << 8); radeon_begin(&sctx->gfx_cs); @@ -1043,7 +1043,7 @@ static void *si_create_rs_state(struct pipe_context *ctx, const struct pipe_rast S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | S_028A48_MSAA_ENABLE(state->multisample || state->poly_smooth || state->line_smooth) | S_028A48_VPORT_SCISSOR_ENABLE(1) | - S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9)); + S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.gfx_level >= GFX9)); bool polygon_mode_enabled = (state->fill_front != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_FRONT)) || @@ -1061,7 +1061,7 @@ static void *si_create_rs_state(struct pipe_context *ctx, const struct pipe_rast S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)) | /* this must be set if POLY_MODE or PERPENDICULAR_ENDCAP_ENA is set */ - S_028814_KEEP_TOGETHER_ENABLE(sscreen->info.chip_class >= GFX10 ? + S_028814_KEEP_TOGETHER_ENABLE(sscreen->info.gfx_level >= GFX10 ? polygon_mode_enabled || rs->perpendicular_end_caps : 0)); @@ -1512,7 +1512,7 @@ static void si_emit_db_render_state(struct si_context *sctx) S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear); } - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { unsigned max_allowed_tiles_in_wave = 0; if (sctx->screen->info.has_dedicated_vram) { @@ -1540,9 +1540,9 @@ static void si_emit_db_render_state(struct si_context *sctx) /* DB_COUNT_CONTROL (occlusion queries) */ if (sctx->num_occlusion_queries > 0 && !sctx->occlusion_queries_disabled) { bool perfect = sctx->num_perfect_occlusion_queries > 0; - bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect; + bool gfx10_perfect = sctx->gfx_level >= GFX10 && perfect; - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { unsigned log_sample_rate = sctx->framebuffer.log_samples; db_count_control = S_028004_PERFECT_ZPASS_COUNTS(perfect) | @@ -1555,7 +1555,7 @@ static void si_emit_db_render_state(struct si_context *sctx) } } else { /* Disable occlusion queries. */ - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { db_count_control = 0; } else { db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1); @@ -1572,12 +1572,12 @@ static void si_emit_db_render_state(struct si_context *sctx) S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) | S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) | S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) | - S_028010_CENTROID_COMPUTATION_MODE(sctx->chip_class >= GFX10_3 ? 1 : 0)); + S_028010_CENTROID_COMPUTATION_MODE(sctx->gfx_level >= GFX10_3 ? 1 : 0)); db_shader_control = sctx->ps_db_shader_control; /* Bug workaround for smoothing (overrasterization) on GFX6. */ - if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) { + if (sctx->gfx_level == GFX6 && sctx->smoothing_enabled) { db_shader_control &= C_02880C_Z_ORDER; db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z); } @@ -1592,9 +1592,9 @@ static void si_emit_db_render_state(struct si_context *sctx) radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL, db_shader_control); - if (sctx->chip_class >= GFX10_3) { + if (sctx->gfx_level >= GFX10_3) { if (sctx->allow_flat_shading) { - if (sctx->chip_class == GFX11) { + if (sctx->gfx_level == GFX11) { radeon_opt_set_context_reg(sctx, R_0283D0_PA_SC_VRS_OVERRIDE_CNTL, SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, S_0283D0_VRS_OVERRIDE_RATE_COMBINER_MODE( @@ -1616,7 +1616,7 @@ static void si_emit_db_render_state(struct si_context *sctx) * * MIN allows sample shading but not coarse shading. */ - if (sctx->chip_class == GFX11) { + if (sctx->gfx_level == GFX11) { unsigned mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ? V_0283D0_SC_VRS_COMB_MODE_MIN : V_0283D0_SC_VRS_COMB_MODE_PASSTHRU; @@ -1642,7 +1642,7 @@ static void si_emit_db_render_state(struct si_context *sctx) /* * format translation */ -uint32_t si_translate_colorformat(enum chip_class chip_class, +uint32_t si_translate_colorformat(enum amd_gfx_level gfx_level, enum pipe_format format) { const struct util_format_description *desc = util_format_description(format); @@ -1656,7 +1656,7 @@ uint32_t si_translate_colorformat(enum chip_class chip_class, if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ return V_028C70_COLOR_10_11_11; - if (chip_class >= GFX10_3 && + if (gfx_level >= GFX10_3 && format == PIPE_FORMAT_R9G9B9E5_FLOAT) /* isn't plain */ return V_028C70_COLOR_5_9_9_9; @@ -1813,7 +1813,7 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, enum pipe_for bool uniform = true; int i; - assert(sscreen->info.chip_class <= GFX9); + assert(sscreen->info.gfx_level <= GFX9); /* Colorspace (return non-RGB formats directly). */ switch (desc->colorspace) { @@ -1829,7 +1829,7 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, enum pipe_for * gathers in stencil sampling. This affects at least * GL45-CTS.texture_cube_map_array.sampling on GFX8. */ - if (sscreen->info.chip_class <= GFX8) + if (sscreen->info.gfx_level <= GFX8) return V_008F14_IMG_DATA_FORMAT_8_8_8_8; if (format == PIPE_FORMAT_X24S8_UINT) @@ -2172,7 +2172,7 @@ static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex, un /* GFX9 allocates 1D textures as 2D. */ if ((res_target == PIPE_TEXTURE_1D || res_target == PIPE_TEXTURE_1D_ARRAY) && - sscreen->info.chip_class == GFX9 && + sscreen->info.gfx_level == GFX9 && tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) { if (res_target == PIPE_TEXTURE_1D) res_target = PIPE_TEXTURE_2D; @@ -2216,7 +2216,7 @@ static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe desc->channel[0].size == 64) return false; - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&sscreen->info)[format]; if (!fmt->img_format || fmt->buffers_only) return false; @@ -2233,7 +2233,7 @@ static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen, { int i; - assert(((struct si_screen *)screen)->info.chip_class <= GFX9); + assert(((struct si_screen *)screen)->info.gfx_level <= GFX9); if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) return V_008F0C_BUF_DATA_FORMAT_10_11_11; @@ -2307,7 +2307,7 @@ static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen, const struct util_format_description *desc, int first_non_void) { - assert(((struct si_screen *)screen)->info.chip_class <= GFX9); + assert(((struct si_screen *)screen)->info.gfx_level <= GFX9); if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) return V_008F0C_BUF_NUM_FORMAT_FLOAT; @@ -2369,7 +2369,7 @@ static unsigned si_is_vertex_format_supported(struct pipe_screen *screen, enum p } } - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&sscreen->info)[format]; if (!fmt->img_format || fmt->img_format >= 128) return 0; @@ -2384,11 +2384,11 @@ static unsigned si_is_vertex_format_supported(struct pipe_screen *screen, enum p return usage; } -static bool si_is_colorbuffer_format_supported(enum chip_class chip_class, +static bool si_is_colorbuffer_format_supported(enum amd_gfx_level gfx_level, enum pipe_format format) { - return si_translate_colorformat(chip_class, format) != V_028C70_COLOR_INVALID && - si_translate_colorswap(chip_class, format, false) != ~0U; + return si_translate_colorformat(gfx_level, format) != V_028C70_COLOR_INVALID && + si_translate_colorswap(gfx_level, format, false) != ~0U; } static bool si_is_zs_format_supported(enum pipe_format format) @@ -2456,7 +2456,7 @@ static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format /* Gfx11: BGRA doesn't work with samples >= 4. Only allow R/0/1 to be the first * component for simplicity. */ - if (sscreen->info.chip_class >= GFX11 && + if (sscreen->info.gfx_level >= GFX11 && !util_format_is_depth_or_stencil(format) && util_format_description(format)->swizzle[0] != PIPE_SWIZZLE_X && util_format_description(format)->swizzle[0] != PIPE_SWIZZLE_0 && @@ -2476,7 +2476,7 @@ static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format if ((usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_BLENDABLE)) && - si_is_colorbuffer_format_supported(sscreen->info.chip_class, format)) { + si_is_colorbuffer_format_supported(sscreen->info.gfx_level, format)) { retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED); if (!util_format_is_pure_integer(format) && !util_format_is_depth_or_stencil(format)) @@ -2560,12 +2560,12 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa } } - format = si_translate_colorformat(sctx->chip_class, surf->base.format); + format = si_translate_colorformat(sctx->gfx_level, surf->base.format); if (format == V_028C70_COLOR_INVALID) { PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format); } assert(format != V_028C70_COLOR_INVALID); - swap = si_translate_colorswap(sctx->chip_class, surf->base.format, false); + swap = si_translate_colorswap(sctx->gfx_level, surf->base.format, false); endian = si_colorformat_endian_swap(format); /* blend clamp should be set for all NORM/SRGB types */ @@ -2598,7 +2598,7 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa format != V_028C70_COLOR_24_8) | S_028C70_NUMBER_TYPE(ntype); - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { assert(!SI_BIG_ENDIAN); color_info |= S_028C70_FORMAT_GFX11(format); } else { @@ -2606,7 +2606,7 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa } /* Intensity is implemented as Red, so treat it that way. */ - color_attrib = sctx->chip_class >= GFX11 ? + color_attrib = sctx->gfx_level >= GFX11 ? S_028C74_FORCE_DST_ALPHA_1_GFX11(desc->swizzle[3] == PIPE_SWIZZLE_1 || util_format_is_intensity(surf->base.format)): S_028C74_FORCE_DST_ALPHA_1_GFX6(desc->swizzle[3] == PIPE_SWIZZLE_1 || util_format_is_intensity(surf->base.format)); @@ -2614,7 +2614,7 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples); unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples); - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { color_attrib |= S_028C74_NUM_FRAGMENTS_GFX11(log_fragments); } else { color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS_GFX6(log_fragments); @@ -2623,7 +2623,7 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa color_info |= S_028C70_COMPRESSION(1); unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.color.fmask.bankh); - if (sctx->chip_class == GFX6) { + if (sctx->gfx_level == GFX6) { /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */ color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); } @@ -2639,16 +2639,16 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa if (!sctx->screen->info.has_dedicated_vram) min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B; - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) | S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.color.dcc.max_compressed_block_size) | S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) | S_028C78_INDEPENDENT_64B_BLOCKS(tex->surface.u.gfx9.color.dcc.independent_64B_blocks); - if (sctx->chip_class >= GFX11) + if (sctx->gfx_level >= GFX11) surf->cb_dcc_control |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX11(tex->surface.u.gfx9.color.dcc.independent_128B_blocks); else surf->cb_dcc_control |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX10(tex->surface.u.gfx9.color.dcc.independent_128B_blocks); - } else if (sctx->chip_class >= GFX8) { + } else if (sctx->gfx_level >= GFX8) { unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B; if (tex->buffer.b.b.nr_storage_samples > 1) { @@ -2664,7 +2664,7 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa } /* This must be set for fast clear to work without FMASK. */ - if (!tex->surface.fmask_size && sctx->chip_class == GFX6) { + if (!tex->surface.fmask_size && sctx->gfx_level == GFX6) { unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh); color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh); } @@ -2676,19 +2676,19 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa unsigned mip0_height = surf->height0 - 1; unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0); - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level); surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) | S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) | - S_028EE0_RESOURCE_LEVEL(sctx->chip_class >= GFX11 ? 0 : 1); - } else if (sctx->chip_class == GFX9) { + S_028EE0_RESOURCE_LEVEL(sctx->gfx_level >= GFX11 ? 0 : 1); + } else if (sctx->gfx_level == GFX9) { color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level); color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) | S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type); } - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(mip0_width) | S_028C68_MIP0_HEIGHT(mip0_height) | S_028C68_MAX_MIP(tex->buffer.b.b.last_level); @@ -2723,12 +2723,12 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su surf->db_htile_data_base = 0; surf->db_htile_surface = 0; - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) | S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11); } - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { assert(tex->surface.u.gfx9.surf_offset == 0); surf->db_depth_base = tex->buffer.gpu_address >> 8; surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.zs.stencil_offset) >> 8; @@ -2736,12 +2736,12 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) | S_028038_SW_MODE(tex->surface.u.gfx9.swizzle_mode) | S_028038_MAXMIP(tex->buffer.b.b.last_level) | - S_028040_ITERATE_256(sctx->chip_class >= GFX11); + S_028040_ITERATE_256(sctx->gfx_level >= GFX11); s_info = S_02803C_FORMAT(stencil_format) | S_02803C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode) | - S_028044_ITERATE_256(sctx->chip_class >= GFX11); + S_028044_ITERATE_256(sctx->gfx_level >= GFX11); - if (sctx->chip_class == GFX9) { + if (sctx->gfx_level == GFX9) { surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.epitch); surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.zs.stencil_epitch); } @@ -2763,7 +2763,7 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8; surf->db_htile_surface = S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1); - if (sctx->chip_class == GFX9) { + if (sctx->gfx_level == GFX9) { surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); } } @@ -2783,7 +2783,7 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su s_info = S_028044_FORMAT(stencil_format); surf->db_depth_info = 0; - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { struct radeon_info *info = &sctx->screen->info; unsigned index = tex->surface.u.legacy.tiling_index[level]; unsigned stencil_index = tex->surface.u.legacy.zs.stencil_tiling_index[level]; @@ -3006,7 +3006,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, */ if (sctx->generate_mipmap_for_depth) { si_make_DB_shader_coherent(sctx, 1, false, sctx->framebuffer.DB_has_shader_readable_metadata); - } else if (sctx->chip_class == GFX9) { + } else if (sctx->gfx_level == GFX9) { /* It appears that DB metadata "leaks" in a sequence of: * - depth clear * - DCC decompress for shader image writes (with DB disabled) @@ -3090,7 +3090,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, if (vi_dcc_enabled(tex, surf->base.u.tex.level)) { sctx->framebuffer.CB_has_shader_readable_metadata = true; - if (sctx->chip_class >= GFX9 && !tex->surface.u.gfx9.color.dcc.pipe_aligned) + if (sctx->gfx_level >= GFX9 && !tex->surface.u.gfx9.color.dcc.pipe_aligned) sctx->framebuffer.all_DCC_pipe_aligned = false; if (tex->buffer.b.b.nr_storage_samples >= 2) @@ -3108,7 +3108,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, } /* For optimal DCC performance. */ - if (sctx->chip_class >= GFX10) + if (sctx->gfx_level >= GFX10) sctx->framebuffer.dcc_overwrite_combiner_watermark = 6; else sctx->framebuffer.dcc_overwrite_combiner_watermark = 4; @@ -3235,7 +3235,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb = (struct si_surface *)state->cbufs[i]; if (!cb) { radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, - sctx->chip_class >= GFX11 ? + sctx->gfx_level >= GFX11 ? S_028C70_FORMAT_GFX11(V_028C70_COLOR_INVALID) : S_028C70_FORMAT_GFX6(V_028C70_COLOR_INVALID)); continue; @@ -3274,7 +3274,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb_color_info |= S_028C70_COMP_SWAP(swap); } - if (sctx->chip_class < GFX11 && cb->base.u.tex.level > 0) + if (sctx->gfx_level < GFX11 && cb->base.u.tex.level > 0) cb_color_info &= C_028C70_FAST_CLEAR; if (tex->surface.fmask_offset) { @@ -3289,9 +3289,9 @@ static void si_emit_framebuffer_state(struct si_context *sctx) state->cbufs[1]->texture->nr_samples <= 1; /* CB can't do MSAA resolve on gfx11. */ - assert(!is_msaa_resolve_dst || sctx->chip_class < GFX11); + assert(!is_msaa_resolve_dst || sctx->gfx_level < GFX11); - if (!is_msaa_resolve_dst && sctx->chip_class < GFX11) + if (!is_msaa_resolve_dst && sctx->gfx_level < GFX11) cb_color_info |= S_028C70_DCC_ENABLE(1); cb_dcc_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8; @@ -3301,7 +3301,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb_dcc_base |= dcc_tile_swizzle; } - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { unsigned cb_color_attrib3, cb_fdcc_control; /* Set mutable surface parameters. */ @@ -3327,7 +3327,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32); radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb_color_attrib2); radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3); - } else if (sctx->chip_class >= GFX10) { + } else if (sctx->gfx_level >= GFX10) { unsigned cb_color_attrib3; /* Set mutable surface parameters. */ @@ -3368,7 +3368,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32); radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb_color_attrib2); radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3); - } else if (sctx->chip_class == GFX9) { + } else if (sctx->gfx_level == GFX9) { struct gfx9_surf_meta_flags meta = { .rb_aligned = 1, .pipe_aligned = 1, @@ -3436,7 +3436,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb_color_slice = S_028C68_TILE_MAX(slice_tile_max); if (tex->surface.fmask_offset) { - if (sctx->chip_class >= GFX7) + if (sctx->gfx_level >= GFX7) cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.color.fmask.pitch_in_pixels / 8 - 1); cb_color_attrib |= @@ -3444,14 +3444,14 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.color.fmask.slice_tile_max); } else { /* This must be set for fast clear to work without FMASK. */ - if (sctx->chip_class >= GFX7) + if (sctx->gfx_level >= GFX7) cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max); cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index); cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max); } radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C, - sctx->chip_class >= GFX8 ? 14 : 13); + sctx->gfx_level >= GFX8 ? 14 : 13); radeon_emit(cb_color_base); /* CB_COLOR0_BASE */ radeon_emit(cb_color_pitch); /* CB_COLOR0_PITCH */ radeon_emit(cb_color_slice); /* CB_COLOR0_SLICE */ @@ -3466,7 +3466,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */ radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */ - if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */ + if (sctx->gfx_level >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */ radeon_emit(cb_dcc_base); } } @@ -3488,13 +3488,13 @@ static void si_emit_framebuffer_state(struct si_context *sctx) bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS); /* Set fields dependent on tc_compatile_htile. */ - if (sctx->chip_class >= GFX9 && tc_compat_htile) { + if (sctx->gfx_level >= GFX9 && tc_compat_htile) { unsigned max_zplanes = 4; if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM && tex->buffer.b.b.nr_samples > 1) max_zplanes = 2; - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { bool iterate256 = tex->buffer.b.b.nr_samples >= 2; db_z_info |= S_028040_ITERATE_FLUSH(1) | S_028040_ITERATE_256(iterate256); @@ -3516,11 +3516,11 @@ static void si_emit_framebuffer_state(struct si_context *sctx) unsigned level = zb->base.u.tex.level; - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base); radeon_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size); - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { radeon_set_context_reg_seq(R_028040_DB_Z_INFO, 6); } else { radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 7); @@ -3540,7 +3540,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) radeon_emit(zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */ radeon_emit(zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */ radeon_emit(zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */ - } else if (sctx->chip_class == GFX9) { + } else if (sctx->gfx_level == GFX9) { radeon_set_context_reg_seq(R_028014_DB_HTILE_DATA_BASE, 3); radeon_emit(zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */ radeon_emit(S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */ @@ -3602,7 +3602,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) radeon_set_context_reg(R_028008_DB_DEPTH_VIEW, zb->db_depth_view); radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); } else if (sctx->framebuffer.dirty_zsbuf) { - if (sctx->chip_class == GFX9) + if (sctx->gfx_level == GFX9) radeon_set_context_reg_seq(R_028038_DB_Z_INFO, 2); else radeon_set_context_reg_seq(R_028040_DB_Z_INFO, 2); @@ -3611,7 +3611,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) * It affects VRS and occlusion queries if depth and stencil are not bound. */ radeon_emit(S_028040_FORMAT(V_028040_Z_INVALID) | /* DB_Z_INFO */ - S_028040_NUM_SAMPLES(sctx->chip_class == GFX11 ? sctx->framebuffer.log_samples : 0)); + S_028040_NUM_SAMPLES(sctx->gfx_level == GFX11 ? sctx->framebuffer.log_samples : 0)); radeon_emit(S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */ } @@ -3651,7 +3651,7 @@ static void si_emit_msaa_sample_locs(struct si_context *sctx) * GFX10 uses sample locations unconditionally, so they always need * to be set up. */ - if ((nr_samples >= 2 || has_msaa_sample_loc_bug || sctx->chip_class >= GFX10) && + if ((nr_samples >= 2 || has_msaa_sample_loc_bug || sctx->gfx_level >= GFX10) && nr_samples != sctx->sample_locs_num_samples) { sctx->sample_locs_num_samples = nr_samples; si_emit_sample_locations(cs, nr_samples); @@ -3686,7 +3686,7 @@ static void si_emit_msaa_sample_locs(struct si_context *sctx) /* The exclusion bits can be set to improve rasterization efficiency * if no sample lies on the pixel boundary (-8 sample offset). */ - bool exclusion = sctx->chip_class >= GFX7 && (!rs->multisample_enable || nr_samples != 16); + bool exclusion = sctx->gfx_level >= GFX7 && (!rs->multisample_enable || nr_samples != 16); radeon_opt_set_context_reg( sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL, SI_TRACKED_PA_SU_PRIM_FILTER_CNTL, S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion)); @@ -3849,11 +3849,11 @@ static void si_emit_msaa_config(struct si_context *sctx) S_028BDC_PERPENDICULAR_ENDCAP_ENA(rs->perpendicular_end_caps) | S_028BDC_EXTRA_DX_DY_PRECISION(rs->perpendicular_end_caps && (sctx->family == CHIP_VEGA20 || - sctx->chip_class >= GFX10)); + sctx->gfx_level >= GFX10)); sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) | S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) | S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | - S_028BE0_COVERED_CENTROID_IS_CENTER(sctx->chip_class >= GFX10_3); + S_028BE0_COVERED_CENTROID_IS_CENTER(sctx->gfx_level >= GFX10_3); if (sctx->framebuffer.nr_samples > 1) { db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) | @@ -3951,7 +3951,7 @@ void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units. * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE. */ - if (screen->info.chip_class == GFX8) + if (screen->info.gfx_level == GFX8) num_records *= stride; state[4] = 0; @@ -3962,7 +3962,7 @@ void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])); - if (screen->info.chip_class >= GFX10) { + if (screen->info.gfx_level >= GFX10) { const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&screen->info)[format]; /* OOB_SELECT chooses the out-of-bounds check: @@ -3974,7 +3974,7 @@ void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf */ state[7] |= S_008F0C_FORMAT(fmt->img_format) | S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) | - S_008F0C_RESOURCE_LEVEL(screen->info.chip_class < GFX11); + S_008F0C_RESOURCE_LEVEL(screen->info.gfx_level < GFX11); } else { int first_non_void; unsigned num_format, data_format; @@ -4063,7 +4063,7 @@ static void gfx10_make_texture_descriptor( } if (tex->upgraded_depth && !is_stencil) { - if (screen->info.chip_class >= GFX11) { + if (screen->info.gfx_level >= GFX11) { assert(img_format == V_008F0C_GFX11_FORMAT_32_FLOAT); img_format = V_008F0C_GFX11_FORMAT_32_FLOAT_CLAMP; } else { @@ -4096,7 +4096,7 @@ static void gfx10_make_texture_descriptor( state[0] = 0; state[1] = S_00A004_FORMAT(img_format) | S_00A004_WIDTH_LO(width - 1); state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) | S_00A008_HEIGHT(height - 1) | - S_00A008_RESOURCE_LEVEL(screen->info.chip_class < GFX11); + S_00A008_RESOURCE_LEVEL(screen->info.gfx_level < GFX11); state[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) | @@ -4118,7 +4118,7 @@ static void gfx10_make_texture_descriptor( unsigned max_mip = res->nr_samples > 1 ? util_logbase2(res->nr_samples) : tex->buffer.b.b.last_level; - if (screen->info.chip_class >= GFX11) { + if (screen->info.gfx_level >= GFX11) { state[1] |= S_00A004_MAX_MIP(max_mip); } else { state[5] |= S_00A014_MAX_MIP(max_mip); @@ -4240,7 +4240,7 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu * fix texture gathers. This affects at least * GL45-CTS.texture_cube_map_array.sampling on GFX8. */ - if (screen->info.chip_class <= GFX8) + if (screen->info.gfx_level <= GFX8) util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle); else util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle); @@ -4326,11 +4326,11 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu } /* S8 with Z32 HTILE needs a special format. */ - if (screen->info.chip_class == GFX9 && pipe_format == PIPE_FORMAT_S8_UINT) + if (screen->info.gfx_level == GFX9 && pipe_format == PIPE_FORMAT_S8_UINT) data_format = V_008F14_IMG_DATA_FORMAT_S8_32; if (!sampler && (res->target == PIPE_TEXTURE_CUBE || res->target == PIPE_TEXTURE_CUBE_ARRAY || - (screen->info.chip_class <= GFX8 && res->target == PIPE_TEXTURE_3D))) { + (screen->info.gfx_level <= GFX8 && res->target == PIPE_TEXTURE_3D))) { /* For the purpose of shader images, treat cube maps and 3D * textures as 2D arrays. For 3D textures, the address * calculations for mipmaps are different, so we rely on the @@ -4367,7 +4367,7 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu state[6] = 0; state[7] = 0; - if (screen->info.chip_class == GFX9) { + if (screen->info.gfx_level == GFX9) { unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle); /* Depth is the the last accessible layer on Gfx9. @@ -4393,7 +4393,7 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu /* The last dword is unused by hw. The shader uses it to clear * bits in the first dword of sampler state. */ - if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) { + if (screen->info.gfx_level <= GFX7 && res->nr_samples <= 1) { if (first_level == last_level) state[7] = C_008F30_MAX_ANISO_RATIO; else @@ -4408,7 +4408,7 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu va = tex->buffer.gpu_address + tex->surface.fmask_offset; #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f))) - if (screen->info.chip_class == GFX9) { + if (screen->info.gfx_level == GFX9) { data_format = V_008F14_IMG_DATA_FORMAT_FMASK; switch (FMASK(res->nr_samples, res->nr_storage_samples)) { case FMASK(2, 1): @@ -4514,7 +4514,7 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu fmask_state[6] = 0; fmask_state[7] = 0; - if (screen->info.chip_class == GFX9) { + if (screen->info.gfx_level == GFX9) { fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode); fmask_state[4] |= S_008F20_DEPTH(last_layer) | S_008F20_PITCH(tex->surface.u.gfx9.color.fmask_epitch); @@ -4713,7 +4713,7 @@ static uint32_t si_translate_border_color(struct si_context *sctx, sctx->border_color_count++; } - return (sctx->screen->info.chip_class >= GFX11 ? S_008F3C_BORDER_COLOR_PTR_GFX11(i): + return (sctx->screen->info.gfx_level >= GFX11 ? S_008F3C_BORDER_COLOR_PTR_GFX11(i): S_008F3C_BORDER_COLOR_PTR_GFX6(i)) | S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER); } @@ -4785,7 +4785,7 @@ static void *si_create_sampler_state(struct pipe_context *ctx, S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) | S_008F30_ANISO_BIAS(max_aniso_ratio) | S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) | S_008F30_TRUNC_COORD(trunc_coord) | - S_008F30_COMPAT_MODE(sctx->chip_class == GFX8 || sctx->chip_class == GFX9)); + S_008F30_COMPAT_MODE(sctx->gfx_level == GFX8 || sctx->gfx_level == GFX9)); rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) | S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0)); @@ -4796,12 +4796,12 @@ static void *si_create_sampler_state(struct pipe_context *ctx, rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, state->border_color_is_integer); - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { rstate->val[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1); } else { - rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) | + rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->gfx_level <= GFX8) | S_008F38_FILTER_PREC_FIX(1) | - S_008F38_ANISO_OVERRIDE_GFX8(sctx->chip_class >= GFX8); + S_008F38_ANISO_OVERRIDE_GFX8(sctx->gfx_level >= GFX8); } /* Create sampler resource for upgraded depth textures. */ @@ -4814,7 +4814,7 @@ static void *si_create_sampler_state(struct pipe_context *ctx, } if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) { - if (sscreen->info.chip_class <= GFX9) + if (sscreen->info.gfx_level <= GFX9) rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1); } else { rstate->upgraded_depth_val[3] = @@ -4995,7 +4995,7 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count, * unsigned, so a shader workaround is needed. The affected * chips are GFX8 and older except Stoney (GFX8.1). */ - always_fix = sscreen->info.chip_class <= GFX8 && sscreen->info.family != CHIP_STONEY && + always_fix = sscreen->info.gfx_level <= GFX8 && sscreen->info.family != CHIP_STONEY && channel->type == UTIL_FORMAT_TYPE_SIGNED; } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) { fix_fetch.u.log_size = 3; /* special encoding */ @@ -5040,7 +5040,7 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count, */ bool check_alignment = log_hw_load_size >= 1 && - (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class >= GFX10); + (sscreen->info.gfx_level == GFX6 || sscreen->info.gfx_level >= GFX10); bool opencode = sscreen->options.vs_fetch_always_opencode; if (check_alignment && (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0) @@ -5067,11 +5067,11 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count, S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])); - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&sscreen->info)[elements[i].src_format]; assert(fmt->img_format != 0 && fmt->img_format < 128); v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) | - S_008F0C_RESOURCE_LEVEL(sscreen->info.chip_class < GFX11); + S_008F0C_RESOURCE_LEVEL(sscreen->info.gfx_level < GFX11); } else { unsigned data_format, num_format; data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void); @@ -5377,7 +5377,7 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) /* Indices are read through TC L2 since GFX8. * L1 isn't used. */ - if (sctx->screen->info.chip_class <= GFX7) + if (sctx->screen->info.gfx_level <= GFX7) sctx->flags |= SI_CONTEXT_WB_L2; } @@ -5387,12 +5387,12 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) if (flags & PIPE_BARRIER_FRAMEBUFFER && sctx->framebuffer.uncompressed_cb_mask) { sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB; - if (sctx->chip_class <= GFX8) + if (sctx->gfx_level <= GFX8) sctx->flags |= SI_CONTEXT_WB_L2; } /* Indirect buffers use TC L2 on GFX9, but not older hw. */ - if (sctx->screen->info.chip_class <= GFX8 && flags & PIPE_BARRIER_INDIRECT_BUFFER) + if (sctx->screen->info.gfx_level <= GFX8 && flags & PIPE_BARRIER_INDIRECT_BUFFER) sctx->flags |= SI_CONTEXT_WB_L2; } @@ -5444,7 +5444,7 @@ void si_init_state_functions(struct si_context *sctx) sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx); - if (sctx->chip_class < GFX11) { + if (sctx->gfx_level < GFX11) { sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE); sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS); sctx->custom_blend_eliminate_fastclear = @@ -5452,7 +5452,7 @@ void si_init_state_functions(struct si_context *sctx) } sctx->custom_blend_dcc_decompress = - si_create_blend_custom(sctx, sctx->chip_class >= GFX11 ? + si_create_blend_custom(sctx, sctx->gfx_level >= GFX11 ? V_028808_CB_DCC_DECOMPRESS_GFX11 : V_028808_CB_DCC_DECOMPRESS_GFX8); @@ -5482,7 +5482,7 @@ void si_init_screen_state_functions(struct si_screen *sscreen) sscreen->b.create_vertex_state = si_pipe_create_vertex_state; sscreen->b.vertex_state_destroy = si_pipe_vertex_state_destroy; - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { sscreen->make_texture_descriptor = gfx10_make_texture_descriptor; } else { sscreen->make_texture_descriptor = si_make_texture_descriptor; @@ -5494,7 +5494,7 @@ void si_init_screen_state_functions(struct si_screen *sscreen) static void si_set_grbm_gfx_index(struct si_context *sctx, struct si_pm4_state *pm4, unsigned value) { - unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX : R_00802C_GRBM_GFX_INDEX; + unsigned reg = sctx->gfx_level >= GFX7 ? R_030800_GRBM_GFX_INDEX : R_00802C_GRBM_GFX_INDEX; si_pm4_set_reg(pm4, reg, value); } @@ -5522,7 +5522,7 @@ static void si_write_harvested_raster_configs(struct si_context *sctx, struct si } si_set_grbm_gfx_index(sctx, pm4, ~0); - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); } } @@ -5540,7 +5540,7 @@ static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *p * (or when we failed to determine the enabled backends). */ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config); - if (sctx->chip_class >= GFX7) + if (sctx->gfx_level >= GFX7) si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); } else { si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1); @@ -5606,22 +5606,22 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); - if (sctx->chip_class < GFX11) { + if (sctx->gfx_level < GFX11) { si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2); si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); } } si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8); - if (sctx->chip_class >= GFX7) + if (sctx->gfx_level >= GFX7) si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, S_028084_ADDRESS(border_color_va >> 40)); - if (sctx->chip_class == GFX6) { + if (sctx->gfx_level == GFX6) { si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1)); } - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { si_pm4_set_reg(pm4, R_030A00_PA_SU_LINE_STIPPLE_VALUE, 0); si_pm4_set_reg(pm4, R_030A04_PA_SC_LINE_STIPPLE_STATE, 0); } else { @@ -5629,8 +5629,8 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) si_pm4_set_reg(pm4, R_008B10_PA_SC_LINE_STIPPLE_STATE, 0); } - if (sctx->chip_class <= GFX7 || !has_clear_state) { - if (sctx->chip_class < GFX11) { + if (sctx->gfx_level <= GFX7 || !has_clear_state) { + if (sctx->gfx_level < GFX11) { si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14); si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16); } @@ -5645,7 +5645,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) S_028034_BR_X(16384) | S_028034_BR_Y(16384)); } - if (sctx->chip_class >= GFX10 && sctx->chip_class < GFX11) { + if (sctx->gfx_level >= GFX10 && sctx->gfx_level < GFX11) { si_pm4_set_reg(pm4, R_028038_DB_DFSM_CONTROL, S_028038_PUNCHOUT_MODE(V_028038_FORCE_OFF) | S_028038_POPS_DRAIN_PS_ON_OVERLAP(1)); @@ -5653,19 +5653,19 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) unsigned cu_mask_ps = 0xffffffff; - if (sctx->chip_class >= GFX10_3) + if (sctx->gfx_level >= GFX10_3) cu_mask_ps = gfx103_get_cu_mask_ps(sscreen); - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { ac_set_reg_cu_en(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(cu_mask_ps) | S_00B01C_WAVE_LIMIT(0x3F) | - S_00B01C_LDS_GROUP_SIZE(sctx->chip_class >= GFX11), + S_00B01C_LDS_GROUP_SIZE(sctx->gfx_level >= GFX11), C_00B01C_CU_EN, 0, &sscreen->info, - (void*)(sctx->chip_class >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg)); + (void*)(sctx->gfx_level >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg)); } - if (sctx->chip_class <= GFX8) { + if (sctx->gfx_level <= GFX8) { si_set_raster_config(sctx, pm4); /* FIXME calculate these values somehow ??? */ @@ -5681,12 +5681,12 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0); } - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(sscreen->info.address32_hi >> 8)); si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8)); - } else if (sscreen->info.chip_class == GFX9) { + } else if (sscreen->info.gfx_level == GFX9) { si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(sscreen->info.address32_hi >> 8)); si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, @@ -5696,7 +5696,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) S_00B524_MEM_BASE(sscreen->info.address32_hi >> 8)); } - if (sctx->chip_class >= GFX7 && sctx->chip_class <= GFX8) { + if (sctx->gfx_level >= GFX7 && sctx->gfx_level <= GFX8) { ac_set_reg_cu_en(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F), C_00B51C_CU_EN, 0, &sscreen->info, (void*)si_pm4_set_reg); @@ -5713,7 +5713,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) S_028A44_ES_VERTS_PER_SUBGRP(64) | S_028A44_GS_PRIMS_PER_SUBGRP(4)); } - if (sctx->chip_class == GFX8) { + if (sctx->gfx_level == GFX8) { unsigned vgt_tess_distribution; vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) | S_028B50_ACCUM_TRI(11) | @@ -5728,11 +5728,11 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution); } - if (sscreen->info.chip_class <= GFX9) { + if (sscreen->info.gfx_level <= GFX9) { si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1); } - if (sctx->chip_class == GFX9) { + if (sctx->gfx_level == GFX9) { si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0); si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0); si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0); @@ -5742,11 +5742,11 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) S_028060_POPS_DRAIN_PS_ON_OVERLAP(1)); } - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { ac_set_reg_cu_en(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F), C_00B41C_CU_EN, 0, &sscreen->info, - (void*)(sctx->chip_class >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg)); + (void*)(sctx->gfx_level >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg)); si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, S_028B50_ACCUM_ISOLINE(12) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) | @@ -5759,13 +5759,13 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0); - if (sctx->chip_class < GFX11) { + if (sctx->gfx_level < GFX11) { si_pm4_set_reg(pm4, R_0301EC_CP_COHER_START_DELAY, - sctx->chip_class >= GFX10 ? 0x20 : 0); + sctx->gfx_level >= GFX10 ? 0x20 : 0); } } - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { si_pm4_set_reg(pm4, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 0); si_pm4_set_reg(pm4, R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1, 0); si_pm4_set_reg(pm4, R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2, 0); @@ -5785,7 +5785,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) /* Enable CMASK/HTILE/DCC caching in L2 for small chips. */ unsigned meta_write_policy, meta_read_policy; - unsigned no_alloc = sctx->chip_class >= GFX11 ? V_02807C_CACHE_NOA_GFX11: + unsigned no_alloc = sctx->gfx_level >= GFX11 ? V_02807C_CACHE_NOA_GFX11: V_02807C_CACHE_NOA_GFX10; if (sscreen->info.max_render_backends <= 4) { meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */ @@ -5805,7 +5805,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) S_02807C_HTILE_RD_POLICY(meta_read_policy)); unsigned gl2_cc; - if (sctx->chip_class >= GFX11) + if (sctx->gfx_level >= GFX11) gl2_cc = S_028410_DCC_WR_POLICY_GFX11(meta_write_policy) | S_028410_COLOR_WR_POLICY_GFX11(V_028410_CACHE_STREAM) | S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX11); @@ -5835,9 +5835,9 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) * a single primitive shader subgroup. */ si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL, - S_028C50_MAX_DEALLOCS_IN_WAVE(sctx->chip_class >= GFX11 ? 16 : 512)); + S_028C50_MAX_DEALLOCS_IN_WAVE(sctx->gfx_level >= GFX11 ? 16 : 512)); - if (sctx->chip_class < GFX11) { + if (sctx->gfx_level < GFX11) { /* Reuse for legacy (non-NGG) only. */ si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14); } @@ -5855,7 +5855,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) si_pm4_set_reg(pm4, R_030988_GE_USER_VGPR_EN, 0); } - if (sctx->chip_class >= GFX10 && sctx->chip_class <= GFX10_3) { + if (sctx->gfx_level >= GFX10 && sctx->gfx_level <= GFX10_3) { /* Logical CUs 16 - 31 */ ac_set_reg_cu_en(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS, S_00B004_CU_EN(cu_mask_ps >> 16), C_00B004_CU_EN, 16, &sscreen->info, (void*)si_pm4_set_reg_idx3); @@ -5871,7 +5871,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) si_pm4_set_reg(pm4, R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3, 0); } - if (sctx->chip_class >= GFX10_3) { + if (sctx->gfx_level >= GFX10_3) { si_pm4_set_reg(pm4, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff); /* The rate combiners have no effect if they are disabled like this: * VERTEX_RATE: BYPASS_VTX_RATE_COMBINER = 1 @@ -5887,7 +5887,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_VRS_COMB_MODE_OVERRIDE)); } - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { si_pm4_set_reg(pm4, R_028C54_PA_SC_BINNER_CNTL_2, 0); si_pm4_set_reg(pm4, R_028620_PA_RATE_CNTL, S_028620_VERTEX_RATE(2) | S_028620_PRIM_RATE(1)); diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index b6e83a186c1..4cbcde6ac34 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -529,7 +529,7 @@ struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap, uns void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab); void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf); /* si_state.c */ -uint32_t si_translate_colorformat(enum chip_class chip_class, enum pipe_format format); +uint32_t si_translate_colorformat(enum amd_gfx_level gfx_level, enum pipe_format format); void si_init_state_compute_functions(struct si_context *sctx); void si_init_state_functions(struct si_context *sctx); void si_init_screen_state_functions(struct si_screen *sscreen); diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c index 49c5758ac07..48c2343f8ba 100644 --- a/src/gallium/drivers/radeonsi/si_state_binning.c +++ b/src/gallium/drivers/radeonsi/si_state_binning.c @@ -406,7 +406,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx) { radeon_begin(&sctx->gfx_cs); - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { struct uvec2 bin_size = {}; struct uvec2 bin_size_extend = {}; @@ -446,7 +446,7 @@ void si_emit_dpbb_state(struct si_context *sctx) struct si_state_dsa *dsa = sctx->queued.named.dsa; unsigned db_shader_control = sctx->ps_db_shader_control; - assert(sctx->chip_class >= GFX9); + assert(sctx->gfx_level >= GFX9); if (!sscreen->dpbb_allowed || sctx->dpbb_force_off || sctx->dpbb_force_off_profile_vs || sctx->dpbb_force_off_profile_ps) { @@ -475,7 +475,7 @@ void si_emit_dpbb_state(struct si_context *sctx) sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_enabled_4bit; struct uvec2 color_bin_size, depth_bin_size; - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { gfx10_get_bin_sizes(sctx, cb_target_enabled_4bit, &color_bin_size, &depth_bin_size); } else { color_bin_size = si_get_color_bin_size(sctx, cb_target_enabled_4bit); diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index 8bf1bea07a7..9103cacc1f4 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -45,7 +45,7 @@ #elif (GFX_VER == 11) #define GFX(name) name##GFX11 #else -#error "Unknown gfx version" +#error "Unknown gfx level" #endif /* special primitive types */ @@ -107,7 +107,7 @@ static void si_emit_spi_map(struct si_context *sctx) radeon_end_update_context_roll(sctx); } -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> static bool si_update_shaders(struct si_context *sctx) { struct pipe_context *ctx = (struct pipe_context *)sctx; @@ -400,7 +400,7 @@ static unsigned si_conv_pipe_prim(unsigned mode) return prim_conv[mode]; } -template<chip_class GFX_VERSION> +template<amd_gfx_level GFX_VERSION> static void si_cp_dma_prefetch_inline(struct si_context *sctx, struct pipe_resource *buf, unsigned offset, unsigned size) { @@ -449,7 +449,7 @@ static void si_cp_dma_prefetch_inline(struct si_context *sctx, struct pipe_resou void si_cp_dma_prefetch(struct si_context *sctx, struct pipe_resource *buf, unsigned offset, unsigned size) { - switch (sctx->chip_class) { + switch (sctx->gfx_level) { case GFX7: si_cp_dma_prefetch_inline<GFX7>(sctx, buf, offset, size); break; @@ -475,7 +475,7 @@ void si_cp_dma_prefetch(struct si_context *sctx, struct pipe_resource *buf, #endif -template<chip_class GFX_VERSION> +template<amd_gfx_level GFX_VERSION> static void si_prefetch_shader_async(struct si_context *sctx, struct si_shader *shader) { struct pipe_resource *bo = &shader->bo->b.b; @@ -492,7 +492,7 @@ enum si_L2_prefetch_mode { /** * Prefetch shaders. */ -template<chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, +template<amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, si_L2_prefetch_mode mode> static void si_prefetch_shaders(struct si_context *sctx) { @@ -623,12 +623,12 @@ static void si_emit_derived_tess_state(struct si_context *sctx, unsigned *num_pa struct si_shader_selector *tcs = sctx->shader.tcs.cso ? sctx->shader.tcs.cso : sctx->shader.tes.cso; unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id; - bool has_primid_instancing_bug = sctx->chip_class == GFX6 && sctx->screen->info.max_se == 1; + bool has_primid_instancing_bug = sctx->gfx_level == GFX6 && sctx->screen->info.max_se == 1; unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; uint8_t num_tcs_input_cp = sctx->patch_vertices; /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */ - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { if (sctx->shader.tcs.cso) ls_current = sctx->shader.tcs.current; else @@ -744,7 +744,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, unsigned *num_pa (wave_size - temp_verts_per_tg % wave_size >= MAX2(max_verts_per_patch, 8))) *num_patches = (temp_verts_per_tg & ~(wave_size - 1)) / max_verts_per_patch; - if (sctx->chip_class == GFX6) { + if (sctx->gfx_level == GFX6) { /* GFX6 bug workaround, related to power management. Limit LS-HS * threadgroups to only one wave. */ @@ -797,7 +797,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, unsigned *num_pa /* Compute the LDS size. */ unsigned lds_size = lds_per_patch * *num_patches; - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { assert(lds_size <= 65536); lds_size = align(lds_size, 512) / 512; } else { @@ -817,10 +817,10 @@ static void si_emit_derived_tess_state(struct si_context *sctx, unsigned *num_pa struct radeon_cmdbuf *cs = &sctx->gfx_cs; radeon_begin(cs); - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { unsigned hs_rsrc2 = ls_current->config.rsrc2; - if (sctx->chip_class >= GFX10) + if (sctx->gfx_level >= GFX10) hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(lds_size); else hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(lds_size); @@ -841,7 +841,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, unsigned *num_pa /* Due to a hw bug, RSRC2_LS must be written twice with another * LS register written in between. */ - if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII) + if (sctx->gfx_level == GFX7 && sctx->family != CHIP_HAWAII) radeon_set_sh_reg(R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2); radeon_set_sh_reg_seq(R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2); radeon_emit(ls_current->config.rsrc1); @@ -869,7 +869,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, unsigned *num_pa if (sctx->last_ls_hs_config != ls_hs_config) { radeon_begin(cs); - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { radeon_set_context_reg_idx(R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config); } else { radeon_set_context_reg(R_028B58_VGT_LS_HS_CONFIG, ls_hs_config); @@ -921,7 +921,7 @@ static unsigned si_get_init_multi_vgt_param(struct si_screen *sscreen, union si_ /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */ if (sscreen->info.has_distributed_tess) { if (key->u.uses_gs) { - if (sscreen->info.chip_class == GFX8) + if (sscreen->info.gfx_level == GFX8) partial_es_wave = true; } else { partial_vs_wave = true; @@ -935,7 +935,7 @@ static unsigned si_get_init_multi_vgt_param(struct si_screen *sscreen, union si_ wd_switch_on_eop = true; } - if (sscreen->info.chip_class >= GFX7) { + if (sscreen->info.gfx_level >= GFX7) { /* WD_SWITCH_ON_EOP has no effect on GPUs with less than * 4 shader engines. Set 1 to pass the assertion below. * The other cases are hardware requirements. @@ -964,7 +964,7 @@ static unsigned si_get_init_multi_vgt_param(struct si_screen *sscreen, union si_ * Assume indirect draws always use small instances. * This is needed for good VS wave utilization. */ - if (sscreen->info.chip_class <= GFX8 && sscreen->info.max_se == 4 && + if (sscreen->info.gfx_level <= GFX8 && sscreen->info.max_se == 4 && key->u.multi_instances_smaller_than_primgroup) wd_switch_on_eop = true; @@ -984,7 +984,7 @@ static unsigned si_get_init_multi_vgt_param(struct si_screen *sscreen, union si_ /* Required by Hawaii and, for some special cases, by GFX8. */ if (ia_switch_on_eoi && (sscreen->info.family == CHIP_HAWAII || - (sscreen->info.chip_class == GFX8 && (key->u.uses_gs || max_primgroup_in_wave != 2)))) + (sscreen->info.gfx_level == GFX8 && (key->u.uses_gs || max_primgroup_in_wave != 2)))) partial_vs_wave = true; /* Instancing bug on Bonaire. */ @@ -1002,18 +1002,18 @@ static unsigned si_get_init_multi_vgt_param(struct si_screen *sscreen, union si_ } /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */ - if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi) + if (sscreen->info.gfx_level <= GFX8 && ia_switch_on_eoi) partial_es_wave = true; return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) | S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) | S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) | - S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) | + S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.gfx_level >= GFX7 ? wd_switch_on_eop : 0) | /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */ - S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ? max_primgroup_in_wave + S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.gfx_level == GFX8 ? max_primgroup_in_wave : 0) | - S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) | - S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9); + S_030960_EN_INST_OPT_BASIC(sscreen->info.gfx_level >= GFX9) | + S_030960_EN_INST_OPT_ADV(sscreen->info.gfx_level >= GFX9); } static void si_init_ia_multi_vgt_param_table(struct si_context *sctx) @@ -1078,7 +1078,7 @@ static bool num_instanced_prims_less_than(const struct pipe_draw_indirect_info * } } -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx, const struct pipe_draw_indirect_info *indirect, @@ -1160,7 +1160,7 @@ static unsigned si_conv_prim_to_gs_out(unsigned mode) } /* rast_prim is the primitive type after GS. */ -template<chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS_INLINE +template<amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS_INLINE static void si_emit_rasterizer_prim_state(struct si_context *sctx) { struct radeon_cmdbuf *cs = &sctx->gfx_cs; @@ -1214,7 +1214,7 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx) } } -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE static void si_emit_vs_state(struct si_context *sctx, unsigned index_size) { @@ -1283,7 +1283,7 @@ static bool si_prim_restart_index_changed(struct si_context *sctx, bool primitiv sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN); } -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE static void si_emit_ia_multi_vgt_param(struct si_context *sctx, const struct pipe_draw_indirect_info *indirect, @@ -1322,7 +1322,7 @@ static void si_emit_ia_multi_vgt_param(struct si_context *sctx, /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL. * We overload last_multi_vgt_param. */ -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS_INLINE +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS_INLINE static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches) { union si_vgt_param_key key = sctx->ia_multi_vgt_param_key; @@ -1376,7 +1376,7 @@ static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches) } } -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE static void si_emit_draw_registers(struct si_context *sctx, const struct pipe_draw_indirect_info *indirect, @@ -1440,7 +1440,7 @@ static void si_emit_draw_registers(struct si_context *sctx, } \ } while (0) -template <chip_class GFX_VERSION, si_has_ngg NGG, si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> +template <amd_gfx_level GFX_VERSION, si_has_ngg NGG, si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw_info *info, unsigned drawid_base, @@ -1812,7 +1812,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw } /* Return false if not bound. */ -template<chip_class GFX_VERSION> +template<amd_gfx_level GFX_VERSION> static bool ALWAYS_INLINE si_set_vb_descriptor(struct si_vertex_elements *velems, struct pipe_vertex_buffer *vb, unsigned index, /* vertex element index */ @@ -1864,7 +1864,7 @@ void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex struct pipe_vertex_buffer *vb, unsigned element_index, uint32_t *out) { - switch (sscreen->info.chip_class) { + switch (sscreen->info.gfx_level) { case GFX6: si_set_vb_descriptor<GFX6>(velems, vb, element_index, out); break; @@ -1887,7 +1887,7 @@ void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex si_set_vb_descriptor<GFX11>(velems, vb, element_index, out); break; default: - unreachable("unhandled chip class"); + unreachable("unhandled gfx level"); } } @@ -1903,7 +1903,7 @@ static ALWAYS_INLINE unsigned get_next_vertex_state_elem(struct pipe_vertex_stat return util_bitcount_fast<POPCNT>(state->input.full_velem_mask & BITFIELD_MASK(semantic_index)); } -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, si_is_draw_vertex_state IS_DRAW_VERTEX_STATE, util_popcnt POPCNT> ALWAYS_INLINE static bool si_upload_and_prefetch_VB_descriptors(struct si_context *sctx, struct pipe_vertex_state *state, @@ -2125,7 +2125,7 @@ static void si_get_draw_start_count(struct si_context *sctx, const struct pipe_d } } -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info, const struct pipe_draw_indirect_info *indirect, @@ -2178,7 +2178,7 @@ static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_i pipe_resource_reference(&indexbuf, NULL); \ } while (0) -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, si_is_draw_vertex_state IS_DRAW_VERTEX_STATE, util_popcnt POPCNT> ALWAYS_INLINE static void si_draw(struct pipe_context *ctx, const struct pipe_draw_info *info, @@ -2638,7 +2638,7 @@ static void si_draw(struct pipe_context *ctx, DRAW_CLEANUP; } -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info, unsigned drawid_offset, @@ -2650,7 +2650,7 @@ static void si_draw_vbo(struct pipe_context *ctx, (ctx, info, drawid_offset, indirect, draws, num_draws, NULL, 0); } -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG, util_popcnt POPCNT> static void si_draw_vertex_state(struct pipe_context *ctx, struct pipe_vertex_state *vstate, @@ -2717,7 +2717,7 @@ static void si_draw_rectangle(struct blitter_context *blitter, void *vertex_elem pipe->draw_vbo(pipe, &info, 0, NULL, &draw, 1); } -template <chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> +template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> static void si_init_draw_vbo(struct si_context *sctx) { if (NGG && GFX_VERSION < GFX10) @@ -2738,7 +2738,7 @@ static void si_init_draw_vbo(struct si_context *sctx) } } -template <chip_class GFX_VERSION> +template <amd_gfx_level GFX_VERSION> static void si_init_draw_vbo_all_pipeline_options(struct si_context *sctx) { si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_OFF, NGG_OFF>(sctx); @@ -2774,7 +2774,7 @@ static void si_invalid_draw_vertex_state(struct pipe_context *ctx, extern "C" void GFX(si_init_draw_functions_)(struct si_context *sctx) { - assert(sctx->chip_class == GFX()); + assert(sctx->gfx_level == GFX()); si_init_draw_vbo_all_pipeline_options<GFX()>(sctx); diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 4ad3d8ca0e4..cf320504e69 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -43,7 +43,7 @@ unsigned si_determine_wave_size(struct si_screen *sscreen, struct si_shader *sha struct si_shader_info *info = shader ? &shader->selector->info : NULL; gl_shader_stage stage = shader ? shader->selector->stage : MESA_SHADER_COMPUTE; - if (sscreen->info.chip_class < GFX10) + if (sscreen->info.gfx_level < GFX10) return 64; /* Legacy GS only supports Wave64. */ @@ -118,7 +118,7 @@ unsigned si_determine_wave_size(struct si_screen *sscreen, struct si_shader *sha * know why this helps. */ if (stage <= MESA_SHADER_GEOMETRY && - !(sscreen->info.chip_class == GFX10 && shader && shader->key.ge.opt.ngg_culling)) + !(sscreen->info.gfx_level == GFX10 && shader && shader->key.ge.opt.ngg_culling)) return 32; /* TODO: Merged shaders must use the same wave size because the driver doesn't recompile @@ -501,7 +501,7 @@ void si_destroy_shader_cache(struct si_screen *sscreen) bool si_shader_mem_ordered(struct si_shader *shader) { - if (shader->selector->screen->info.chip_class < GFX10) + if (shader->selector->screen->info.gfx_level < GFX10) return false; /* Return true if both types of VMEM that return something are used. */ @@ -588,7 +588,7 @@ static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shad static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_shader_selector *sel, struct si_shader *shader) { - if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.chip_class >= GFX10) + if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.gfx_level >= GFX10) return; /* VS as VS, or VS as ES: */ @@ -646,7 +646,7 @@ static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_sha unsigned max = 0; if (shader->info.uses_instanceid) { - if (sscreen->info.chip_class >= GFX10) + if (sscreen->info.gfx_level >= GFX10) max = MAX2(max, 3); else if (is_ls) max = MAX2(max, 2); /* use (InstanceID / StepRate0) because StepRate0 == 1 */ @@ -660,7 +660,7 @@ static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_sha /* GFX11: We prefer to compute RelAutoIndex using (WaveID * WaveSize + ThreadID). * Older chips didn't have WaveID in LS. */ - if (is_ls && sscreen->info.chip_class <= GFX10_3) + if (is_ls && sscreen->info.gfx_level <= GFX10_3) max = MAX2(max, 1); /* RelAutoIndex */ return max; @@ -669,7 +669,7 @@ static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_sha unsigned si_calc_inst_pref_size(struct si_shader *shader) { /* TODO: Disable for now. */ - if (shader->selector->screen->info.chip_class == GFX11) + if (shader->selector->screen->info.gfx_level == GFX11) return 0; /* inst_pref_size is calculated in cache line size granularity */ @@ -682,7 +682,7 @@ static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader) struct si_pm4_state *pm4; uint64_t va; - assert(sscreen->info.chip_class <= GFX8); + assert(sscreen->info.gfx_level <= GFX8); pm4 = si_get_shader_pm4_state(shader); if (!pm4) @@ -711,15 +711,15 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader) va = shader->bo->gpu_address; - if (sscreen->info.chip_class >= GFX9) { - if (sscreen->info.chip_class >= GFX11) { + if (sscreen->info.gfx_level >= GFX9) { + if (sscreen->info.gfx_level >= GFX11) { ac_set_reg_cu_en(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS, S_00B404_INST_PREF_SIZE(si_calc_inst_pref_size(shader)) | S_00B404_CU_EN(0xffff), C_00B404_CU_EN, 16, &sscreen->info, (void (*)(void*, unsigned, uint32_t))si_pm4_set_reg_idx3); } - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); } else { si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8); @@ -730,7 +730,7 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader) shader->config.rsrc2 = S_00B42C_USER_SGPR(num_user_sgprs) | S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); - if (sscreen->info.chip_class >= GFX10) + if (sscreen->info.gfx_level >= GFX10) shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5); else shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5); @@ -746,16 +746,16 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader) si_pm4_set_reg( pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS, S_00B428_VGPRS((shader->config.num_vgprs - 1) / (shader->wave_size == 32 ? 8 : 4)) | - (sscreen->info.chip_class <= GFX9 ? S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) + (sscreen->info.gfx_level <= GFX9 ? S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) | S_00B428_DX10_CLAMP(1) | S_00B428_MEM_ORDERED(si_shader_mem_ordered(shader)) | - S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) | + S_00B428_WGP_MODE(sscreen->info.gfx_level >= GFX10) | S_00B428_FLOAT_MODE(shader->config.float_mode) | - S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 + S_00B428_LS_VGPR_COMP_CNT(sscreen->info.gfx_level >= GFX9 ? si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0)); - if (sscreen->info.chip_class <= GFX8) { + if (sscreen->info.gfx_level <= GFX8) { si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2); } } @@ -790,7 +790,7 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader) uint64_t va; unsigned oc_lds_en; - assert(sscreen->info.chip_class <= GFX8); + assert(sscreen->info.gfx_level <= GFX8); pm4 = si_get_shader_pm4_state(shader); if (!pm4) @@ -956,7 +956,7 @@ static void si_emit_shader_gs(struct si_context *sctx) radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT, shader->ctx_reg.gs.vgt_gs_instance_cnt); - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { /* R_028A44_VGT_GS_ONCHIP_CNTL */ radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL, shader->ctx_reg.gs.vgt_gs_onchip_cntl); @@ -981,30 +981,30 @@ static void si_emit_shader_gs(struct si_context *sctx) /* These don't cause any context rolls. */ if (sctx->screen->info.spi_cu_en_has_effect) { - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { ac_set_reg_cu_en(&sctx->gfx_cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, shader->ctx_reg.gs.spi_shader_pgm_rsrc3_gs, C_00B21C_CU_EN, 0, &sctx->screen->info, (void (*)(void*, unsigned, uint32_t)) - (sctx->chip_class >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); + (sctx->gfx_level >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); sctx->tracked_regs.reg_saved &= ~BITFIELD64_BIT(SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS); } - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { ac_set_reg_cu_en(&sctx->gfx_cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, shader->ctx_reg.gs.spi_shader_pgm_rsrc4_gs, C_00B204_CU_EN_GFX10, 16, &sctx->screen->info, (void (*)(void*, unsigned, uint32_t)) - (sctx->chip_class >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); + (sctx->gfx_level >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); sctx->tracked_regs.reg_saved &= ~BITFIELD64_BIT(SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS); } } else { radeon_begin_again(&sctx->gfx_cs); - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { radeon_opt_set_sh_reg_idx3(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS, shader->ctx_reg.gs.spi_shader_pgm_rsrc3_gs); } - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { radeon_opt_set_sh_reg_idx3(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS, SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS, shader->ctx_reg.gs.spi_shader_pgm_rsrc4_gs); @@ -1023,7 +1023,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) unsigned max_stream = util_last_bit(sel->info.base.gs.active_stream_mask); unsigned offset; - assert(sscreen->info.chip_class < GFX11); /* gfx11 doesn't have the legacy pipeline */ + assert(sscreen->info.gfx_level < GFX11); /* gfx11 doesn't have the legacy pipeline */ pm4 = si_get_shader_pm4_state(shader); if (!pm4) @@ -1064,7 +1064,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) va = shader->bo->gpu_address; - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { unsigned input_prim = sel->info.base.gs.input_primitive; gl_shader_stage es_stage = shader->key.ge.part.gs.es->stage; unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt; @@ -1094,7 +1094,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) else num_user_sgprs = GFX9_GS_NUM_USER_SGPR; - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); } else { si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8); @@ -1102,7 +1102,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) | S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) | - S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) | + S_00B228_WGP_MODE(sscreen->info.gfx_level >= GFX10) | S_00B228_FLOAT_MODE(shader->config.float_mode) | S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) | @@ -1111,7 +1111,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) S_00B22C_LDS_SIZE(shader->config.lds_size) | S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5); } else { rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8); @@ -1124,7 +1124,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) shader->ctx_reg.gs.spi_shader_pgm_rsrc3_gs = S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F); shader->ctx_reg.gs.spi_shader_pgm_rsrc4_gs = - (sscreen->info.chip_class >= GFX11 ? S_00B204_CU_EN_GFX11(1) : S_00B204_CU_EN_GFX10(0xffff)) | + (sscreen->info.gfx_level >= GFX11 ? S_00B204_CU_EN_GFX11(1) : S_00B204_CU_EN_GFX10(0xffff)) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0); shader->ctx_reg.gs.vgt_gs_onchip_cntl = @@ -1189,7 +1189,7 @@ static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader shader->ctx_reg.ngg.ge_ngg_subgrp_cntl); radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN, shader->ctx_reg.ngg.vgt_primitiveid_en); - if (sctx->chip_class < GFX11) { + if (sctx->gfx_level < GFX11) { radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL, shader->ctx_reg.ngg.vgt_gs_onchip_cntl); } @@ -1220,12 +1220,12 @@ static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader shader->ctx_reg.ngg.spi_shader_pgm_rsrc3_gs, C_00B21C_CU_EN, 0, &sctx->screen->info, (void (*)(void*, unsigned, uint32_t)) - (sctx->chip_class >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); + (sctx->gfx_level >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); ac_set_reg_cu_en(&sctx->gfx_cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, shader->ctx_reg.ngg.spi_shader_pgm_rsrc4_gs, C_00B204_CU_EN_GFX10, 16, &sctx->screen->info, (void (*)(void*, unsigned, uint32_t)) - (sctx->chip_class >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); + (sctx->gfx_level >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); sctx->tracked_regs.reg_saved &= ~BITFIELD64_BIT(SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS) & ~BITFIELD64_BIT(SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS); } else { @@ -1420,7 +1420,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) | /* Disable the WGP mode on gfx10.3 because it can hang. (it happened on VanGogh) * Let's disable it on all chips that disable exactly 1 CU per SA for GS. */ - S_00B228_WGP_MODE(sscreen->info.chip_class == GFX10) | + S_00B228_WGP_MODE(sscreen->info.gfx_level == GFX10) | S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt)); si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) | @@ -1432,7 +1432,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader shader->ctx_reg.ngg.spi_shader_pgm_rsrc3_gs = S_00B21C_CU_EN(cu_mask) | S_00B21C_WAVE_LIMIT(0x3F); - if (sscreen->info.chip_class >= GFX11) { + if (sscreen->info.gfx_level >= GFX11) { shader->ctx_reg.ngg.spi_shader_pgm_rsrc4_gs = S_00B204_CU_EN_GFX11(0x1) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64) | S_00B204_INST_PREF_SIZE(si_calc_inst_pref_size(shader)); @@ -1487,7 +1487,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader shader->ctx_reg.ngg.pa_cl_ngg_cntl = S_028838_INDEX_BUF_EDGE_FLAG_ENA(gfx10_edgeflags_have_effect(shader)) | /* Reuse for NGG. */ - S_028838_VERTEX_REUSE_DEPTH(sscreen->info.chip_class >= GFX10_3 ? 30 : 0); + S_028838_VERTEX_REUSE_DEPTH(sscreen->info.gfx_level >= GFX10_3 ? 30 : 0); shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, shader, true); /* Oversubscribe PC. This improves performance when there are too many varyings. */ @@ -1508,7 +1508,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(oversub_pc_lines > 0) | S_030980_NUM_PC_LINES(oversub_pc_lines - 1); - if (sscreen->info.chip_class >= GFX11) { + if (sscreen->info.gfx_level >= GFX11) { shader->ge_cntl = S_03096C_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) | S_03096C_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) | S_03096C_BREAK_PRIMGRP_AT_EOI(break_wave_at_eoi) | @@ -1532,7 +1532,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader * * Tessellation is unaffected because it always sets GE_CNTL.VERT_GRP_SIZE = 0. */ - if ((sscreen->info.chip_class == GFX10) && + if ((sscreen->info.gfx_level == GFX10) && (es_stage == MESA_SHADER_VERTEX || gs_stage == MESA_SHADER_VERTEX) && /* = no tess */ shader->ngg.hw_max_esverts != 256 && shader->ngg.hw_max_esverts > 5) { @@ -1570,7 +1570,7 @@ static void si_emit_shader_vs(struct si_context *sctx) radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN, shader->ctx_reg.vs.vgt_primitiveid_en); - if (sctx->chip_class <= GFX8) { + if (sctx->gfx_level <= GFX8) { radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF, shader->ctx_reg.vs.vgt_reuse_off); } @@ -1595,7 +1595,7 @@ static void si_emit_shader_vs(struct si_context *sctx) shader->vgt_vertex_reuse_block_cntl); /* Required programming for tessellation. (legacy pipeline only) */ - if (sctx->chip_class >= GFX10 && shader->selector->stage == MESA_SHADER_TESS_EVAL) { + if (sctx->gfx_level >= GFX10 && shader->selector->stage == MESA_SHADER_TESS_EVAL) { radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL, S_028A44_ES_VERTS_PER_SUBGRP(250) | @@ -1606,7 +1606,7 @@ static void si_emit_shader_vs(struct si_context *sctx) radeon_end_update_context_roll(sctx); /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */ - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { radeon_begin_again(&sctx->gfx_cs); radeon_opt_set_uconfig_reg(sctx, R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC, shader->ctx_reg.vs.ge_pc_alloc); @@ -1633,7 +1633,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader, info->base.vs.window_space_position : 0; bool enable_prim_id = shader->key.ge.mono.u.vs_export_prim_id || info->uses_primid; - assert(sscreen->info.chip_class < GFX11); + assert(sscreen->info.gfx_level < GFX11); pm4 = si_get_shader_pm4_state(shader); if (!pm4) @@ -1659,11 +1659,11 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader, shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id; } else { shader->ctx_reg.vs.vgt_gs_mode = - ac_vgt_gs_mode(gs->info.base.gs.vertices_out, sscreen->info.chip_class); + ac_vgt_gs_mode(gs->info.base.gs.vertices_out, sscreen->info.gfx_level); shader->ctx_reg.vs.vgt_primitiveid_en = 0; } - if (sscreen->info.chip_class <= GFX8) { + if (sscreen->info.gfx_level <= GFX8) { /* Reuse needs to be set off if we write oViewport. */ shader->ctx_reg.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(info->writes_viewport_index); } @@ -1691,7 +1691,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader, nparams = MAX2(shader->info.nr_param_exports, 1); shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1); - if (sscreen->info.chip_class >= GFX10) { + if (sscreen->info.gfx_level >= GFX10) { shader->ctx_reg.vs.spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0); } @@ -1715,12 +1715,12 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader, oc_lds_en = shader->selector->stage == MESA_SHADER_TESS_EVAL ? 1 : 0; - if (sscreen->info.chip_class >= GFX7) { + if (sscreen->info.gfx_level >= GFX7) { ac_set_reg_cu_en(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(cu_mask) | S_00B118_WAVE_LIMIT(0x3F), C_00B118_CU_EN, 0, &sscreen->info, (void (*)(void*, unsigned, uint32_t)) - (sscreen->info.chip_class >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg)); + (sscreen->info.gfx_level >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg)); si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(late_alloc_wave64)); } @@ -1736,12 +1736,12 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader, uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) | S_00B12C_OC_LDS_EN(oc_lds_en) | S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); - if (sscreen->info.chip_class >= GFX10) + if (sscreen->info.gfx_level >= GFX10) rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5); - else if (sscreen->info.chip_class == GFX9) + else if (sscreen->info.gfx_level == GFX9) rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5); - if (sscreen->info.chip_class <= GFX9) + if (sscreen->info.gfx_level <= GFX9) rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8); if (!sscreen->use_ngg_streamout) { @@ -1920,7 +1920,7 @@ static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader) * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export * instructions if any are present. */ - if ((sscreen->info.chip_class <= GFX9 || info->base.fs.uses_discard || + if ((sscreen->info.gfx_level <= GFX9 || info->base.fs.uses_discard || shader->key.ps.part.epilog.alpha_func != PIPE_FUNC_ALWAYS) && !spi_shader_col_format && !info->writes_z && !info->writes_stencil && !info->writes_samplemask) @@ -1936,7 +1936,7 @@ static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader) S_0286D8_PS_W32_EN(shader->wave_size == 32); /* Workaround when there are no PS inputs but LDS is used. */ - if (sscreen->info.chip_class == GFX11 && !num_interp && shader->config.lds_size) + if (sscreen->info.gfx_level == GFX11 && !num_interp && shader->config.lds_size) spi_ps_in_control |= S_0286D8_PARAM_GEN(1); shader->ctx_reg.ps.num_interp = num_interp; @@ -1957,7 +1957,7 @@ static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader) S_00B028_DX10_CLAMP(1) | S_00B028_MEM_ORDERED(si_shader_mem_ordered(shader)) | S_00B028_FLOAT_MODE(shader->config.float_mode); - if (sscreen->info.chip_class < GFX10) { + if (sscreen->info.gfx_level < GFX10) { rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8); } @@ -1967,7 +1967,7 @@ static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader) S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) | S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0)); - if (sscreen->info.chip_class >= GFX11) { + if (sscreen->info.gfx_level >= GFX11) { unsigned cu_mask_ps = gfx103_get_cu_mask_ps(sscreen); ac_set_reg_cu_en(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS, @@ -2184,7 +2184,7 @@ void si_ps_key_update_framebuffer(struct si_context *sctx) /* 1D textures are allocated and used as 2D on GFX9. */ key->ps.mono.fbfetch_msaa = sctx->framebuffer.nr_samples > 1; key->ps.mono.fbfetch_is_1D = - sctx->chip_class != GFX9 && + sctx->gfx_level != GFX9 && (tex->target == PIPE_TEXTURE_1D || tex->target == PIPE_TEXTURE_1D_ARRAY); key->ps.mono.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY || tex->target == PIPE_TEXTURE_2D_ARRAY || @@ -2220,7 +2220,7 @@ void si_ps_key_update_framebuffer_blend(struct si_context *sctx) sctx->framebuffer.spi_shader_col_format); key->ps.part.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit; - key->ps.part.epilog.dual_src_blend_swizzle = sctx->chip_class >= GFX11 && + key->ps.part.epilog.dual_src_blend_swizzle = sctx->gfx_level >= GFX11 && blend->dual_src_blend && (sel->info.colors_written_4bit & 0xff) == 0xff; @@ -2242,7 +2242,7 @@ void si_ps_key_update_framebuffer_blend(struct si_context *sctx) * to the range supported by the type if a channel has less * than 16 bits and the export format is 16_ABGR. */ - if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) { + if (sctx->gfx_level <= GFX7 && sctx->family != CHIP_HAWAII) { key->ps.part.epilog.color_is_int8 = sctx->framebuffer.color_is_int8; key->ps.part.epilog.color_is_int10 = sctx->framebuffer.color_is_int10; } @@ -2280,7 +2280,7 @@ void si_ps_key_update_blend_rasterizer(struct si_context *sctx) key->ps.part.epilog.alpha_to_one = blend->alpha_to_one && rs->multisample_enable; key->ps.part.epilog.alpha_to_coverage_via_mrtz = - sctx->chip_class >= GFX11 && blend->alpha_to_coverage && rs->multisample_enable && + sctx->gfx_level >= GFX11 && blend->alpha_to_coverage && rs->multisample_enable && (ps->info.writes_z || ps->info.writes_stencil || ps->info.writes_samplemask); } @@ -2405,7 +2405,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_sh si_clear_vs_key_outputs(sctx, sel, key); break; case MESA_SHADER_TESS_CTRL: - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { si_get_vs_key_inputs(sctx, key, &key->ge.part.tcs.ls_prolog); key->ge.part.tcs.ls = sctx->shader.vs.cso; } @@ -2417,7 +2417,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_sh si_clear_vs_key_outputs(sctx, sel, key); break; case MESA_SHADER_GEOMETRY: - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { if (sctx->shader.tes.cso) { si_clear_vs_key_inputs(sctx, key, &key->ge.part.gs.vs_prolog); key->ge.part.gs.es = sctx->shader.tes.cso; @@ -2690,7 +2690,7 @@ current_not_ready: shader->compiler_ctx_state.is_debug_context = sctx->is_debug; /* If this is a merged shader, get the first shader's selector. */ - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { if (sel->stage == MESA_SHADER_TESS_CTRL) previous_stage_sel = ((struct si_shader_key_ge*)key)->part.tcs.ls; else if (sel->stage == MESA_SHADER_GEOMETRY) @@ -3070,7 +3070,7 @@ void si_get_active_slot_masks(struct si_screen *sscreen, const struct si_shader_ * and so we can benefit from a better cache hit rate if we keep image * descriptors together. */ - if (sscreen->info.chip_class < GFX11 && num_msaa_images) + if (sscreen->info.gfx_level < GFX11 && num_msaa_images) num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */ start = si_get_image_slot(num_images - 1) / 2; @@ -3087,7 +3087,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx, if (!sel) return NULL; - if (sscreen->info.chip_class == GFX11 && state->stream_output.num_outputs) { + if (sscreen->info.gfx_level == GFX11 && state->stream_output.num_outputs) { fprintf(stderr, "radeonsi: streamout unimplemented\n"); abort(); } @@ -3134,8 +3134,8 @@ static void *si_create_shader_selector(struct pipe_context *ctx, * - num_invocations * gs.vertices_out > 256 * - LDS usage is too high */ - sel->tess_turns_off_ngg = sscreen->info.chip_class >= GFX10 && - sscreen->info.chip_class <= GFX10_3 && + sel->tess_turns_off_ngg = sscreen->info.gfx_level >= GFX10 && + sscreen->info.gfx_level <= GFX10_3 && (sel->info.base.gs.invocations * sel->info.base.gs.vertices_out > 256 || sel->info.base.gs.invocations * sel->info.base.gs.vertices_out * (sel->info.num_outputs * 4 + 1) > 6500 /* max dw per GS primitive */); @@ -3158,7 +3158,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx, } bool ngg_culling_allowed = - sscreen->info.chip_class >= GFX10 && + sscreen->info.gfx_level >= GFX10 && sscreen->use_ngg_culling && sel->info.writes_position && !sel->info.writes_viewport_index && /* cull only against viewport 0 */ @@ -3362,7 +3362,7 @@ bool si_update_ngg(struct si_context *sctx) */ if (sctx->screen->info.has_vgt_flush_ngg_legacy_bug && !new_ngg) { sctx->flags |= SI_CONTEXT_VGT_FLUSH; - if (sctx->chip_class == GFX10) { + if (sctx->gfx_level == GFX10) { /* Workaround for https://gitlab.freedesktop.org/mesa/mesa/-/issues/2941 */ si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); } @@ -3489,7 +3489,7 @@ void si_update_ps_kill_enable(struct si_context *sctx) void si_update_vrs_flat_shading(struct si_context *sctx) { - if (sctx->chip_class >= GFX10_3 && sctx->shader.ps.cso) { + if (sctx->gfx_level >= GFX10_3 && sctx->shader.ps.cso) { struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; struct si_shader_info *info = &sctx->shader.ps.cso->info; bool allow_flat_shading = info->allow_flat_shading; @@ -3574,10 +3574,10 @@ static void si_delete_shader(struct si_context *sctx, struct si_shader *shader) switch (shader->selector->stage) { case MESA_SHADER_VERTEX: if (shader->key.ge.as_ls) { - if (sctx->chip_class <= GFX8) + if (sctx->gfx_level <= GFX8) state_index = SI_STATE_IDX(ls); } else if (shader->key.ge.as_es) { - if (sctx->chip_class <= GFX8) + if (sctx->gfx_level <= GFX8) state_index = SI_STATE_IDX(es); } else if (shader->key.ge.as_ngg) { state_index = SI_STATE_IDX(gs); @@ -3590,7 +3590,7 @@ static void si_delete_shader(struct si_context *sctx, struct si_shader *shader) break; case MESA_SHADER_TESS_EVAL: if (shader->key.ge.as_es) { - if (sctx->chip_class <= GFX8) + if (sctx->gfx_level <= GFX8) state_index = SI_STATE_IDX(es); } else if (shader->key.ge.as_ngg) { state_index = SI_STATE_IDX(gs); @@ -3703,7 +3703,7 @@ static void si_emit_vgt_flush(struct radeon_cmdbuf *cs) /* Initialize state related to ESGS / GSVS ring buffers */ bool si_update_gs_ring_buffers(struct si_context *sctx) { - assert(sctx->chip_class < GFX11); + assert(sctx->gfx_level < GFX11); struct si_shader_selector *es = sctx->shader.tes.cso ? sctx->shader.tes.cso : sctx->shader.vs.cso; @@ -3717,7 +3717,7 @@ bool si_update_gs_ring_buffers(struct si_context *sctx) /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16. * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2). */ - unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se; + unsigned gs_vertex_reuse = (sctx->gfx_level >= GFX8 ? 32 : 16) * num_se; unsigned alignment = 256 * num_se; /* The maximum size is 63.999 MB per SE. */ unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; @@ -3742,7 +3742,7 @@ bool si_update_gs_ring_buffers(struct si_context *sctx) * * GFX9 doesn't have the ESGS ring. */ - bool update_esgs = sctx->chip_class <= GFX8 && esgs_ring_size && + bool update_esgs = sctx->gfx_level <= GFX8 && esgs_ring_size && (!sctx->esgs_ring || sctx->esgs_ring->width0 < esgs_ring_size); bool update_gsvs = gsvs_ring_size && (!sctx->gsvs_ring || sctx->gsvs_ring->width0 < gsvs_ring_size); @@ -3774,7 +3774,7 @@ bool si_update_gs_ring_buffers(struct si_context *sctx) /* Set ring bindings. */ if (sctx->esgs_ring) { - assert(sctx->chip_class <= GFX8); + assert(sctx->gfx_level <= GFX8); si_set_ring_buffer(sctx, SI_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false, false, 0, 0, 0); } @@ -3787,7 +3787,7 @@ bool si_update_gs_ring_buffers(struct si_context *sctx) /* These registers will be shadowed, so set them only once. */ struct radeon_cmdbuf *cs = &sctx->gfx_cs; - assert(sctx->chip_class >= GFX7); + assert(sctx->gfx_level >= GFX7); si_emit_vgt_flush(cs); @@ -3795,7 +3795,7 @@ bool si_update_gs_ring_buffers(struct si_context *sctx) /* Set the GS registers. */ if (sctx->esgs_ring) { - assert(sctx->chip_class <= GFX8); + assert(sctx->gfx_level <= GFX8); radeon_set_uconfig_reg(R_030900_VGT_ESGS_RING_SIZE, sctx->esgs_ring->width0 / 256); } @@ -3813,9 +3813,9 @@ bool si_update_gs_ring_buffers(struct si_context *sctx) if (!pm4) return false; - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { if (sctx->esgs_ring) { - assert(sctx->chip_class <= GFX8); + assert(sctx->gfx_level <= GFX8); si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE, sctx->esgs_ring->width0 / 256); } if (sctx->gsvs_ring) @@ -3996,7 +3996,7 @@ bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes) si_context_add_resource_size(sctx, &sctx->scratch_buffer->b.b); } - if (sctx->chip_class < GFX11 && !si_update_scratch_relocs(sctx)) + if (sctx->gfx_level < GFX11 && !si_update_scratch_relocs(sctx)) return false; } @@ -4032,7 +4032,7 @@ void si_init_tess_factor_ring(struct si_context *sctx) si_resource(sctx->tess_rings)->gpu_address + sctx->screen->hs.tess_offchip_ring_size; unsigned tf_ring_size_field = sctx->screen->hs.tess_factor_ring_size / 4; - if (sctx->chip_class >= GFX11) + if (sctx->gfx_level >= GFX11) tf_ring_size_field /= sctx->screen->info.max_se; assert((tf_ring_size_field & C_030938_SIZE) == 0); @@ -4042,7 +4042,7 @@ void si_init_tess_factor_ring(struct si_context *sctx) /* TODO: tmz + shadowed_regs support */ struct radeon_cmdbuf *cs = &sctx->gfx_cs; - assert(sctx->chip_class >= GFX7); + assert(sctx->gfx_level >= GFX7); radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(sctx->tess_rings), RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RINGS); @@ -4053,10 +4053,10 @@ void si_init_tess_factor_ring(struct si_context *sctx) radeon_set_uconfig_reg(R_030938_VGT_TF_RING_SIZE, S_030938_SIZE(tf_ring_size_field)); radeon_set_uconfig_reg(R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8); - if (sctx->chip_class >= GFX10) { + if (sctx->gfx_level >= GFX10) { radeon_set_uconfig_reg(R_030984_VGT_TF_MEMORY_BASE_HI, S_030984_BASE_HI(factor_va >> 40)); - } else if (sctx->chip_class == GFX9) { + } else if (sctx->gfx_level == GFX9) { radeon_set_uconfig_reg(R_030944_VGT_TF_MEMORY_BASE_HI, S_030944_BASE_HI(factor_va >> 40)); } @@ -4070,14 +4070,14 @@ void si_init_tess_factor_ring(struct si_context *sctx) si_cs_preamble_add_vgt_flush(sctx); /* Append these registers to the init config state. */ - if (sctx->chip_class >= GFX7) { + if (sctx->gfx_level >= GFX7) { si_pm4_set_reg(sctx->cs_preamble_state, R_030938_VGT_TF_RING_SIZE, S_030938_SIZE(tf_ring_size_field)); si_pm4_set_reg(sctx->cs_preamble_state, R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8); - if (sctx->chip_class >= GFX10) + if (sctx->gfx_level >= GFX10) si_pm4_set_reg(sctx->cs_preamble_state, R_030984_VGT_TF_MEMORY_BASE_HI, S_030984_BASE_HI(factor_va >> 40)); - else if (sctx->chip_class == GFX9) + else if (sctx->gfx_level == GFX9) si_pm4_set_reg(sctx->cs_preamble_state, R_030944_VGT_TF_MEMORY_BASE_HI, S_030944_BASE_HI(factor_va >> 40)); si_pm4_set_reg(sctx->cs_preamble_state, R_03093C_VGT_HS_OFFCHIP_PARAM, @@ -4141,10 +4141,10 @@ struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen, union } else if (key.u.gs) stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); - if (screen->info.chip_class >= GFX9) + if (screen->info.gfx_level >= GFX9) stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2); - if (screen->info.chip_class >= GFX10) { + if (screen->info.gfx_level >= GFX10) { stages |= S_028B54_HS_W32_EN(key.u.hs_wave32) | S_028B54_GS_W32_EN(key.u.gs_wave32) | S_028B54_VS_W32_EN(key.u.vs_wave32); @@ -4161,7 +4161,7 @@ static void si_emit_scratch_state(struct si_context *sctx) struct radeon_cmdbuf *cs = &sctx->gfx_cs; radeon_begin(cs); - if (sctx->chip_class >= GFX11) { + if (sctx->gfx_level >= GFX11) { radeon_set_context_reg_seq(R_0286E8_SPI_TMPRING_SIZE, 3); radeon_emit(sctx->spi_tmpring_size); /* SPI_TMPRING_SIZE */ radeon_emit(sctx->scratch_buffer->gpu_address >> 8); /* SPI_GFX_SCRATCH_BASE_LO */ diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c index baceace822f..464259d2d9c 100644 --- a/src/gallium/drivers/radeonsi/si_state_streamout.c +++ b/src/gallium/drivers/radeonsi/si_state_streamout.c @@ -283,14 +283,14 @@ static void si_flush_vgt_streamout(struct si_context *sctx) radeon_begin(cs); /* The register is at different places on different ASICs. */ - if (sctx->chip_class >= GFX9) { + if (sctx->gfx_level >= GFX9) { reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL; radeon_emit(PKT3(PKT3_WRITE_DATA, 3, 0)); radeon_emit(S_370_DST_SEL(V_370_MEM_MAPPED_REGISTER) | S_370_ENGINE_SEL(V_370_ME)); radeon_emit(R_0300FC_CP_STRMOUT_CNTL >> 2); radeon_emit(0); radeon_emit(0); - } else if (sctx->chip_class >= GFX7) { + } else if (sctx->gfx_level >= GFX7) { reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL; radeon_set_uconfig_reg(reg_strmout_cntl, 0); } else { diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c index a1d38b0b2bd..522d6d43b3a 100644 --- a/src/gallium/drivers/radeonsi/si_state_viewport.c +++ b/src/gallium/drivers/radeonsi/si_state_viewport.c @@ -241,7 +241,7 @@ static void si_emit_one_scissor(struct si_context *ctx, struct radeon_cmdbuf *cs /* Workaround for a hw bug on GFX6 that occurs when PA_SU_HARDWARE_- * SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0. */ - if (ctx->chip_class == GFX6 && (final.maxx == 0 || final.maxy == 0)) { + if (ctx->gfx_level == GFX6 && (final.maxx == 0 || final.maxy == 0)) { radeon_emit(S_028250_TL_X(1) | S_028250_TL_Y(1) | S_028250_WINDOW_OFFSET_DISABLE(1)); radeon_emit(S_028254_BR_X(1) | S_028254_BR_Y(1)); radeon_end(); @@ -290,8 +290,8 @@ static void si_emit_guardband(struct si_context *ctx) /* GFX6-GFX7 need to align the offset to an ubertile consisting of all SEs. */ const unsigned hw_screen_offset_alignment = - ctx->chip_class >= GFX11 ? 32 : - ctx->chip_class >= GFX8 ? 16 : MAX2(ctx->screen->se_tile_repeat, 16); + ctx->gfx_level >= GFX11 ? 32 : + ctx->gfx_level >= GFX8 ? 16 : MAX2(ctx->screen->se_tile_repeat, 16); /* Indexed by quantization modes */ static int max_viewport_size[] = {65535, 16383, 4095}; diff --git a/src/gallium/drivers/radeonsi/si_test_dma_perf.c b/src/gallium/drivers/radeonsi/si_test_dma_perf.c index 3fad2ee688c..9bb07c7ec62 100644 --- a/src/gallium/drivers/radeonsi/si_test_dma_perf.c +++ b/src/gallium/drivers/radeonsi/si_test_dma_perf.c @@ -108,7 +108,7 @@ void si_test_dma_perf(struct si_screen *sscreen) unsigned cs_dwords_per_thread = test_cs ? cs_dwords_per_thread_list[cs_method % NUM_SHADERS] : 0; - if (sctx->chip_class == GFX6) { + if (sctx->gfx_level == GFX6) { /* GFX6 doesn't support CP DMA operations through L2. */ if (test_cp && cache_policy != L2_BYPASS) continue; @@ -120,7 +120,7 @@ void si_test_dma_perf(struct si_screen *sscreen) /* SI_RESOURCE_FLAG_UNCACHED setting RADEON_FLAG_UNCACHED doesn't affect * chips before gfx9. */ - if (test_cs && cache_policy && sctx->chip_class < GFX9) + if (test_cs && cache_policy && sctx->gfx_level < GFX9) continue; printf("%s ,", placement_str[placement]); @@ -331,7 +331,7 @@ void si_test_dma_perf(struct si_screen *sscreen) /* Ban CP DMA clears via MC on <= GFX8. They are super slow * on GTT, which we can get due to BO evictions. */ - if (sctx->chip_class <= GFX8 && placement == 1 && r->is_cp && + if (sctx->gfx_level <= GFX8 && placement == 1 && r->is_cp && r->cache_policy == L2_BYPASS) continue; diff --git a/src/gallium/drivers/radeonsi/si_test_image_copy_region.c b/src/gallium/drivers/radeonsi/si_test_image_copy_region.c index 8865133e11b..0c72a63c3ab 100644 --- a/src/gallium/drivers/radeonsi/si_test_image_copy_region.c +++ b/src/gallium/drivers/radeonsi/si_test_image_copy_region.c @@ -238,7 +238,7 @@ static void print_image_attrs(struct si_screen *sscreen, struct si_texture *tex) { const char *mode; - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { static const char *modes[32] = { [ADDR_SW_LINEAR] = "LINEAR", [ADDR_SW_4KB_S_X] = "4KB_S_X", diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 7b110eeae80..d3bf3ad96fa 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -122,7 +122,7 @@ static unsigned si_texture_get_offset(struct si_screen *sscreen, struct si_textu unsigned level, const struct pipe_box *box, unsigned *stride, unsigned *layer_stride) { - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { unsigned pitch; if (tex->surface.is_linear) { pitch = tex->surface.u.gfx9.pitch[level]; @@ -188,13 +188,13 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac (ptex->bind & PIPE_BIND_SHARED) || is_imported) { flags |= RADEON_SURF_NO_HTILE; } else if (tc_compatible_htile && - (sscreen->info.chip_class >= GFX9 || array_mode == RADEON_SURF_MODE_2D)) { + (sscreen->info.gfx_level >= GFX9 || array_mode == RADEON_SURF_MODE_2D)) { /* TC-compatible HTILE only supports Z32_FLOAT. * GFX9 also supports Z16_UNORM. * On GFX8, promote Z16 to Z32. DB->CB copies will convert * the format for transfers. */ - if (sscreen->info.chip_class == GFX8) + if (sscreen->info.gfx_level == GFX8) bpe = 4; flags |= RADEON_SURF_TC_COMPATIBLE_HTILE; @@ -205,7 +205,7 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac } /* Disable DCC? (it can't be disabled if modifiers are used) */ - if (sscreen->info.chip_class >= GFX8 && modifier == DRM_FORMAT_MOD_INVALID && !is_imported) { + if (sscreen->info.gfx_level >= GFX8 && modifier == DRM_FORMAT_MOD_INVALID && !is_imported) { /* Global options that disable DCC. */ if (ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC) flags |= RADEON_SURF_DISABLE_DCC; @@ -222,11 +222,11 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac flags |= RADEON_SURF_DISABLE_DCC; /* R9G9B9E5 isn't supported for rendering by older generations. */ - if (sscreen->info.chip_class < GFX10_3 && + if (sscreen->info.gfx_level < GFX10_3 && ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT) flags |= RADEON_SURF_DISABLE_DCC; - switch (sscreen->info.chip_class) { + switch (sscreen->info.gfx_level) { case GFX8: /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */ if (sscreen->info.family == CHIP_STONEY && bpe == 16 && ptex->nr_samples >= 2) @@ -276,7 +276,7 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac if (sscreen->debug_flags & DBG(NO_FMASK)) flags |= RADEON_SURF_NO_FMASK; - if (sscreen->info.chip_class == GFX9 && (ptex->flags & SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE)) { + if (sscreen->info.gfx_level == GFX9 && (ptex->flags & SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE)) { flags |= RADEON_SURF_FORCE_MICRO_TILE_MODE; surface->micro_tile_mode = SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex->flags); } @@ -285,11 +285,11 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac /* GFX11 shouldn't get here because the flag is only used by the CB MSAA resolving * that GFX11 doesn't have. */ - assert(sscreen->info.chip_class <= GFX10_3); + assert(sscreen->info.gfx_level <= GFX10_3); flags |= RADEON_SURF_FORCE_SWIZZLE_MODE; - if (sscreen->info.chip_class >= GFX10) + if (sscreen->info.gfx_level >= GFX10) surface->u.gfx9.swizzle_mode = ADDR_SW_64KB_R_X; } @@ -560,7 +560,7 @@ static bool si_displayable_dcc_needs_explicit_flush(struct si_texture *tex) { struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen; - if (sscreen->info.chip_class <= GFX8) + if (sscreen->info.gfx_level <= GFX8) return false; /* With modifiers and > 1 planes any applications will know that they @@ -600,7 +600,7 @@ static bool si_resource_get_param(struct pipe_screen *screen, struct pipe_contex if (resource->target == PIPE_BUFFER) *value = 0; else - *value = ac_surface_get_plane_stride(sscreen->info.chip_class, + *value = ac_surface_get_plane_stride(sscreen->info.gfx_level, &tex->surface, plane, level); return true; @@ -609,7 +609,7 @@ static bool si_resource_get_param(struct pipe_screen *screen, struct pipe_contex *value = 0; } else { uint64_t level_offset = tex->surface.is_linear ? tex->surface.u.gfx9.offset[level] : 0; - *value = ac_surface_get_plane_offset(sscreen->info.chip_class, + *value = ac_surface_get_plane_offset(sscreen->info.gfx_level, &tex->surface, plane, layer) + level_offset; } return true; @@ -692,9 +692,9 @@ static bool si_texture_get_handle(struct pipe_screen *screen, struct pipe_contex return false; if (plane) { - whandle->offset = ac_surface_get_plane_offset(sscreen->info.chip_class, + whandle->offset = ac_surface_get_plane_offset(sscreen->info.gfx_level, &tex->surface, plane, 0); - whandle->stride = ac_surface_get_plane_stride(sscreen->info.chip_class, + whandle->stride = ac_surface_get_plane_stride(sscreen->info.gfx_level, &tex->surface, plane, 0); whandle->modifier = tex->surface.modifier; return sscreen->ws->buffer_get_handle(sscreen->ws, res->buf, whandle); @@ -749,7 +749,7 @@ static bool si_texture_get_handle(struct pipe_screen *screen, struct pipe_contex if ((!res->b.is_shared || update_metadata) && whandle->offset == 0) si_set_tex_bo_metadata(sscreen, tex); - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { slice_size = tex->surface.u.gfx9.surf_slice_size; } else { slice_size = (uint64_t)tex->surface.u.legacy.level[0].slice_size_dw * 4; @@ -846,7 +846,7 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex, u_log_printf(log, "%s", surf_info); free(surf_info); - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { return; } @@ -947,10 +947,10 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, * GFX9 and later use the same tiling for both, so TC-compatible HTILE can be * enabled on demand. */ - tex->tc_compatible_htile = (sscreen->info.chip_class == GFX8 && + tex->tc_compatible_htile = (sscreen->info.gfx_level == GFX8 && tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE) || /* Mipmapping always starts TC-compatible. */ - (sscreen->info.chip_class >= GFX8 && + (sscreen->info.gfx_level >= GFX8 && tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE && tex->buffer.b.b.last_level > 0); @@ -958,7 +958,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, * - GFX8 only supports Z32_FLOAT. * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */ if (tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE) { - if (sscreen->info.chip_class >= GFX9 && base->format == PIPE_FORMAT_Z16_UNORM) + if (sscreen->info.gfx_level >= GFX9 && base->format == PIPE_FORMAT_Z16_UNORM) tex->db_render_format = base->format; else { tex->db_render_format = PIPE_FORMAT_Z32_FLOAT; @@ -980,13 +980,13 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, if (tex->is_depth) { tex->htile_stencil_disabled = !tex->surface.has_stencil; - if (sscreen->info.chip_class >= GFX9) { + if (sscreen->info.gfx_level >= GFX9) { tex->can_sample_z = true; tex->can_sample_s = true; /* Stencil texturing with HTILE doesn't work * with mipmapping on Navi10-14. */ - if (sscreen->info.chip_class == GFX10 && base->last_level > 0) + if (sscreen->info.gfx_level == GFX10 && base->last_level > 0) tex->htile_stencil_disabled = true; } else { tex->can_sample_z = !tex->surface.u.legacy.depth_adjusted; @@ -997,7 +997,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, * because we lose a little bit of Z precision in order to make space for * stencil in HTILE. */ - if (sscreen->info.chip_class == GFX8 && + if (sscreen->info.gfx_level == GFX8 && tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE) tex->htile_stencil_disabled = false; } @@ -1005,7 +1005,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, tex->db_compatible = surface->flags & RADEON_SURF_ZBUFFER; } else { if (tex->surface.cmask_offset) { - assert(sscreen->info.chip_class < GFX11); + assert(sscreen->info.gfx_level < GFX11); tex->cb_color_info |= S_028C70_FAST_CLEAR(1); tex->cmask_buffer = &tex->buffer; } @@ -1057,7 +1057,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, if (tex->is_depth && tex->surface.meta_offset) { uint32_t clear_value = 0; - if (sscreen->info.chip_class >= GFX9 || tex->tc_compatible_htile) + if (sscreen->info.gfx_level >= GFX9 || tex->tc_compatible_htile) clear_value = 0x0000030F; assert(num_clears < ARRAY_SIZE(clears)); @@ -1078,7 +1078,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, assert(num_clears < ARRAY_SIZE(clears)); si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset, tex->surface.meta_size, DCC_CLEAR_0000); - } else if (sscreen->info.chip_class >= GFX9) { + } else if (sscreen->info.gfx_level >= GFX9) { /* Clear to uncompressed. Clearing this to black is complicated. */ assert(num_clears < ARRAY_SIZE(clears)); si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset, @@ -1125,7 +1125,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, assert(num_clears < ARRAY_SIZE(clears)); si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.display_dcc_offset, tex->surface.u.gfx9.color.display_dcc_size, - sscreen->info.chip_class >= GFX11 ? GFX11_DCC_CLEAR_1111_UNORM + sscreen->info.gfx_level >= GFX11 ? GFX11_DCC_CLEAR_1111_UNORM : GFX8_DCC_CLEAR_1111); } @@ -1187,7 +1187,7 @@ static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen, /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8, * which requires 2D tiling. */ - if (sscreen->info.chip_class == GFX8 && tc_compatible_htile) + if (sscreen->info.gfx_level == GFX8 && tc_compatible_htile) return RADEON_SURF_MODE_2D; /* Handle common candidates for the linear mode. @@ -1255,7 +1255,7 @@ si_texture_create_with_modifier(struct pipe_screen *screen, bool is_flushed_depth = templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH || templ->flags & SI_RESOURCE_FLAG_FORCE_LINEAR; bool tc_compatible_htile = - sscreen->info.chip_class >= GFX8 && + sscreen->info.gfx_level >= GFX8 && /* There are issues with TC-compatible HTILE on Tonga (and * Iceland is the same design), and documented bug workarounds * don't help. For example, this fails: @@ -1346,7 +1346,7 @@ bool si_texture_commit(struct si_context *ctx, struct si_resource *res, unsigned unsigned blks = util_format_get_blocksize(format); unsigned samples = MAX2(1, res->b.b.nr_samples); - assert(ctx->chip_class >= GFX9); + assert(ctx->gfx_level >= GFX9); unsigned row_pitch = surface->u.gfx9.prt_level_pitch[level] * surface->prt_tile_height * surface->prt_tile_depth * blks * samples; @@ -1599,9 +1599,9 @@ static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *ssc while (next_plane) { struct si_auxiliary_texture *ptex = (struct si_auxiliary_texture *)next_plane; if (plane >= nplanes || ptex->buffer != tex->buffer.buf || - ptex->offset != ac_surface_get_plane_offset(sscreen->info.chip_class, + ptex->offset != ac_surface_get_plane_offset(sscreen->info.gfx_level, &tex->surface, plane, 0) || - ptex->stride != ac_surface_get_plane_stride(sscreen->info.chip_class, + ptex->stride != ac_surface_get_plane_stride(sscreen->info.gfx_level, &tex->surface, plane, 0)) { si_texture_reference(&tex, NULL); return NULL; @@ -1624,7 +1624,7 @@ static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *ssc return NULL; } - if (ac_surface_get_plane_offset(sscreen->info.chip_class, &tex->surface, 0, 0) + + if (ac_surface_get_plane_offset(sscreen->info.gfx_level, &tex->surface, 0, 0) + tex->surface.total_size > buf->size || buf->alignment_log2 < tex->surface.alignment_log2) { si_texture_reference(&tex, NULL); @@ -2003,7 +2003,7 @@ bool vi_dcc_formats_compatible(struct si_screen *sscreen, enum pipe_format forma const struct util_format_description *desc1, *desc2; /* All formats are compatible on GFX11. */ - if (sscreen->info.chip_class >= GFX11) + if (sscreen->info.gfx_level >= GFX11) return true; /* No format change - exit early. */ @@ -2137,7 +2137,7 @@ static void si_surface_destroy(struct pipe_context *pipe, struct pipe_surface *s FREE(surface); } -unsigned si_translate_colorswap(enum chip_class chip_class, enum pipe_format format, +unsigned si_translate_colorswap(enum amd_gfx_level gfx_level, enum pipe_format format, bool do_endian_swap) { const struct util_format_description *desc = util_format_description(format); @@ -2147,7 +2147,7 @@ unsigned si_translate_colorswap(enum chip_class chip_class, enum pipe_format for if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ return V_028C70_SWAP_STD; - if (chip_class >= GFX10_3 && + if (gfx_level >= GFX10_3 && format == PIPE_FORMAT_R9G9B9E5_FLOAT) /* isn't plain */ return V_028C70_SWAP_STD; @@ -2335,7 +2335,7 @@ static int si_get_sparse_texture_virtual_page_size(struct pipe_screen *screen, * ARB_sparse_texture2 need MS texture support, but we relax it by just return * no page size for GFX10+ to keep shader query capbility. */ - if (multi_sample && sscreen->info.chip_class != GFX9) + if (multi_sample && sscreen->info.gfx_level != GFX9) return 0; /* Unsupport formats. */ @@ -2378,7 +2378,7 @@ void si_init_screen_texture_functions(struct si_screen *sscreen) * which works around some applications using modifiers that are not * allowed in combination with lack of error reporting in * gbm_dri_surface_create */ - if (sscreen->info.chip_class >= GFX9 && sscreen->info.kernel_has_modifiers) { + if (sscreen->info.gfx_level >= GFX9 && sscreen->info.kernel_has_modifiers) { sscreen->b.resource_create_with_modifiers = si_texture_create_with_modifiers; sscreen->b.query_dmabuf_modifiers = si_query_dmabuf_modifiers; sscreen->b.is_dmabuf_modifier_supported = si_is_dmabuf_modifier_supported; diff --git a/src/gallium/drivers/radeonsi/si_uvd.c b/src/gallium/drivers/radeonsi/si_uvd.c index 11436b07350..2a3ccf35dcf 100644 --- a/src/gallium/drivers/radeonsi/si_uvd.c +++ b/src/gallium/drivers/radeonsi/si_uvd.c @@ -93,7 +93,7 @@ static struct pb_buffer *si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_bu struct si_texture *luma = (struct si_texture *)buf->resources[0]; struct si_texture *chroma = (struct si_texture *)buf->resources[1]; enum ruvd_surface_type type = - (sscreen->info.chip_class >= GFX9) ? RUVD_SURFACE_TYPE_GFX9 : RUVD_SURFACE_TYPE_LEGACY; + (sscreen->info.gfx_level >= GFX9) ? RUVD_SURFACE_TYPE_GFX9 : RUVD_SURFACE_TYPE_LEGACY; msg->body.decode.dt_field_mode = buf->base.interlaced; diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index b195da5b772..4d3d269bb17 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -954,7 +954,7 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs, cs->ip_type = ip_type; cs->stop_exec_on_failure = stop_exec_on_failure; cs->noop = ctx->ws->noop_cs; - cs->has_chaining = ctx->ws->info.chip_class >= GFX7 && + cs->has_chaining = ctx->ws->info.gfx_level >= GFX7 && (ip_type == AMD_IP_GFX || ip_type == AMD_IP_COMPUTE); struct amdgpu_cs_fence_info fence_info; @@ -1660,7 +1660,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, /* Pad the IB according to the mask. */ switch (cs->ip_type) { case AMD_IP_SDMA: - if (ws->info.chip_class <= GFX6) { + if (ws->info.gfx_level <= GFX6) { while (rcs->current.cdw & ib_pad_dw_mask) radeon_emit(rcs, 0xf0000000); /* NOP packet */ } else { diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c index 125ee64832a..6ea421fcb6f 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c @@ -60,25 +60,25 @@ static void handle_env_var_force_family(struct amdgpu_winsys *ws) for (i = CHIP_TAHITI; i < CHIP_LAST; i++) { if (!strcmp(family, ac_get_llvm_processor_name(i))) { - /* Override family and chip_class. */ + /* Override family and gfx_level. */ ws->info.family = i; ws->info.name = "NOOP"; strcpy(ws->info.lowercase_name , "noop"); if (i >= CHIP_GFX1100) - ws->info.chip_class = GFX11; + ws->info.gfx_level = GFX11; else if (i >= CHIP_SIENNA_CICHLID) - ws->info.chip_class = GFX10_3; + ws->info.gfx_level = GFX10_3; else if (i >= CHIP_NAVI10) - ws->info.chip_class = GFX10; + ws->info.gfx_level = GFX10; else if (i >= CHIP_VEGA10) - ws->info.chip_class = GFX9; + ws->info.gfx_level = GFX9; else if (i >= CHIP_TONGA) - ws->info.chip_class = GFX8; + ws->info.gfx_level = GFX8; else if (i >= CHIP_BONAIRE) - ws->info.chip_class = GFX7; + ws->info.gfx_level = GFX7; else - ws->info.chip_class = GFX6; + ws->info.gfx_level = GFX6; /* Don't submit any IBs. */ setenv("RADEON_NOOP", "1", 1); diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c index 44e3758955d..9199654ef00 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c @@ -581,7 +581,7 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs, switch (cs->ip_type) { case AMD_IP_SDMA: /* pad DMA ring to 8 DWs */ - if (cs->ws->info.chip_class <= GFX6) { + if (cs->ws->info.gfx_level <= GFX6) { while (rcs->current.cdw & 7) radeon_emit(rcs, 0xf0000000); /* NOP packet */ } else { diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c index c537eb2f3be..a05d5b4c37e 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c @@ -50,14 +50,14 @@ static void set_micro_tile_mode(struct radeon_surf *surf, { uint32_t tile_mode; - if (info->chip_class < GFX6) { + if (info->gfx_level < GFX6) { surf->micro_tile_mode = 0; return; } tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]]; - if (info->chip_class >= GFX7) + if (info->gfx_level >= GFX7) surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode); else surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode); @@ -231,7 +231,7 @@ static void si_compute_cmask(const struct radeon_info *info, if (surf->flags & RADEON_SURF_Z_OR_SBUFFER) return; - assert(info->chip_class <= GFX8); + assert(info->gfx_level <= GFX8); switch (num_pipes) { case 2: @@ -304,7 +304,7 @@ static void si_compute_htile(const struct radeon_info *info, * are always reproducible. I think I have seen the test hang * on Carrizo too, though it was very rare there. */ - if (info->chip_class >= GFX7 && num_pipes < 4) + if (info->gfx_level >= GFX7 && num_pipes < 4) num_pipes = 4; switch (num_pipes) { diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index b32fe09e1ce..76e7e90a12b 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -212,7 +212,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) case CHIP_RS400: case CHIP_RC410: case CHIP_RS480: - ws->info.chip_class = R300; + ws->info.gfx_level = R300; break; case CHIP_R420: /* R4xx-based cores. */ case CHIP_R423: @@ -223,7 +223,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) case CHIP_RS600: case CHIP_RS690: case CHIP_RS740: - ws->info.chip_class = R400; + ws->info.gfx_level = R400; break; case CHIP_RV515: /* R5xx-based cores. */ case CHIP_R520: @@ -231,7 +231,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) case CHIP_R580: case CHIP_RV560: case CHIP_RV570: - ws->info.chip_class = R500; + ws->info.gfx_level = R500; break; case CHIP_R600: case CHIP_RV610: @@ -241,13 +241,13 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) case CHIP_RV635: case CHIP_RS780: case CHIP_RS880: - ws->info.chip_class = R600; + ws->info.gfx_level = R600; break; case CHIP_RV770: case CHIP_RV730: case CHIP_RV710: case CHIP_RV740: - ws->info.chip_class = R700; + ws->info.gfx_level = R700; break; case CHIP_CEDAR: case CHIP_REDWOOD: @@ -260,24 +260,24 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) case CHIP_BARTS: case CHIP_TURKS: case CHIP_CAICOS: - ws->info.chip_class = EVERGREEN; + ws->info.gfx_level = EVERGREEN; break; case CHIP_CAYMAN: case CHIP_ARUBA: - ws->info.chip_class = CAYMAN; + ws->info.gfx_level = CAYMAN; break; case CHIP_TAHITI: case CHIP_PITCAIRN: case CHIP_VERDE: case CHIP_OLAND: case CHIP_HAINAN: - ws->info.chip_class = GFX6; + ws->info.gfx_level = GFX6; break; case CHIP_BONAIRE: case CHIP_KAVERI: case CHIP_KABINI: case CHIP_HAWAII: - ws->info.chip_class = GFX7; + ws->info.gfx_level = GFX7; break; } @@ -308,7 +308,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) /* Check for dma */ ws->info.ip[AMD_IP_SDMA].num_queues = 0; /* DMA is disabled on R700. There is IB corruption and hangs. */ - if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) { + if (ws->info.gfx_level >= EVERGREEN && ws->info.drm_minor >= 27) { ws->info.ip[AMD_IP_SDMA].num_queues = 1; } @@ -419,18 +419,18 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) &tiling_config); ws->info.r600_num_banks = - ws->info.chip_class >= EVERGREEN ? + ws->info.gfx_level >= EVERGREEN ? 4 << ((tiling_config & 0xf0) >> 4) : 4 << ((tiling_config & 0x30) >> 4); ws->info.pipe_interleave_bytes = - ws->info.chip_class >= EVERGREEN ? + ws->info.gfx_level >= EVERGREEN ? 256 << ((tiling_config & 0xf00) >> 8) : 256 << ((tiling_config & 0xc0) >> 6); if (!ws->info.pipe_interleave_bytes) ws->info.pipe_interleave_bytes = - ws->info.chip_class >= EVERGREEN ? 512 : 256; + ws->info.gfx_level >= EVERGREEN ? 512 : 256; radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL, &ws->info.num_tile_pipes); @@ -554,7 +554,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) return false; } - if (ws->info.chip_class == GFX7) { + if (ws->info.gfx_level == GFX7) { if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL, ws->info.cik_macrotile_mode_array)) { fprintf(stderr, "radeon: Kernel 3.13 is required for Sea Islands support.\n"); @@ -562,7 +562,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) } } - if (ws->info.chip_class >= GFX6) { + if (ws->info.gfx_level >= GFX6) { if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL, ws->info.si_tile_mode_array)) { fprintf(stderr, "radeon: Kernel 3.10 is required for Southern Islands support.\n"); @@ -573,14 +573,14 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) /* Hawaii with old firmware needs type2 nop packet. * accel_working2 with value 3 indicates the new firmware. */ - ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= GFX6 || + ws->info.gfx_ib_pad_with_type2 = ws->info.gfx_level <= GFX6 || (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 3); ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */ ws->info.ib_alignment = 4096; ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40; /* HTILE is broken with 1D tiling on old kernels and GFX7. */ - ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != GFX7 || + ws->info.htile_cmask_support_1d_tiling = ws->info.gfx_level != GFX7 || ws->info.drm_minor >= 38; ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48; ws->info.has_bo_metadata = false; @@ -590,15 +590,15 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->info.kernel_flushes_tc_l2_after_ib = true; /* Old kernels disallowed register writes via COPY_DATA * that are used for indirect compute dispatches. */ - ws->info.has_indirect_compute_dispatch = ws->info.chip_class == GFX7 || - (ws->info.chip_class == GFX6 && + ws->info.has_indirect_compute_dispatch = ws->info.gfx_level == GFX7 || + (ws->info.gfx_level == GFX6 && ws->info.drm_minor >= 45); /* GFX6 doesn't support unaligned loads. */ - ws->info.has_unaligned_shader_loads = ws->info.chip_class == GFX7 && + ws->info.has_unaligned_shader_loads = ws->info.gfx_level == GFX7 && ws->info.drm_minor >= 50; ws->info.has_sparse_vm_mappings = false; /* 2D tiling on GFX7 is supported since DRM 2.35.0 */ - ws->info.has_2d_tiling = ws->info.chip_class <= GFX6 || ws->info.drm_minor >= 35; + ws->info.has_2d_tiling = ws->info.gfx_level <= GFX6 || ws->info.drm_minor >= 35; ws->info.has_read_registers_query = ws->info.drm_minor >= 42; ws->info.max_alignment = 1024*1024; ws->info.has_graphics = true; |