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| author | Marek Olšák <marek.olsak@amd.com> | 2017-06-16 21:07:49 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2017-06-19 20:15:36 +0200 |
| commit | 353b60cab53a732cecc978b6f8777f3032ff0fce (patch) | |
| tree | d46ba1b4b107b97176d4805526af956ba65b3dbf | |
| parent | 064f07fef343f517d4bf20f06af9fbb1baea2ff8 (diff) | |
radeonsi/gfx9: disable sparse buffers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index d4e6d42bc21..fda615e30c4 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -548,6 +548,9 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) sscreen->b.info.drm_minor < 50); case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: + /* TODO: GFX9 hangs. */ + if (sscreen->b.chip_class >= GFX9) + return 0; /* Disable on SI due to VM faults in CP DMA. Enable once these * faults are mitigated in software. */ |