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authorTapani Pälli <tapani.palli@intel.com>2014-06-09 12:30:55 +0300
committerMatt Turner <mattst88@gmail.com>2014-06-09 21:08:05 -0700
commit198204c9c5721b1b8d3e0350831ed80b4f19b56d (patch)
tree068d6979518c05cbfe6ee69efec5cef9ee575f4d
parent5cb1cad0aef8d1c426207c955996278290e19e60 (diff)
i965/fs: initialize src as reg_undef for texture opcodes on Gen5/6.
Commit 07af0ab changed fs_inst to have 0 sources for texture opcodes in emit_texture_gen5 (Ironlake, Sandybrige) while fs_generator still uses a single source from brw_reg struct. Patch sets src as reg_undef which matches the behavior before the constructor got changed. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79534
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_visitor.cpp18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 0b4fbb7b00a..30899324048 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1171,21 +1171,21 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
fs_inst *inst = NULL;
switch (ir->op) {
case ir_tex:
- inst = emit(SHADER_OPCODE_TEX, dst);
+ inst = emit(SHADER_OPCODE_TEX, dst, reg_undef);
break;
case ir_txb:
mlen = MAX2(mlen, header_present + 4 * reg_width);
emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
mlen += reg_width;
- inst = emit(FS_OPCODE_TXB, dst);
+ inst = emit(FS_OPCODE_TXB, dst, reg_undef);
break;
case ir_txl:
mlen = MAX2(mlen, header_present + 4 * reg_width);
emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
mlen += reg_width;
- inst = emit(SHADER_OPCODE_TXL, dst);
+ inst = emit(SHADER_OPCODE_TXL, dst, reg_undef);
break;
case ir_txd: {
mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */
@@ -1215,17 +1215,17 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
case ir_txs:
emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
mlen += reg_width;
- inst = emit(SHADER_OPCODE_TXS, dst);
+ inst = emit(SHADER_OPCODE_TXS, dst, reg_undef);
break;
case ir_query_levels:
emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
mlen += reg_width;
- inst = emit(SHADER_OPCODE_TXS, dst);
+ inst = emit(SHADER_OPCODE_TXS, dst, reg_undef);
break;
case ir_txf:
mlen = header_present + 4 * reg_width;
emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), lod));
- inst = emit(SHADER_OPCODE_TXF, dst);
+ inst = emit(SHADER_OPCODE_TXF, dst, reg_undef);
break;
case ir_txf_ms:
mlen = header_present + 4 * reg_width;
@@ -1235,13 +1235,13 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
/* sample index */
emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
mlen += reg_width;
- inst = emit(SHADER_OPCODE_TXF_CMS, dst);
+ inst = emit(SHADER_OPCODE_TXF_CMS, dst, reg_undef);
break;
case ir_lod:
- inst = emit(SHADER_OPCODE_LOD, dst);
+ inst = emit(SHADER_OPCODE_LOD, dst, reg_undef);
break;
case ir_tg4:
- inst = emit(SHADER_OPCODE_TG4, dst);
+ inst = emit(SHADER_OPCODE_TG4, dst, reg_undef);
break;
default:
fail("unrecognized texture opcode");