diff options
| author | Zou Nan hai <nanhai.zou@intel.com> | 2011-03-03 10:30:06 +0800 |
|---|---|---|
| committer | Zou Nan hai <nanhai.zou@intel.com> | 2011-03-03 10:30:06 +0800 |
| commit | 118ecb1a2226494929a87c36b7802b64451ca004 (patch) | |
| tree | eca786bce75256c9f44cc98a010d61e77c1868df | |
| parent | 2e756f3d6f15d61297a3bb4efe6a88c29081a5eb (diff) | |
i965: SNB GT1 has only 32k urb and max 128 urb entries.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_urb.c | 19 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_chipset.h | 4 |
2 files changed, 19 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c index 57be50a4451..c3819f9b360 100644 --- a/src/mesa/drivers/dri/i965/gen6_urb.c +++ b/src/mesa/drivers/dri/i965/gen6_urb.c @@ -34,15 +34,26 @@ static void prepare_urb( struct brw_context *brw ) { - brw->urb.nr_vs_entries = 256; - brw->urb.nr_gs_entries = 256; + int urb_size, max_urb_entry; + struct intel_context *intel = &brw->intel; + + if (IS_GT1(intel->intelScreen->deviceID)) { + urb_size = 32 * 1024; + max_urb_entry = 128; + } else { + urb_size = 64 * 1024; + max_urb_entry = 256; + } + + brw->urb.nr_vs_entries = max_urb_entry; + brw->urb.nr_gs_entries = max_urb_entry; /* CACHE_NEW_VS_PROG */ brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1); - if (256 * brw->urb.vs_size > 64 * 1024) + if (2 * brw->urb.vs_size > urb_size) brw->urb.nr_vs_entries = brw->urb.nr_gs_entries = - (64 * 1024 ) / brw->urb.vs_size; + (urb_size ) / (2 * brw->urb.vs_size); } static void diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 4fecdbed203..4ff9140d56e 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -133,6 +133,10 @@ devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \ devid == PCI_CHIP_SANDYBRIDGE_S) +#define IS_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \ + devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \ + devid == PCI_CHIP_SANDYBRIDGE_S) + #define IS_965(devid) (IS_GEN4(devid) || \ IS_G4X(devid) || \ IS_GEN5(devid) || \ |