diff options
author | Kenneth Graunke <kenneth@whitecape.org> | 2023-01-10 14:02:06 -0800 |
---|---|---|
committer | Marge Bot <emma+marge@anholt.net> | 2023-01-12 21:48:40 +0000 |
commit | ebdf6a79266b2b2249b549707fcdbaf9eae905ce (patch) | |
tree | 7eda0bb94197455a3f67dcdb4bb61ecaeb9efe94 | |
parent | 18e91ad329102d821f06ee3f874067b4d97d05e2 (diff) |
intel/genxml: Drop CACHE_MODE_SS definition.23.0-branchpoint
This is a global register which isn't settable by userspace contexts.
It also shouldn't appear in any of our aubinator decodes from error
states or aub dumps, as no userspace batch should be setting it.
So it's not very valuable to have here. Just makes us think we can
set it. Plus, a lot of the field definitions changed a bunch, and
would need updating.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20627>
-rw-r--r-- | src/intel/genxml/gen11.xml | 12 | ||||
-rw-r--r-- | src/intel/genxml/gen12.xml | 10 | ||||
-rw-r--r-- | src/intel/genxml/gen125.xml | 10 |
3 files changed, 1 insertions, 31 deletions
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 97f66495290..3450f821c6f 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -6649,16 +6649,6 @@ <field name="Blend Optimization Fix Disable Mask" start="30" end="30" type="bool" /> <field name="Color Compression Disable Mask" start="31" end="31" type="bool" /> </register> - <register name="CACHE_MODE_SS" length="1" num="0x0e420"> - <field name="Instruction Level 1 Cache Disable" start="0" end="0" type="bool" /> - <field name="Instruction Level 1 Cache and In-Flight Queue Disable " start="1" end="1" type="bool" /> - <field name="Float Blend Optimization Enable" start="4" end="4" type="bool" /> - <field name="Per Sample Blend Opt Disable" start="11" end="11" type="bool" /> - <field name="Instruction Level 1 Cache Disable Mask" start="16" end="16" type="bool" /> - <field name="Instruction Level 1 Cache and In-Flight Queue Disable Mask" start="17" end="17" type="bool" /> - <field name="Float Blend Optimization Enable Mask" start="20" end="20" type="bool" /> - <field name="Per Sample Blend Opt Disable Mask" start="27" end="27" type="bool" /> - </register> <register name="CL_INVOCATION_COUNT" length="2" num="0x2338"> <field name="CL Invocation Count Report" start="0" end="63" type="uint" /> </register> @@ -6930,4 +6920,4 @@ <register name="VS_INVOCATION_COUNT" length="2" num="0x2320"> <field name="VS Invocation Count Report" start="0" end="63" type="uint" /> </register> -</genxml>
\ No newline at end of file +</genxml> diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index c4c0b99bfdb..5f0858e1dfd 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -6898,16 +6898,6 @@ <field name="Blend Optimization Fix Disable Mask" start="30" end="30" type="bool" /> <field name="Color Compression Disable Mask" start="31" end="31" type="bool" /> </register> - <register name="CACHE_MODE_SS" length="1" num="0x0e420"> - <field name="Instruction Level 1 Cache Disable" start="0" end="0" type="bool" /> - <field name="Instruction Level 1 Cache and In-Flight Queue Disable " start="1" end="1" type="bool" /> - <field name="Float Blend Optimization Enable" start="4" end="4" type="bool" /> - <field name="Per Sample Blend Opt Disable" start="11" end="11" type="bool" /> - <field name="Instruction Level 1 Cache Disable Mask" start="16" end="16" type="bool" /> - <field name="Instruction Level 1 Cache and In-Flight Queue Disable Mask" start="17" end="17" type="bool" /> - <field name="Float Blend Optimization Enable Mask" start="20" end="20" type="bool" /> - <field name="Per Sample Blend Opt Disable Mask" start="27" end="27" type="bool" /> - </register> <register name="CL_INVOCATION_COUNT" length="2" num="0x2338"> <field name="CL Invocation Count Report" start="0" end="63" type="uint" /> </register> diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml index d8ab604cc71..d8ed8c90b08 100644 --- a/src/intel/genxml/gen125.xml +++ b/src/intel/genxml/gen125.xml @@ -7376,16 +7376,6 @@ <field name="Blend Optimization Fix Disable Mask" start="30" end="30" type="bool" /> <field name="Color Compression Disable Mask" start="31" end="31" type="bool" /> </register> - <register name="CACHE_MODE_SS" length="1" num="0x0e420"> - <field name="Instruction Level 1 Cache Disable" start="0" end="0" type="bool" /> - <field name="Instruction Level 1 Cache and In-Flight Queue Disable " start="1" end="1" type="bool" /> - <field name="Float Blend Optimization Enable" start="4" end="4" type="bool" /> - <field name="Per Sample Blend Opt Disable" start="11" end="11" type="bool" /> - <field name="Instruction Level 1 Cache Disable Mask" start="16" end="16" type="bool" /> - <field name="Instruction Level 1 Cache and In-Flight Queue Disable Mask" start="17" end="17" type="bool" /> - <field name="Float Blend Optimization Enable Mask" start="20" end="20" type="bool" /> - <field name="Per Sample Blend Opt Disable Mask" start="27" end="27" type="bool" /> - </register> <register name="CHICKEN_RASTER_1" length="1" num="0x6204"> <field name="AA Line Quality Fix" start="5" end="5" type="bool" /> <field name="AA Line Quality Fix Mask" start="21" end="21" type="bool" /> |