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path: root/drivers/gpu/drm/i915/intel_dpll_mgr.c
AgeCommit message (Expand)AuthorFilesLines
2019-06-17drm/i915: move modesetting core code under display/Jani Nikula1-3359/+0
2019-06-12drm/i915: Rename HSW/BDW PLL bitsVille Syrjälä1-2/+2
2019-06-04drm/i915: Make state dumpers take a const stateVille Syrjälä1-8/+8
2019-05-14drm/i915: Replace use of PLLS power domain with DISPLAY_CORE domainImre Deak1-18/+18
2019-05-06drm/i915: Replace intel_ddi_pll_init()Ville Syrjälä1-25/+0
2019-05-03drm/i915: Use mul_u32_u32() moreVille Syrjälä1-2/+2
2019-05-03drm/i915: extract intel_dpio_phy.h from i915_drv.hJani Nikula1-0/+1
2019-04-30drm/i915: make intel_dpll_mgr.h self-containedJani Nikula1-0/+1
2019-03-26drm/i915: switch intel_wait_for_register to uncoreDaniele Ceraolo Spurio1-12/+13
2019-03-22drm/i915/ehl: Add dpll mgrLucas De Marchi1-1/+15
2019-03-19drm/i915: Remove the fragile array index -> link rate mappingVille Syrjälä1-68/+68
2019-03-19drm/i915: Nuke icl_calc_dp_combo_pll_link()Ville Syrjälä1-70/+0
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from icl_get_dpll()Ville Syrjälä1-18/+17
2019-03-19drm/i915: Pass crtc_state down to icl dpll funcsVille Syrjälä1-4/+8
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from cnl_get_dpll()Ville Syrjälä1-8/+7
2019-03-19drm/i915: Pass crtc_state down to cnl dpll funcsVille Syrjälä1-17/+12
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from bxt_get_dpll()Ville Syrjälä1-16/+10
2019-03-19drm/i915: Pass crtc_state down to bxt dpll funcsVille Syrjälä1-23/+25
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from skl_get_dpll()Ville Syrjälä1-8/+7
2019-03-19drm/i915: Pass crtc_state down to skl dpll funcsVille Syrjälä1-10/+7
2019-03-19drm/i915: Don't pass crtc to intel_get_shared_dpll() and .get_dpll()Ville Syrjälä1-29/+27
2019-03-19drm/i915: Don't pass crtc to intel_find_shared_dpll()Ville Syrjälä1-9/+9
2019-03-15drm/i915/icl: remove intel_dpll_is_combophy()Lucas De Marchi1-5/+0
2019-03-15drm/i915/icl: split combo and tbt pll funcsLucas De Marchi1-20/+54
2019-03-15drm/i915/icl: split combo and mg pll disableLucas De Marchi1-7/+23
2019-03-15drm/i915/icl: split pll enable in three stepsLucas De Marchi1-19/+37
2019-03-15drm/i915/icl: split combo and mg pll enableLucas De Marchi1-4/+21
2019-03-13drm/i915/gen11+: First assume next platforms will inherit stuffRodrigo Vivi1-1/+1
2019-03-01drm/i915/icl: move MG pll hw_state readoutLucas De Marchi1-48/+74
2019-01-31drm/i915: Pick the first unused PLL once againVille Syrjälä1-1/+2
2019-01-29drm/i915/icl: keep track of unused pll while loopingLucas De Marchi1-10/+9
2019-01-29drm/i915/icl: use tc_port in MG_PLL macrosLucas De Marchi1-40/+39
2019-01-17drm/i915/dpll_mgr: switch to kernel typesJani Nikula1-72/+73
2019-01-14drm/i915: Markup paired operations on display power domainsChris Wilson1-21/+45
2018-12-03drm/i915/icl: Calculate DPLL params for DSIMadhav Chauhan1-1/+2
2018-10-31drm/i915/icl: Fix crash when getting DPLL of a MST encoder in TC portsJosé Roberto de Souza1-2/+10
2018-10-16drm/i915/icl: Refactor icl pll functionsVandita Kulkarni1-37/+17
2018-10-16drm/i915/icl: Use helper functions to classify the portsVandita Kulkarni1-10/+4
2018-10-16drm/i915/icl: Refactor get_ddi_pll using helper funcVandita Kulkarni1-1/+1
2018-10-08drm/i915: Fixup kernel doc for param name changesChris Wilson1-3/+3
2018-10-05drm/i915: Make shared dpll functions take crtc_state, v3.Maarten Lankhorst1-18/+11
2018-09-04drm/i915: Fix ICL+ HDMI clock readoutVille Syrjälä1-8/+15
2018-08-20drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separa...Manasi Navare1-6/+7
2018-07-27drm/i915/icl: Add TBT checks for PLL calculationsAnusha Srivatsa1-1/+3
2018-07-23Merge drm/drm-next into drm-intel-next-queuedRodrigo Vivi1-3/+3
2018-07-19drm/i915/icl: compute the TBT PLL registersPaulo Zanoni1-1/+21
2018-07-19Merge tag 'drm-intel-next-2018-07-09' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-24/+85
2018-07-05drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva1-0/+3
2018-07-02drm/i915: Use drm_plane_mask() & co.Ville Syrjälä1-3/+3
2018-06-21drm/i915/icl: Do read-modify-write as needed during MG PLL programmingImre Deak1-4/+35
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