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authorDnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>2025-09-22 20:33:17 +0530
committerSuraj Kandpal <suraj.kandpal@intel.com>2025-09-23 21:44:34 +0530
commit8147f7a1c083fd565fb958824f7c552de3b2dc46 (patch)
treec6adf18d23c0e204f917b6a9e23a2569c477448c /arch/x86/kernel/cpu/hygon.c
parent4dfaae643e59cf3ab71b88689dce1b874f036f00 (diff)
drm/i915/xe3: Restrict PTL intel_encoder_is_c10phy() to only PHY A
On PTL, no combo PHY is connected to PORT B. However, PORT B can still be used for Type-C and will utilize the C20 PHY for eDP over Type-C. In such configurations, VBTs also enumerate PORT B. This leads to issues where PORT B is incorrectly identified as using the C10 PHY, due to the assumption that returning true for PORT B in intel_encoder_is_c10phy() would not cause problems. From PTL's perspective, only PORT A/PHY A uses the C10 PHY. Update the helper intel_encoder_is_c10phy() to return true only for PORT A/PHY on PTL. v2: Change the condition code style for ptl/wcl Bspec: 72571,73944 Fixes: 9d10de78a37f ("drm/i915/wcl: C10 phy connected to port A and B") Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250922150317.2334680-4-dnyaneshwar.bhadane@intel.com
Diffstat (limited to 'arch/x86/kernel/cpu/hygon.c')
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