diff options
| author | Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> | 2025-06-14 01:01:45 +0530 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2025-06-18 14:59:39 -0700 |
| commit | 9d10de78a37f4f397de7662faa0c8ab54b6171c9 (patch) | |
| tree | c2c8e51b8eae2567e8af11deaa38c74f4e2b3c40 /arch/x86/kernel/cpu | |
| parent | 3d77a3280da9ef96e2f8281e43b2cec18f142160 (diff) | |
drm/i915/wcl: C10 phy connected to port A and B
WCL added a c10 phy connected to port B. PTL code is currently
restricting c10 to phy_a only.
PTL doesn't have a PHY connected to PORT B; as such,there will
never be a case where PTL uses PHY B.
WCL uses PORT A and B with the C10 PHY.Reusing the condition
for WCL and extending it for PORT B should not cause any issues
for PTL.
-v2: Reuse and extend PTL condition for WCL (Matt)
Bspec: 73944
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20250613193146.3549862-9-dnyaneshwar.bhadane@intel.com
Diffstat (limited to 'arch/x86/kernel/cpu')
0 files changed, 0 insertions, 0 deletions