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path: root/drivers/gpu/drm/i915/display/intel_dpio_phy.c
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2024-04-30drm/i915/dpio: Extract vlv_dpio_phy_regs.hdrm-intel-next-2024-04-30Ville Syrjälä1-0/+1
2024-04-30drm/i915/dpio: Clean up the vlv/chv PHY register bitsVille Syrjälä1-31/+28
2024-04-30drm/i915/dpio: Clean up VLV/CHV DPIO PHY register definesVille Syrjälä1-1/+1
2024-04-30drm/i915/dpio: Rename a few CHV DPIO PHY registersVille Syrjälä1-8/+8
2024-04-30drm/i915/dpio: Give VLV DPIO group register a clearer nameVille Syrjälä1-17/+17
2024-04-30drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooksVille Syrjälä1-16/+11
2024-04-30drm/i915/dpio: s/port/ch/Ville Syrjälä1-22/+22
2024-04-30drm/i915/dpio: Remove pointless VLV_PCS01_DW8 readVille Syrjälä1-1/+0
2024-04-19drm/i915/dpio: Program bxt/glk PHY TX registers per-laneVille Syrjälä1-13/+22
2024-04-19drm/i915/dpio: s/ddi/dpio/ for bxt/glk PHY stuffVille Syrjälä1-63/+63
2024-04-19drm/i915/dpio: Use intel_de_rmw() for BXT DPIO latency optim setupVille Syrjälä1-9/+3
2024-04-19drm/i915/dpio: Introdude bxt_ddi_phy_rmw_grp()Ville Syrjälä1-22/+39
2024-04-19drm/i915/dpio: Extract bxt_dpio_phy_regs.hVille Syrjälä1-0/+1
2024-04-19drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glkVille Syrjälä1-3/+3
2024-04-19drm/i915/dpio: Clean up bxt/glk PHY registersVille Syrjälä1-22/+22
2024-03-26drm/i915/display: prefer intel_de_wait*() functions over uncore onesJani Nikula1-5/+2
2023-11-17drm/i915: convert vlv_dpio_read()/write() from pipe to phyJani Nikula1-77/+80
2023-11-17drm/i915: add vlv_pipe_to_phy() helper to replace DPIO_PHY()Jani Nikula1-0/+14
2023-02-16drm/i915/display/phys: use intel_de_rmw if possibleAndrzej Hajda1-35/+16
2023-01-18drm/i915: move chv_dpll_md and bxt_phy_grc to display sub-struct under stateJani Nikula1-4/+5
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula1-0/+1
2022-11-03drm/i915/dpio: un-inline the vlv phy/channel mapping functionsJani Nikula1-0/+42
2022-08-31drm/i915: move and group power related members under display.powerJani Nikula1-1/+1
2022-04-20drm/i915: Move per-platform power well hooks to intel_display_power_well.cImre Deak1-0/+1
2021-10-14drm/i915: split out vlv sideband to a separate fileJani Nikula1-3/+2
2021-10-04drm/i915: Pass the lane to intel_ddi_level()Ville Syrjälä1-1/+1
2021-10-04drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level()Ville Syrjälä1-2/+0
2021-10-04drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels()Ville Syrjälä1-9/+21
2021-05-05drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä1-0/+1
2020-10-01drm/i915: Plumb crtc_state to link trainingVille Syrjälä1-11/+12
2020-07-02drm/i915/display: prefer dig_port to reference intel_digital_portLucas De Marchi1-19/+19
2020-02-11drm/i915/dpio_phy: convert to drm_device based logging macros.Wambui Karuga1-12/+16
2020-02-04drm/i915/display: Make WARN* drm specific where drm_device ptr is availablePankaj Bharadiya1-1/+2
2020-01-27drm/i915/dpio_phy: use intel_de_*() functions for register accessJani Nikula1-37/+40
2020-01-13drm/i915: Pass intel_encoder to enc_to_*()Ville Syrjälä1-9/+9
2019-11-01drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.Maarten Lankhorst1-7/+7
2019-08-16drm/i915: Wrappers for display register waitsDaniele Ceraolo Spurio1-4/+2
2019-08-07drm/i915: rename intel_drv.h to display/intel_display_types.hJani Nikula1-1/+1
2019-06-17drm/i915: move modesetting core code under display/Jani Nikula1-0/+1088
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