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-rw-r--r--backend/src/backend/gen_context.cpp6
-rw-r--r--backend/src/backend/gen_encoder.cpp13
-rw-r--r--backend/src/backend/gen_encoder.hpp3
-rw-r--r--backend/src/backend/gen_insn_selection.cpp2
4 files changed, 23 insertions, 1 deletions
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 43fa7fa0..a9f6fab3 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -94,6 +94,10 @@ namespace gbe
return i;
}
+ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
+#define SET_GENINSN_DBGINFO(I) \
+ if(OCL_DEBUGINFO) p->DBGInfo = I.DBGInfo;
+
void GenContext::emitInstructionStream(void) {
// Emit Gen ISA
for (auto &block : *sel->blockList)
@@ -103,6 +107,7 @@ namespace gbe
// no more virtual register here in that part of the code generation
GBE_ASSERT(insn.state.physicalFlag);
p->curr = insn.state;
+ SET_GENINSN_DBGINFO(insn);
switch (opcode) {
#define DECL_SELECTION_IR(OPCODE, FAMILY) \
case SEL_OP_##OPCODE: this->emit##FAMILY(insn); break;
@@ -116,6 +121,7 @@ namespace gbe
for(int i = 0; i < 8; i++)
p->NOP();
}
+#undef SET_GENINSN_DBGINFO
bool GenContext::patchBranches(void) {
using namespace ir;
diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index 7c4357ab..b8ea736c 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -591,11 +591,23 @@ namespace gbe
this->setSrc1(insn, bti);
}
}
+
+ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
+ void GenEncoder::setDBGInfo(DebugInfo in, bool hasHigh)
+ {
+ if(OCL_DEBUGINFO)
+ {
+ storedbg.push_back(in);
+ if(hasHigh) storedbg.push_back(in);
+ }
+ }
+
GenCompactInstruction *GenEncoder::nextCompact(uint32_t opcode) {
GenCompactInstruction insn;
std::memset(&insn, 0, sizeof(GenCompactInstruction));
insn.bits1.opcode = opcode;
this->store.push_back(insn.low);
+ setDBGInfo(DBGInfo, false);
return (GenCompactInstruction *)&this->store.back();
}
@@ -605,6 +617,7 @@ namespace gbe
insn.header.opcode = opcode;
this->store.push_back(insn.low);
this->store.push_back(insn.high);
+ setDBGInfo(DBGInfo, true);
return (GenNativeInstruction *)(&this->store.back()-1);
}
diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
index e4f5ff4a..503577fd 100644
--- a/backend/src/backend/gen_encoder.hpp
+++ b/backend/src/backend/gen_encoder.hpp
@@ -88,6 +88,9 @@ namespace gbe
uint32_t deviceID;
/*! simd width for this codegen */
uint32_t simdWidth;
+ DebugInfo DBGInfo;
+ vector<DebugInfo> storedbg;
+ void setDBGInfo(DebugInfo in, bool hasHigh);
////////////////////////////////////////////////////////////////////////
// Encoding functions
////////////////////////////////////////////////////////////////////////
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 32d05d3a..cd7b2ebd 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -2069,7 +2069,7 @@ namespace gbe
extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
#define SET_SEL_DBGINFO(I) \
if(OCL_DEBUGINFO) \
- sel.setDBGInfo_SEL(I.DBGInfo)
+ this->setDBGInfo_SEL(I.DBGInfo)
void Selection::Opaque::matchBasicBlock(const ir::BasicBlock &bb, uint32_t insnNum)
{