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| author | Zhigang Gong <zhigang.gong@intel.com> | 2014-03-28 14:57:51 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-04-08 16:21:33 +0800 |
| commit | 4350a22d881858dfa308a6f5623e5a7211a58a28 (patch) | |
| tree | 1a30ab39e7ef4aafa4d9f127c5ad56ccc5767f1e /backend/src/backend/gen_insn_selection.cpp | |
| parent | d1290292be2c55fef20d85eb8d72bee0fc818360 (diff) | |
Silent some compilation warnings.
Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Yang, Rong R" <rong.r.yang@intel.com>
Reviewed-by: "Song, Ruiling" <ruiling.song@intel.com>
Diffstat (limited to 'backend/src/backend/gen_insn_selection.cpp')
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index a26aed7f..aec04594 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -2939,7 +2939,6 @@ namespace gbe markAllChildren(dag); } - const uint32_t simdWidth = sel.ctx.getSimdWidth(); const Register pred = insn.getPredicate(); sel.push(); sel.curr.predicate = GEN_PREDICATE_NONE; |