diff options
author | Luo Xionghu <xionghu.luo@intel.com> | 2016-01-05 10:28:04 -0500 |
---|---|---|
committer | Yang Rong <rong.r.yang@intel.com> | 2016-11-08 20:38:21 +0800 |
commit | 8508700d3be4407208d3e7fa7c9765a7563ed13d (patch) | |
tree | 65886754580a232b1e55a2439a25d298e6cfbdf3 | |
parent | 28ac589ad44a482830ca9372e77f5480039bfdec (diff) |
add atomic operators output for GEN_IR and gen disa.
the function types of atomic instruction are useful for analyzing the gen
ir and disassembly.
Signed-off-by: Luo Xionghu <xionghu.luo@intel.com>
Reviewed-by: Ruiling Song <ruiling.song@intel.com>
-rw-r--r-- | backend/src/backend/gen/gen_mesa_disasm.c | 45 | ||||
-rw-r--r-- | backend/src/ir/instruction.cpp | 25 |
2 files changed, 65 insertions, 5 deletions
diff --git a/backend/src/backend/gen/gen_mesa_disasm.c b/backend/src/backend/gen/gen_mesa_disasm.c index 56532755..ecda1aca 100644 --- a/backend/src/backend/gen/gen_mesa_disasm.c +++ b/backend/src/backend/gen/gen_mesa_disasm.c @@ -495,6 +495,24 @@ static const char *data_port1_data_cache_msg_type[] = { [13] = "Typed Surface Write", }; +static const char *atomic_opration_type[] = { + [1] = "and", + [2] = "or", + [3] = "xor", + [4] = "xchg", + [5] = "inc", + [6] = "dec", + [7] = "add", + [8] = "sub", + [9] = "rsub", + [10] = "imax", + [11] = "imin", + [12] = "umax", + [13] = "umin", + [14] = "cmpxchg", + [15] = "invalid" +}; + static int column; static int gen_version; @@ -573,6 +591,7 @@ static int gen_version; #define UNTYPED_RW_MSG_TYPE(inst) GEN_BITS_FIELD(inst, bits3.gen7_untyped_rw.msg_type) #define BYTE_RW_SIMD_MODE(inst) GEN_BITS_FIELD(inst, bits3.gen7_byte_rw.simd_mode) #define BYTE_RW_DATA_SIZE(inst) GEN_BITS_FIELD(inst, bits3.gen7_byte_rw.data_size) +#define UNTYPED_RW_AOP_TYPE(inst) GEN_BITS_FIELD(inst, bits3.gen7_atomic_op.aop_type) #define SCRATCH_RW_OFFSET(inst) GEN_BITS_FIELD(inst, bits3.gen7_scratch_rw.offset) #define SCRATCH_RW_BLOCK_SIZE(inst) GEN_BITS_FIELD(inst, bits3.gen7_scratch_rw.block_size) #define SCRATCH_RW_INVALIDATE_AFTER_READ(inst) GEN_BITS_FIELD(inst, bits3.gen7_scratch_rw.invalidate_after_read) @@ -1509,6 +1528,14 @@ int gen_disasm (FILE *file, const void *inst, uint32_t deviceID, uint32_t compac data_port_data_cache_block_size[OWORD_RW_BLOCK_SIZE(inst)], data_port_data_cache_category[UNTYPED_RW_CATEGORY(inst)], data_port_data_cache_msg_type[UNTYPED_RW_MSG_TYPE(inst)]); + else if(UNTYPED_RW_MSG_TYPE(inst) == 6) + format(file, " (bti: %d, rgba: %d, %s, %s, %s, %s)", + UNTYPED_RW_BTI(inst), + UNTYPED_RW_RGBA(inst), + data_port_data_cache_simd_mode[UNTYPED_RW_SIMD_MODE(inst)], + data_port_data_cache_category[UNTYPED_RW_CATEGORY(inst)], + data_port_data_cache_msg_type[UNTYPED_RW_MSG_TYPE(inst)], + atomic_opration_type[UNTYPED_RW_AOP_TYPE(inst)]); else format(file, " not implemented"); } else { @@ -1526,13 +1553,21 @@ int gen_disasm (FILE *file, const void *inst, uint32_t deviceID, uint32_t compac UNTYPED_RW_BTI(inst), data_port_data_cache_category[UNTYPED_RW_CATEGORY(inst)], data_port1_data_cache_msg_type[UNTYPED_RW_MSG_TYPE(inst)]); + else if(UNTYPED_RW_MSG_TYPE(inst) == 2) + format(file, " (bti: %d, rgba: %d, %s, %s, %s, %s)", + UNTYPED_RW_BTI(inst), + UNTYPED_RW_RGBA(inst), + data_port_data_cache_simd_mode[UNTYPED_RW_SIMD_MODE(inst)], + data_port_data_cache_category[UNTYPED_RW_CATEGORY(inst)], + data_port1_data_cache_msg_type[UNTYPED_RW_MSG_TYPE(inst)], + atomic_opration_type[UNTYPED_RW_AOP_TYPE(inst)]); else format(file, " (bti: %d, rgba: %d, %s, %s, %s)", - UNTYPED_RW_BTI(inst), - UNTYPED_RW_RGBA(inst), - data_port_data_cache_simd_mode[UNTYPED_RW_SIMD_MODE(inst)], - data_port_data_cache_category[UNTYPED_RW_CATEGORY(inst)], - data_port1_data_cache_msg_type[UNTYPED_RW_MSG_TYPE(inst)]); + UNTYPED_RW_BTI(inst), + UNTYPED_RW_RGBA(inst), + data_port_data_cache_simd_mode[UNTYPED_RW_SIMD_MODE(inst)], + data_port_data_cache_category[UNTYPED_RW_CATEGORY(inst)], + data_port1_data_cache_msg_type[UNTYPED_RW_MSG_TYPE(inst)]); break; case GEN_SFID_DATAPORT_CONSTANT: format(file, " (bti: %d, %s)", diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp index 3ee094b4..b00c276b 100644 --- a/backend/src/ir/instruction.cpp +++ b/backend/src/ir/instruction.cpp @@ -1719,6 +1719,31 @@ namespace ir { INLINE void AtomicInstruction::out(std::ostream &out, const Function &fn) const { this->outOpcode(out); out << "." << AS; + +#define OUT_ATOMIC_OP(TYPE) \ + case ATOMIC_OP_##TYPE: \ + { out << "." << #TYPE; \ + break; \ + } + switch(atomicOp) + { + OUT_ATOMIC_OP(AND) + OUT_ATOMIC_OP(OR) + OUT_ATOMIC_OP(XOR) + OUT_ATOMIC_OP(XCHG) + OUT_ATOMIC_OP(INC) + OUT_ATOMIC_OP(DEC) + OUT_ATOMIC_OP(ADD) + OUT_ATOMIC_OP(SUB) + OUT_ATOMIC_OP(IMAX) + OUT_ATOMIC_OP(IMIN) + OUT_ATOMIC_OP(UMAX) + OUT_ATOMIC_OP(UMIN) + OUT_ATOMIC_OP(CMPXCHG) + default: + out << "." << "INVALID"; + assert(0); + }; out << " %" << this->getDst(fn, 0); out << " {" << "%" << this->getSrc(fn, 0) << "}"; for (uint32_t i = 1; i < srcNum; ++i) |