add missing file

6 files changed, 714 insertions, 11 deletions

diff --git a/r600.h b/r600.h
new file mode 100644
index 0000000..a8482ba
--- /dev/null
+++ b/r600.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600_H
+#define R600_H
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include "xf86drm.h"
+#include "radeon_bo.h"
+#include "radeon_drm.h"
+#include "r600_winsys.h"
+
+#define R600_MAX_BATCH	256
+
+struct r600_winsys;
+struct r600_atom;
+
+struct radeon_ib {
+	u32	*ptr;
+	u32	cpkts;
+	u32	length_dw;
+	u32	*relocs;
+	u32	crelocs;
+	u32	nrelocs;
+};
+
+typedef int (*r600_atom_create_t)(struct r600_winsys*, struct r600_atom*, void*);
+typedef int (*r600_atom_emit_t)(struct r600_winsys*, struct r600_atom*, void*, struct radeon_ib*);
+
+struct r600_atom {
+	int				refcount;
+	u32				type;
+	u32				id;
+	u32				nflushes;
+	u32				npkts;
+	u32				nbo;
+	u32				pkts[1024];
+	struct radeon_bo		*bo[32];
+	u32				flags[32];
+	void				*state;
+	r600_atom_emit_t		emit;
+};
+
+struct r600_atom_flush {
+	u32			flags;
+	struct radeon_bo	*bo;
+};
+
+struct r600_batch {
+	struct r600_atom		*atoms[R600_BATCH_NATOMS];
+	struct r600_atom		*emit_atoms[R600_BATCH_NATOMS];
+	u32				nemit_atoms;
+	u32				nflush;
+	struct r600_atom_flush		flush[480];
+	u32				npkts;
+	struct drm_r600_batch		drm;
+};
+
+struct r600_scheduler {
+	struct radeon_ib		*ib;
+	u32				npkts;
+	u32				nbatch;
+	struct r600_batch		batch[R600_MAX_BATCH];
+	u32				last_id[R600_BATCH_NATOMS];
+};
+
+struct r600_winsys {
+	int				fd;
+	struct radeon_bo		*bo[32];
+	u32				nbo;
+	struct r600_scheduler		scheduler;
+	unsigned			npipes;
+	unsigned			nbanks;
+	unsigned			group_bytes;
+	struct radeon_bo_manager	*bom;
+};
+
+extern void r600_atom_ref(struct r600_atom *atom);
+extern u32 radeon_ib_reloc(struct radeon_ib *ib, struct radeon_bo *bo, u32 d);
+extern int radeon_ib_get(struct r600_winsys *rdev, struct radeon_ib **ib);
+extern void radeon_ib_free(struct radeon_ib *ib);
+extern int radeon_ib_schedule(struct r600_winsys *rdev, struct radeon_ib *ib);
+extern int r600_atom_emit_default(struct r600_winsys *rdev, struct r600_atom *atom,
+					void *data, struct radeon_ib *ib);
+extern void r600_winsys_set_bo_list(struct r600_winsys *rdev, u32 nbo, struct radeon_bo **bo);
+extern struct radeon_bo *radeon_bo_lookup(struct r600_winsys *rdev, u32 handle);
+extern u64 crc_64(void *d, size_t len);
+/* R700 */
+extern void r700_scheduler_states_default(struct r600_winsys *rdev, struct r600_scheduler *scheduler);
+extern int r600_atoms_init(struct r600_winsys *rdev);
+extern int r600_draw_cmd_size(struct drm_r600_batch *batch);
+extern int r600_draw_cmd_emit(struct radeon_ib *ib, struct drm_r600_batch *batch);
+extern void r600_memcpy_bo(struct radeon_bo *bo, u32 *src, u32 size);
+
+static inline int radeon_ib_begin(struct radeon_ib *ib, u32 ndw)
+{
+	if ((ib->cpkts + ndw) > ib->length_dw)
+		return -ENOMEM;
+	return 0;
+}
+
+static inline int radeon_ib_copy(struct radeon_ib *ib, u32 *pkts, u32 ndw)
+{
+	if ((ib->cpkts + ndw) > ib->length_dw) {
+		fprintf(stderr, "IB FULL !\n");
+		return -ENOMEM;
+	}
+	memcpy(&ib->ptr[ib->cpkts], pkts, ndw * 4);
+	ib->cpkts += ndw;
+	return 0;
+}
+
+#endif
diff --git a/r600_clear.c b/r600_clear.c
new file mode 100644
index 0000000..240f93e
--- /dev/null
+++ b/r600_clear.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include "radeon_bo.h"
+#include "r600.h"
+#include "r600_clear.h"
+#include "r600d.h"
+
+static u32 vsconstants[16] = {
+	0x3C03126F, 0x00000000, 0x00000000, 0xBF800000,
+	0x00000000, 0x3C03126F, 0x00000000, 0xBF800000,
+	0x00000000, 0x00000000, 0xBF800000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x3F800000,
+};
+
+static u32 vsshaders[64] = {
+    0x0000001C, 0x81000400, 0x00000005, 0x80000000,
+    0x00000007, 0xA04C0000, 0xC001A03C, 0x94000688,
+    0xC0024000, 0x94200688, 0x900000F8, 0x00A80C90,
+    0x00000000, 0x00000000, 0x00200001, 0x006C2810,
+    0x00A00401, 0x206C2800, 0x01200801, 0x406C2800,
+    0x81A00C01, 0x606C2800, 0x00202001, 0x006C2800,
+    0x00A02401, 0x206C2810, 0x01202801, 0x406C2800,
+    0x81A02C01, 0x606C2800, 0x00204001, 0x006C2800,
+    0x00A04401, 0x206C2800, 0x01204801, 0x406C2810,
+    0x81A04C01, 0x606C2800, 0x00206001, 0x006C2800,
+    0x00A06401, 0x206C2800, 0x01206801, 0x406C2800,
+    0x81A06C01, 0x606C2810, 0x00000002, 0x00940C90,
+    0x00000402, 0x20940C90, 0x00000802, 0x40940C90,
+    0x80000C02, 0x60940C90, 0x00000000, 0x00000000,
+    0x7C000000, 0x1C351001, 0x00080000, 0x0BEADEAF,
+    0x7C000100, 0x18ED1002, 0x00080000, 0x0BEADEAF,
+};
+
+static u32 fsshaders[20] = {
+    0x00000003, 0x80000000, 0x00000005, 0xA00C0000,
+    0xC0008000, 0x94200688, 0x900000F8, 0x00480C90,
+    0x00000000, 0x00000000, 0x00000000, 0x00340C90,
+    0x00000400, 0x20340C90, 0x00000800, 0x40340C90,
+    0x80000C00, 0x60340C90, 0x00000000, 0x00000000,
+};
+
+static float rvbo[32] = {
+    0.000000, 0.000000, -1.000000, 0.500000,
+    0.500000, 0.500000, 0.000000, 250.000000,
+    0.000000, -1.000000, 0.500000, 0.500000,
+    0.500000, 0.000000, 250.000000, 250.000000,
+    -1.000000, 0.500000, 0.500000, 0.500000,
+    0.000000, 0.000000, 250.000000, -1.000000,
+    0.500000, 0.500000, 0.500000, 0.000000,
+    0.000000, 0.000000, 0.000000, 0.000000,
+};
+
+int r600_clear_queue(struct r600_winsys *rw, struct r600_atom *fb,
+			struct r600_clear_data *rclear, unsigned buffers,
+			const float *rgba, float depth, unsigned stencil)
+{
+	struct drm_r600_scissor scissor;
+	struct drm_r600_framebuffer *pfb;
+	struct r600_request rq;
+	int r;
+
+	pfb = r600_atom_state(fb);
+	rclear->batch.scissor = r600_atom_destroy(rclear->batch.scissor);
+	rclear->batch.framebuffer = fb;
+	/* scissor */
+	scissor.pa_sc_vport_scissor_0_tl = 0x80000000;
+	scissor.pa_sc_vport_scissor_0_br = S_028244_BR_X(pfb->width) | S_028244_BR_Y(pfb->height);
+	rq.type = R600_ATOM_SCISSOR;
+	rq.data = &scissor;
+	rq.nbo = 0;
+	rclear->batch.scissor = r600_atom_create(rw, &rq);
+	/* queue batch */
+	rq.type = 0;
+	rq.data = &rclear->batch;
+	rq.nbo = 0;
+	r = r600_scheduler_queue(rw, &rq);
+	if (r)
+		return r;
+	r = r600_scheduler_flush(rw);
+	return r;
+}
+
+void r600_clear_destroy(struct r600_clear_data *rclear)
+{
+	rclear->batch.framebuffer = NULL;
+	rclear->batch.scissor = r600_atom_destroy(rclear->batch.scissor);
+	rclear->batch.rasterizer = r600_atom_destroy(rclear->batch.rasterizer);
+	rclear->batch.cb_cntl = r600_atom_destroy(rclear->batch.cb_cntl);
+	rclear->batch.viewport = r600_atom_destroy(rclear->batch.viewport);
+	rclear->batch.blend = r600_atom_destroy(rclear->batch.blend);
+	rclear->batch.vs_constants = r600_atom_destroy(rclear->batch.vs_constants);
+	rclear->batch.dsa = r600_atom_destroy(rclear->batch.dsa);
+	rclear->batch.vs_shader = r600_atom_destroy(rclear->batch.vs_shader);
+	rclear->batch.fs_shader = r600_atom_destroy(rclear->batch.fs_shader);
+}
+
+int r600_clear_init(struct r600_winsys *rw,
+			struct radeon_bo_manager *bom,
+			struct r600_clear_data *rclear)
+{
+	struct drm_r600_blend blend;
+	struct drm_r600_framebuffer fb;
+	struct drm_r600_cb_cntl cb_cntl;
+	struct drm_r600_dsa dsa;
+	struct drm_r600_rasterizer rasterizer;
+	struct drm_r600_viewport vport;
+	struct drm_r600_constants vs_constants;
+	struct drm_r600_vs_shader vs_shader;
+	struct drm_r600_fs_shader fs_shader;
+	struct drm_r600_shader_resource vs_resource;
+	struct r600_request rq;
+	struct radeon_bo *vbo = NULL;
+	struct radeon_bo *vs = NULL;
+	struct radeon_bo *fs = NULL;
+	int r = 0;
+
+	vbo = radeon_bo_open(bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
+	if (vbo == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	r600_memcpy_bo(vbo, (u32*)rvbo, 32 * 4);
+	vs = radeon_bo_open(bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
+	if (vs == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	r600_memcpy_bo(vs, (u32*)vsshaders, 64 * 4);
+	fs = radeon_bo_open(bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
+	if (fs == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	r600_memcpy_bo(fs, (u32*)fsshaders, 20 * 4);
+
+	/* rasterizer state */
+	rasterizer.pa_sc_mpass_ps_cntl = 0x00000000;
+	rasterizer.pa_sc_line_cntl = 0x00000400;
+	rasterizer.pa_sc_aa_config = 0x00000000;
+	rasterizer.pa_sc_aa_sample_locs_mctx = 0x00000000;
+	rasterizer.pa_sc_aa_mask = 0xffffffff;
+	rasterizer.pa_cl_clip_cntl = 0x00000000;
+	rasterizer.pa_cl_vs_out_cntl = 0x00000000;
+	rasterizer.pa_cl_naninf_cntl = 0x00000000;
+	rasterizer.pa_cl_gb_vert_clip_adj = 0x3f800000;
+	rasterizer.pa_cl_gb_vert_disc_adj = 0x3f800000;
+	rasterizer.pa_cl_gb_horz_clip_adj = 0x3f800000;
+	rasterizer.pa_cl_gb_horz_disc_adj = 0x3f800000;
+	rasterizer.pa_su_sc_mode_cntl = 0x00080000;
+	rasterizer.pa_su_point_size = 0x00080008;
+	rasterizer.pa_su_point_minmax = 0x80000000;
+	rasterizer.pa_su_line_cntl = 0x00000008;
+	rasterizer.pa_sc_line_stipple = 0x00000005;
+	rasterizer.pa_su_poly_offset_db_fmt_cntl = 0x00000000;
+	rasterizer.pa_su_poly_offset_clamp = 0x00000000;
+	rasterizer.pa_su_poly_offset_front_scale = 0x00000000;
+	rasterizer.pa_su_poly_offset_front_offset = 0x00000000;
+	rasterizer.pa_su_poly_offset_back_scale = 0x00000000;
+	rasterizer.pa_su_poly_offset_back_offset = 0x00000000;
+	rq.type = R600_ATOM_RASTERIZER;
+	rq.data = &rasterizer;
+	rq.nbo = 0;
+	rclear->batch.rasterizer = r600_atom_create(rw, &rq);
+	/* cb cntl */
+	cb_cntl.cb_clrcmp_control = 0x01000000;
+	cb_cntl.cb_clrcmp_src = 0x00000000;
+	cb_cntl.cb_clrcmp_dst = 0x000000ff;
+	cb_cntl.cb_clrcmp_msk = 0xffffffff;
+	cb_cntl.cb_color_control = 0x00cc0000;
+	cb_cntl.cb_clear_alpha = 0x00000000;
+	cb_cntl.cb_clear_blue = 0x00000000;
+	cb_cntl.cb_clear_green = 0x00000000;
+	cb_cntl.cb_clear_red = 0x00000000;
+	cb_cntl.cb_blend_alpha = 0x00000000;
+	cb_cntl.cb_blend_blue = 0x00000000;
+	cb_cntl.cb_blend_green = 0x00000000;
+	cb_cntl.cb_blend_red = 0x00000000;
+	cb_cntl.cb_fog_blue = 0x00000000;
+	cb_cntl.cb_fog_green = 0x00000000;
+	cb_cntl.cb_fog_red = 0x00000000;
+	rq.type = R600_ATOM_CB_CNTL;
+	rq.data = &cb_cntl;
+	rq.nbo = 0;
+	rclear->batch.cb_cntl = r600_atom_create(rw, &rq);
+	/* viewport */
+	vport.pa_cl_vte_cntl = 0x0000043f;
+	vport.pa_cl_vport_xscale_0 = 0x42fa0000;
+	vport.pa_cl_vport_xoffset_0 = 0x42fa0000;
+	vport.pa_cl_vport_yscale_0 = 0xc2fa0000;
+	vport.pa_cl_vport_yoffset_0 = 0x42fa0000;
+	vport.pa_cl_vport_zscale_0 = 0x3f000000;
+	vport.pa_cl_vport_zoffset_0 = 0x3f000000;
+	rq.type = R600_ATOM_VIEWPORT;
+	rq.data = &vport;
+	rq.nbo = 0;
+	rclear->batch.viewport = r600_atom_create(rw, &rq);
+	/* blend */
+	blend.cb_blend0_control = 0x00010001;
+	blend.cb_blend1_control = 0x00000000;
+	blend.cb_blend2_control = 0x00000000;
+	blend.cb_blend3_control = 0x00000000;
+	blend.cb_blend4_control = 0x00000000;
+	blend.cb_blend5_control = 0x00000000;
+	blend.cb_blend6_control = 0x00000000;
+	blend.cb_blend7_control = 0x00000000;
+	blend.cb_blend_control = 0x00010001;
+	rq.type = R600_ATOM_BLEND;
+	rq.data = &blend;
+	rq.nbo = 0;
+	rclear->batch.blend = r600_atom_create(rw, &rq);
+	/* ps constant */
+	rclear->batch.ps_constants = NULL;
+	/* vs constant */
+	vs_constants.nconstants = 4;
+	vs_constants.offset = 0x400;
+	memcpy(vs_constants.constants, vsconstants, vs_constants.nconstants * 4 * 4);
+	rq.type = R600_ATOM_CONSTANTS;
+	rq.data = &vs_constants;
+	rq.nbo = 0;
+	rclear->batch.vs_constants = r600_atom_create(rw, &rq);
+	/* depth stencil alpha */
+	dsa.db_stencil_clear = 0x00000000;
+	dsa.db_depth_clear = 0x3F800000;
+	dsa.db_stencilrefmask = 0xFFFFFF00;
+	dsa.db_stencilrefmask_bf = 0xFFFFFF00;
+	dsa.db_depth_control = 0x00700700;
+	dsa.db_shader_control = 0x00000210;
+	dsa.db_render_control = 0x00000060;
+	dsa.db_render_override = 0x0000002A;
+	dsa.db_alpha_to_mask = 0x0000AA00;
+	dsa.db_sresults_compare_state1 = 0x00000000;
+	dsa.db_preload_control = 0x00000000;
+	rq.type = R600_ATOM_DSA;
+	rq.data = &dsa;
+	rq.nbo = 0;
+	rclear->batch.dsa = r600_atom_create(rw, &rq);
+	/* vs_shader */
+	vs_shader.ninputs = 2;
+	vs_shader.input_semantic[0] = 1;
+	vs_shader.input_gpr[0] = 1;
+	vs_shader.input_semantic[1] = 2;
+	vs_shader.input_gpr[1] = 2;
+	vs_shader.noutputs = 1;
+	vs_shader.output_semantic[0] = 4;
+	vs_shader.sq_pgm_resources_vs = 0x00000006;
+	vs_shader.ndwords = 64;
+	vs_shader.handle = vs->handle;
+	vs_shader.offset = 0;
+	rq.bo[0] = vs;
+	rq.nbo = 1;
+	rq.type = R600_ATOM_VS_SHADER;
+	rq.data = &vs_shader;
+	rclear->batch.vs_shader = r600_atom_create(rw, &rq);
+	/* ps_shader */
+	fs_shader.spi_ps_input_cntl[0] = 0x00000804;
+	fs_shader.spi_ps_input_cntl[1] = 0x00000000;
+	fs_shader.spi_ps_in_control_0 = 0x10000001;
+	fs_shader.spi_ps_in_control_1 = 0x00000000;
+	fs_shader.sq_pgm_resources_ps = 0x00000003;
+	fs_shader.sq_pgm_exports_ps = 0x00000002;
+	fs_shader.ndwords = 20;
+	fs_shader.handle = fs->handle;
+	fs_shader.offset = 0;
+	rq.bo[0] = fs;
+	rq.nbo = 1;
+	rq.type = R600_ATOM_FS_SHADER;
+	rq.data = &fs_shader;
+	rclear->batch.fs_shader = r600_atom_create(rw, &rq);
+	/* inputs */
+	vs_resource.nresource = 2;
+	vs_resource.resource[0].handle = vbo->handle;
+	vs_resource.resource[0].resource_id = 0;
+	vs_resource.resource[0].sq_vtx_constant_word0 = 0x00000000;
+	vs_resource.resource[0].sq_vtx_constant_word1 = vbo->size;
+	vs_resource.resource[0].sq_vtx_constant_word2 = 0x03001C00;
+	vs_resource.resource[0].sq_vtx_constant_word3 = 0x00000001;
+	vs_resource.resource[0].sq_vtx_constant_word4 = 0x00000000;
+	vs_resource.resource[0].sq_vtx_constant_word5 = 0x00000000;
+	vs_resource.resource[0].sq_vtx_constant_word6 = 0xC0000000;
+	vs_resource.resource[1].handle = vbo->handle;
+	vs_resource.resource[1].resource_id = 1;
+	vs_resource.resource[1].sq_vtx_constant_word0 = 0x0000000C;
+	vs_resource.resource[1].sq_vtx_constant_word1 = vbo->size - 0xC;
+	vs_resource.resource[1].sq_vtx_constant_word2 = 0x02301C00;
+	vs_resource.resource[1].sq_vtx_constant_word3 = 0x00000001;
+	vs_resource.resource[1].sq_vtx_constant_word4 = 0x00000000;
+	vs_resource.resource[1].sq_vtx_constant_word5 = 0x00000000;
+	vs_resource.resource[1].sq_vtx_constant_word6 = 0xC0000000;
+	rq.bo[0] = vbo;
+	rq.bo[1] = vbo;
+	rq.nbo = 2;
+	rq.type = R600_ATOM_SHADER_RESOURCE;
+	rq.data = &vs_resource;
+	rclear->batch.vs_resource = r600_atom_create(rw, &rq);
+	rclear->batch.vgt_primitive_type = 5;
+	rclear->batch.vgt_dma_index_type = 0;
+	rclear->batch.vgt_dma_num_instances = 1;
+	rclear->batch.vgt_num_indices = 4;
+	rclear->batch.vgt_draw_initiator = 2;
+out_err:
+	radeon_bo_unref(vbo);
+	radeon_bo_unref(fs);
+	radeon_bo_unref(vs);
+	return r;
+}
diff --git a/r600_clear.h b/r600_clear.h
new file mode 100644
index 0000000..227551d
--- /dev/null
+++ b/r600_clear.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600_CLEAR_H
+#define R600_CLEAR_H
+
+#include "r600_winsys.h"
+
+struct r600_clear_data {
+	struct drm_r600_batch	batch;
+};
+
+int r600_clear_queue(struct r600_winsys *rw, struct r600_atom *fb,
+			struct r600_clear_data *rclear, unsigned buffers,
+			const float *rgba, float depth, unsigned stencil);
+void r600_clear_destroy(struct r600_clear_data *rclear);
+int r600_clear_init(struct r600_winsys *rw,
+			struct radeon_bo_manager *bom,
+			struct r600_clear_data *rclear);
+
+#endif
+
diff --git a/r600_winsys.c b/r600_winsys.c
new file mode 100644
index 0000000..b9bbe87
--- /dev/null
+++ b/r600_winsys.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include "r600.h"
+#include "r600_winsys.h"
+
+#pragma pack(1)
+struct ib_reloc_gem {
+    uint32_t    handle;
+    uint32_t    read_domain;
+    uint32_t    write_domain;
+    uint32_t    flags;
+};
+#pragma pack()
+#define RELOC_SIZE (sizeof(struct ib_reloc_gem) / sizeof(uint32_t))
+
+u32 radeon_ib_reloc(struct radeon_ib *ib, struct radeon_bo *bo, u32 d)
+{
+	struct ib_reloc_gem *reloc;
+	int i;
+
+	for (i = 0; i < ib->crelocs; i++) {
+		reloc = (struct ib_reloc_gem*)&ib->relocs[i * RELOC_SIZE];
+		if (reloc->handle == bo->handle) {
+			reloc->read_domain |= d;
+			return (i * RELOC_SIZE);
+		}
+	}
+	if (ib->crelocs >= ib->nrelocs)
+		return 0xFFFFFFFFUL;
+	i = ib->crelocs++;
+	reloc = (struct ib_reloc_gem*)&ib->relocs[i * RELOC_SIZE];
+	reloc->handle = bo->handle;
+	reloc->read_domain = d;
+	reloc->write_domain = 0;
+	reloc->flags = 0;
+	return (i * RELOC_SIZE);
+}
+
+int radeon_ib_get(struct r600_winsys *rdev, struct radeon_ib **ib)
+{
+	struct radeon_ib *lib;
+
+	lib = malloc(sizeof(struct radeon_ib));
+	if (lib == NULL)
+		return -ENOMEM;
+	memset(lib, sizeof(*lib), 0);
+	lib->ptr = malloc(64 * 1024);
+	if (lib->ptr == NULL) {
+		free(lib);
+		return -ENOMEM;
+	}
+	lib->cpkts = 0;
+	lib->length_dw = 64 * 1024 / 4;
+	lib->relocs = malloc(64 * 1024);
+	if (lib->relocs == NULL) {
+		free(lib->ptr);
+		free(lib);
+		return -ENOMEM;
+	}
+	lib->nrelocs = 64 * 1024 / RELOC_SIZE;
+	lib->crelocs = 0;
+	*ib = lib;
+	return 0;
+}
+
+void radeon_ib_free(struct radeon_ib *ib)
+{
+	if (ib == NULL)
+		return;
+	free(ib->ptr);
+	free(ib->relocs);
+	free(ib);
+}
+
+int radeon_ib_schedule(struct r600_winsys *rdev, struct radeon_ib *ib)
+{
+	struct drm_radeon_cs drmib;
+	struct drm_radeon_cs_chunk chunks[2];
+	uint64_t chunk_array[2];
+	int r = 0;
+
+#if 0
+	for (r = 0; r < ib->cpkts; r++) {
+		printf("0x%08X\n", ib->ptr[r]);
+	}
+#endif
+	drmib.num_chunks = 2;
+	drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
+	chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
+	chunks[0].length_dw = ib->cpkts;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)ib->ptr;
+	chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
+	chunks[1].length_dw = ib->crelocs * 4;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)ib->relocs;
+	chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
+	chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
+#if 1
+	r = drmCommandWriteRead(rdev->fd, DRM_RADEON_CS, &drmib,
+				sizeof(struct drm_radeon_cs));
+#endif
+	return r;
+}
+
+int r600_winsys_init(struct r600_winsys **rdev, struct radeon_bo_manager *bom, int fd)
+{
+	struct r600_winsys *dev;
+	int r;
+
+	*rdev = NULL;
+	dev = malloc(sizeof(struct r600_winsys));
+	if (dev == NULL)
+		return -ENOMEM;
+	memset(dev, 0, sizeof(struct r600_winsys));
+	dev->fd = fd;
+	dev->bom = bom;
+	r = r600_atoms_init(dev);
+	if (r)
+		return r;
+	*rdev = dev;
+	return r;
+}
+
+void r600_winsys_release(struct r600_winsys *rdev)
+{
+	memset(rdev, 0, sizeof(struct r600_winsys));
+	free(rdev);
+}
+
+u64 crc_64(void *d, size_t len)
+{
+	u8 *data = (uint8_t*)d;
+	u64 div = 0x42F0E1EBA9EA3693;
+	u64 crc = 0xFFFFFFFFFFFFFFFF;
+	u8 t;
+	int i, j;
+
+	for (j = 0; j < len; j++) {
+		t = data[j];
+		for (i = 0; i < 8; i++) {
+			if ((t >> 7) ^ (crc >> 63)) {
+				crc = (crc << 1) ^ div;
+			} else {
+				crc = (crc << 1);
+			}
+			t = (t << 1) & 0xFF;
+		}
+	}
+	return crc;
+}
+
+void r600_memcpy_bo(struct radeon_bo *bo, u32 *src, u32 size)
+{
+	int r;
+
+	r = radeon_bo_map(bo, 1);
+	if (r) {
+		return;
+	}
+	memcpy(bo->ptr, src, size);
+	radeon_bo_unmap(bo);
+}
+
+void r600_winsys_set_bo_list(struct r600_winsys *rdev, u32 nbo, struct radeon_bo **bo)
+{
+	memcpy(rdev->bo, bo, sizeof(void*) * nbo);
+	rdev->nbo = nbo;
+}
+
+struct radeon_bo *radeon_bo_lookup(struct r600_winsys *rdev, u32 handle)
+{
+	int i;
+
+	for (i = 0; i < rdev->nbo; i++) {
+		if (rdev->bo[i] && rdev->bo[i]->handle == handle) {
+			radeon_bo_ref(rdev->bo[i]);
+			return rdev->bo[i];
+		}
+	}
+	return NULL;
+}
diff --git a/r600_winsys.h b/r600_winsys.h
index 70fb433..ce60ee7 100644
--- a/r600_winsys.h
+++ b/r600_winsys.h
@@ -252,15 +252,4 @@ extern struct r600_atom *r600_atom_destroy(struct r600_atom *atom);
 
 struct pipe_screen *r600_create_screen(struct r600_winsys *r600_winsys, struct radeon_bo_manager *bom);
 
-struct r600_clear_data {
-	struct drm_r600_batch	batch;
-};
-
-int r600_clear_queue(struct r600_winsys *rw, struct r600_atom *fb,
-			struct r600_clear_data *rclear, unsigned buffers,
-			const float *rgba, float depth, unsigned stencil);
-void r600_clear_destroy(struct r600_clear_data *rclear);
-int r600_clear_init(struct r600_winsys *rw,
-			struct radeon_bo_manager *bom,
-			struct r600_clear_data *rclear);
 #endif
diff --git a/test.c b/test.c
index aef1a6b..fa1f2df 100644
--- a/test.c
+++ b/test.c
@@ -22,6 +22,7 @@
 #include <string.h>
 #include <errno.h>
 #include "r600_winsys.h"
+#include "r600_clear.h"
 #include "radeon.h"
 
 int r600_winsys_init(struct r600_winsys **rdev, struct radeon_bo_manager *bom, int fd);