path: root/r600_winsys.h

/*
 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * on the rights to use, copy, modify, merge, publish, distribute, sub
 * license, and/or sell copies of the Software, and to permit persons to whom
 * the Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *      Jerome Glisse
 */
#ifndef R600_WINSYS_H
#define R600_WINSYS_H

#include "radeon_bo.h"

typedef uint64_t		u64;
typedef uint32_t		u32;
typedef uint8_t			u8;

/* opaque structure */
struct r600_winsys;
struct r600_atom;

#define R600_ATOM_FRAMEBUFFER		1
#define R600_ATOM_RASTERIZER		2
#define R600_ATOM_CB_CNTL		3
#define R600_ATOM_VIEWPORT		4
#define R600_ATOM_SCISSOR		5
#define R600_ATOM_BLEND			6
#define R600_ATOM_CONSTANTS		7
#define R600_ATOM_DSA			8
#define R600_ATOM_VS_SHADER		9
#define R600_ATOM_FS_SHADER		10
#define R600_ATOM_SHADER_RESOURCE	11
#define R600_BATCH_NATOMS		12

struct drm_r600_surface {
	u32			width;
	u32			height;
	u32			color_info;
	u32			cb_target_mask;
	u32			cb_shader_mask;
	u32			nsamples;
	u32			offset;
	u32			placements[2];
	u32			handle;
};

struct drm_r600_framebuffer {
	u32			width;
	u32			height;
	u32			ncb;
	struct drm_r600_surface	cb[8];
	u32			db_offset;
	u32			db_placements[2];
	u32			db_handle;
	u32			db_depth_size;
	u32			db_depth_view;
	u32			db_depth_info;
	u32			db_htile_surface;
	u32			db_prefetch_limit;
};

struct drm_r600_cb_cntl {
	u32			cb_clrcmp_control;
	u32			cb_clrcmp_src;
	u32			cb_clrcmp_dst;
	u32			cb_clrcmp_msk;
	u32			cb_color_control;
	u32			cb_blend_alpha;
	u32			cb_blend_blue;
	u32			cb_blend_green;
	u32			cb_blend_red;
	u32			cb_clear_alpha;
	u32			cb_clear_blue;
	u32			cb_clear_green;
	u32			cb_clear_red;
	u32			cb_fog_blue;
	u32			cb_fog_green;
	u32			cb_fog_red;
};

/* pa - primitive assembly */
struct drm_r600_rasterizer {
	u32			pa_sc_mpass_ps_cntl;
	u32			pa_sc_line_cntl;
	u32			pa_sc_aa_config;
	u32			pa_sc_aa_sample_locs_mctx;
	u32			pa_sc_aa_mask;
	u32			pa_cl_clip_cntl;
	u32			pa_cl_vs_out_cntl;
	u32			pa_cl_naninf_cntl;
	u32			pa_cl_gb_vert_clip_adj;
	u32			pa_cl_gb_vert_disc_adj;
	u32			pa_cl_gb_horz_clip_adj;
	u32			pa_cl_gb_horz_disc_adj;
	u32			pa_su_sc_mode_cntl;
	u32			pa_su_point_size;
	u32			pa_su_point_minmax;
	u32			pa_su_line_cntl;
	u32			pa_sc_line_stipple;
	u32			pa_su_poly_offset_db_fmt_cntl;
	u32			pa_su_poly_offset_clamp;
	u32			pa_su_poly_offset_front_scale;
	u32			pa_su_poly_offset_front_offset;
	u32			pa_su_poly_offset_back_scale;
	u32			pa_su_poly_offset_back_offset;
};

/* vport - viewport */
struct drm_r600_viewport {
	u32			pa_cl_vte_cntl;
	u32			pa_cl_vport_xscale_0;
	u32			pa_cl_vport_yscale_0;
	u32			pa_cl_vport_zscale_0;
	u32			pa_cl_vport_xoffset_0;
	u32			pa_cl_vport_yoffset_0;
	u32			pa_cl_vport_zoffset_0;
};

/* pipe_scissor_state */
struct drm_r600_scissor {
	u32			pa_sc_vport_scissor_0_tl;
	u32			pa_sc_vport_scissor_0_br;
};

/* blend - blending */
struct drm_r600_blend {
	u32			cb_blend0_control;
	u32			cb_blend1_control;
	u32			cb_blend2_control;
	u32			cb_blend3_control;
	u32			cb_blend4_control;
	u32			cb_blend5_control;
	u32			cb_blend6_control;
	u32			cb_blend7_control;
	u32			cb_blend_control;
};

/* constant */
struct drm_r600_constants {
	u32			offset;
	u32			nconstants;
	u32			constants[512];
};

/* depth, stencil, alpha control */
struct drm_r600_dsa {
	u32			db_stencil_clear;
	u32			db_depth_clear;
	u32			db_stencilrefmask;
	u32			db_stencilrefmask_bf;
	u32			db_depth_control;
	u32			db_shader_control;
	u32			db_render_control;
	u32			db_render_override;
	u32			db_sresults_compare_state1;
	u32			db_preload_control;
	u32			db_alpha_to_mask;
};

/* vs_shader - vertex shader */
struct drm_r600_vs_shader {
	u32			sq_pgm_resources_vs;
	u8			input_semantic[32];
	u8			input_gpr[32];
	u8			ninputs;
	u8			output_semantic[32];
	u8			fog_output_id;
	u8			noutputs;
	u32			ndwords;
	u32			handle;
	u32			offset;
};

/* fragment shader */
struct drm_r600_fs_shader {
	u32			spi_ps_in_control_0;
	u32			spi_ps_in_control_1;
	u32			spi_ps_input_cntl[32];
	u32			sq_pgm_resources_ps;
	u32			sq_pgm_exports_ps;
	u32			ndwords;
	u32			handle;
	u32			offset;
};

struct drm_r600_resource {
	u32			handle;
	u32			resource_id;
	u32			sq_vtx_constant_word0;
	u32			sq_vtx_constant_word1;
	u32			sq_vtx_constant_word2;
	u32			sq_vtx_constant_word3;
	u32			sq_vtx_constant_word4;
	u32			sq_vtx_constant_word5;
	u32			sq_vtx_constant_word6;
};

struct drm_r600_shader_resource {
	u32				nresource;
	struct drm_r600_resource	resource[32];
};

struct drm_r600_batch {
	struct r600_atom		*vs_constants;
	struct r600_atom		*ps_constants;
	struct r600_atom		*blend;
	struct r600_atom		*framebuffer;
	struct r600_atom		*cb_cntl;
	struct r600_atom		*rasterizer;
	struct r600_atom		*viewport;
	struct r600_atom		*scissor;
	struct r600_atom		*dsa;
	struct r600_atom		*vs_shader;
	struct r600_atom		*fs_shader;
	struct r600_atom		*vs_resource;
	u32				vgt_primitive_type;
	u32				vgt_dma_index_type;
	u32				vgt_dma_num_instances;
	u32				vgt_num_indices;
	u32				vgt_draw_initiator;
};

struct r600_request {
	u32				type;
	void				*data;
	u32				nbo;
	struct radeon_bo		*bo[32];
};

extern int r600_scheduler_queue(struct r600_winsys*, struct r600_request*);
extern int r600_scheduler_flush(struct r600_winsys*);
extern void *r600_atom_state(struct r600_atom *atom);
extern struct r600_atom *r600_atom_create(struct r600_winsys*, struct r600_request*);
extern struct r600_atom *r600_atom_destroy(struct r600_atom *atom);

struct pipe_screen *r600_create_screen(struct r600_winsys *r600_winsys, struct radeon_bo_manager *bom);

struct r600_clear_data {
	struct drm_r600_batch	batch;
};

int r600_clear_queue(struct r600_winsys *rw, struct r600_atom *fb,
			struct r600_clear_data *rclear, unsigned buffers,
			const float *rgba, float depth, unsigned stencil);
void r600_clear_destroy(struct r600_clear_data *rclear);
int r600_clear_init(struct r600_winsys *rw,
			struct radeon_bo_manager *bom,
			struct r600_clear_data *rclear);
#endif