summaryrefslogtreecommitdiff
path: root/src/mesa/drivers
AgeCommit message (Expand)AuthorFilesLines
2014-10-01i965: Initialize the SampleMap{2,4,8}x variablesAnuj Phogat3-0/+55
2014-10-01i965: Drop CACHE_NEW_VS_PROG from the gen7_sf_state atom.Kenneth Graunke1-1/+1
2014-10-01i965: Drop brwBindProgram driver hook.Kenneth Graunke1-20/+0
2014-10-01i965: Add missing /* BRW_NEW_FRAGMENT_PROGRAM */ comments.Kenneth Graunke3-6/+7
2014-10-01i965: Use "1ull" instead of "1" in BRW_NEW_* defines.Kenneth Graunke1-32/+32
2014-10-01i965: Use ~0ull when flagging all BRW_NEW_* dirty flags.Kenneth Graunke3-4/+4
2014-10-01i965: Fix INTEL_DEBUG=state to work with 64-bit dirty bits.Kenneth Graunke1-16/+7
2014-10-01i965: Delete CACHE_NEW_BLORP_CONST_COLOR_PROG.Kenneth Graunke2-3/+0
2014-10-01i965: Fix typo in commentChris Forbes1-1/+1
2014-10-01i965: Fix spelling of GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHMChris Forbes2-2/+2
2014-09-30i965/fs: Fix the buildJason Ekstrand1-1/+1
2014-09-30i965/fs: Fix an uninitialized value warningsJason Ekstrand1-3/+4
2014-09-30i965/fs: Emit compressed BFI2 instructions on Gen > 7.Matt Turner1-1/+1
2014-09-30i965/fs: Allow SIMD16 borrow/carry/64-bit multiply on Gen > 7.Matt Turner1-3/+3
2014-09-30i965/fs: Set MUL source type to W/UW in 64-bit mul macro on Gen8.Matt Turner1-1/+22
2014-09-30i965/fs: Optimize sqrt+inv into rsq.Matt Turner1-0/+11
2014-09-30i965/vec4: Optimize sqrt+inv into rsq.Matt Turner1-0/+11
2014-09-30i965/vec4: Call opt_algebraic after opt_cse.Matt Turner1-1/+1
2014-09-30i965/fs: Extend predicated break pass to predicate WHILE.Matt Turner1-0/+36
2014-09-30i965/fs: Don't make a name for a vector splitting temporaryIan Romanick1-3/+8
2014-09-30glsl: Make ir_variable::num_state_slots and ir_variable::state_slots privateIan Romanick3-9/+9
2014-09-30i965/brw_reg: Make the accumulator register take an explicit width.Jason Ekstrand3-10/+15
2014-09-30mesa: Drop the always-software-primitive-restart paths.Eric Anholt1-8/+0
2014-09-30i965/fs: Properly calculate the number of instructions in calculate_register_...Jason Ekstrand1-1/+3
2014-09-30i965/fs: Use the GRF for FB writes on gen >= 7Jason Ekstrand6-71/+142
2014-09-30i965/fs: Handle COMPR4 in LOAD_PAYLOADJason Ekstrand2-1/+36
2014-09-30i965/fs: Constant propagate into LOAD_PAYLOADJason Ekstrand1-0/+1
2014-09-30i965/fs: Add split_virtual_grfs and compute_to_mrf after lower_load_payloadJason Ekstrand1-0/+2
2014-09-30i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instructionJason Ekstrand4-29/+28
2014-09-30i965/fs: Use the GRF for UNTYPED_SURFACE_READ instructionsJason Ekstrand4-16/+24
2014-09-30i965/fs: Use the GRF for UNTYPED_ATOMIC instructionsJason Ekstrand6-25/+36
2014-09-30i965/fs: Add a function for getting a component of a 8 or 16-wide registerJason Ekstrand1-0/+10
2014-09-30i965/fs: Use the instruction execution size directly for texture generationJason Ekstrand1-3/+10
2014-09-30i965/fs: Use exec_size instead of force_uncompressed in dump_instructionJason Ekstrand1-6/+7
2014-09-30i965/fs: Use instruction execution sizes instead of heuristicsJason Ekstrand3-23/+10
2014-09-30i965/fs: Use instruction execution sizes to set compression stateJason Ekstrand1-6/+19
2014-09-30i965/fs: Remove unneeded uses of force_uncompressedJason Ekstrand3-25/+9
2014-09-30i965/fs: Derive force_uncompressed from instruction exec_sizeJason Ekstrand1-0/+3
2014-09-30i965/fs: Make fs_reg::effective_width take fs_inst* instead of fs_visitor*Jason Ekstrand3-37/+43
2014-09-30i965/fs: Better guess the width of LOAD_PAYLOADJason Ekstrand1-2/+9
2014-09-30i965/fs: Add an exec_size field to fs_instJason Ekstrand5-32/+126
2014-09-30i965/fs: Determine partial writes based on the destination widthJason Ekstrand2-5/+3
2014-09-30i965/fs: Fix a bug in register coalesceJason Ekstrand1-0/+17
2014-09-30i965/fs: Rework GEN5 texturing code to use fs_reg and offset()Jason Ekstrand1-39/+38
2014-09-30i965/fs_reg: Allocate double the number of vgrfs in SIMD16 modeJason Ekstrand9-157/+371
2014-09-30i965/fs: Handle printing of registers better.Jason Ekstrand1-2/+6
2014-09-30i965: Explicitly set widths on gen5 math instruction destinations.Jason Ekstrand1-1/+1
2014-09-30i965/fs: Make half() divide the register width by 2 and use it moreJason Ekstrand2-5/+13
2014-09-30i965/fs: Add a concept of a width to fs_regJason Ekstrand2-4/+78
2014-09-30i965/fs: A little harmless refactoring of register_coalesceJason Ekstrand1-7/+7
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-09 13:21:16 +0000