index
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mesa/mesa
10.0
10.1
10.2
10.3
10.4
10.5
10.6
11.0
11.1
11.2
12.0
13.0
17.0
17.1
17.2
17.3
18.0
18.1
18.2
18.3
19.0
19.1
19.2
19.3
20.0
20.1
20.2
20.3
21.0
21.1
21.2
21.3
22.0
22.1
22.2
22.3
23.0
23.1
23.2
23.3
24.0
24.1
7.10
7.11
7.8
7.8-gles
7.9
8.0
9.0
9.1
9.2
a7xx-gmem
amber
elima/radv-video-encode-caps-maxbitrate
explicit-sync
main
powervr-mesa-next-wayland
review/fragment_shader_barycentric
staging/23.2
staging/23.3
staging/24.0
staging/24.1
uav-counter-meta
vk-no-nir-android
zink-stablefix
The Mesa 3D Graphics Library (mirrored from https://gitlab.freedesktop.org/mesa/mesa)
brianp
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path:
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src
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mesa
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drivers
/
dri
/
i965
/
brw_disasm.c
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Author
Files
Lines
2011-05-13
i965: Rename dp_render_target struct to gen6_dp.
Kenneth Graunke
1
-12
/
+12
2010-12-23
i965: Correct the dp_read message descriptor setup on g4x.
Eric Anholt
1
-1
/
+1
2010-12-01
i965: Dump the WHILE jump distance on gen6.
Eric Anholt
1
-1
/
+2
2010-10-26
i965: Add disasm for the flag register.
Eric Anholt
1
-0
/
+3
2010-10-26
i965: Use SENDC on the first render target write on gen6.
Eric Anholt
1
-3
/
+7
2010-10-06
i965: Add some clarification of the WECtrl field.
Eric Anholt
1
-2
/
+2
2010-10-06
i965: Fix up IF/ELSE/ENDIF for gen6.
Eric Anholt
1
-0
/
+5
2010-10-04
i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod.
Eric Anholt
1
-1
/
+1
2010-09-28
i965: disasm quarter and write enable instruction control on sandybridge
Zhenyu Wang
1
-9
/
+61
2010-08-28
i965: Add disasm for gen5 sampler messages.
Eric Anholt
1
-6
/
+19
2010-08-20
i965: Add AccWrCtl support on Sandybridge.
Zhenyu Wang
1
-0
/
+7
2010-08-20
i965: Mention the mlen and rlen for URB reads.
Zhenyu Wang
1
-0
/
+5
2010-08-20
i965: Adjust disasm of subreg numbers to be in units of the register type.
Zhenyu Wang
1
-6
/
+20
2010-08-16
i965: Add disasm for Compr4 instruction compression.
Eric Anholt
1
-1
/
+16
2010-07-22
i965: Fix the disasm output for da16 src widths.
Eric Anholt
1
-1
/
+1
2010-07-21
i965: Add disasm for dataport reads (register unspilling).
Eric Anholt
1
-1
/
+22
2010-07-08
i965: Add disasm for SEND mlen/rlen on Sandybridge.
Eric Anholt
1
-1
/
+1
2010-07-08
i965: Fix disasm of a SEND's mlen and rlen on Ironlake.
Eric Anholt
1
-4
/
+11
2010-07-08
i965: Add decode for Sandybridge DP write messages.
Zhenyu Wang
1
-9
/
+21
2010-05-14
i965: Parse the ff_sync URB send opcode on Ironlake disasm.
Eric Anholt
1
-1
/
+15
2010-05-14
i965: Dump out the correct shared function for SEND on Ironlake.
Eric Anholt
1
-3
/
+11
2010-03-22
i965: Add disasm for SNB MATH opcode.
Eric Anholt
1
-1
/
+6
2010-03-10
i965: Use the PLN instruction when possible in interpolation.
Eric Anholt
1
-0
/
+1
2010-03-10
i965: Print the offset for IFF in disasm
Eric Anholt
1
-1
/
+1
2010-03-09
i965: Print the offsets for WHILE and BREAK in disasm.
Eric Anholt
1
-2
/
+2
2009-12-31
Merge branch 'mesa_7_7_branch'
Brian Paul
1
-0
/
+1
2009-12-26
i965: Fix setup of immediate types for gen4 disasm.
Eric Anholt
1
-1
/
+1
2009-12-24
i965: Add missing va_end.
Vinson Lee
1
-0
/
+1
2009-08-04
i965: Print out ELSE and ENDIF src1 arguments like IF does.
Eric Anholt
1
-2
/
+2
2009-08-04
i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.
Eric Anholt
1
-5
/
+7
2009-08-04
i965: Initial import of disasm code from intel-gen4asm.
Eric Anholt
1
-0
/
+901