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2022-04-17gallium: move drivers/radeon/* into drivers/radeonsi/Marek Olšák26-56720/+0
this is only used by radeonsi Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Mihai Preda <mhpreda@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15907>
2022-03-11radeon: add EFC support to only VCN2.0 devicesThong Thai5-43/+40368
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5228 Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15196>
2022-03-01amd: add support for gfx1036 and gfx1037 chipsMarek Olšák1-0/+1
Both are identified as GFX1036 for simplicity. Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Tested-by: Yifan Zhang <yifan1.zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>
2022-01-26radeon/vcn: Updating render_pic_list for correctionRuijing Dong1-1/+21
In order to keep track of reference frame buffer address changing, using past_ref to compare with render_pic_list, once the one in past_ref is valid and if render_pic_list has that entry, it will need to update it to the latest one in ref[i]. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5868 Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14646>
2022-01-20amd: move uvd decode definitions to common placeDave Airlie1-395/+1
This just makes sharing these easier later. Acked-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14607>
2022-01-20amd: move vcn decoding regs + structs to a common file.Dave Airlie2-1055/+1
This just moves the main regs + fw interface structs to a new shared file. Acked-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14607>
2022-01-12radeon/vcn: enable dynamic dpb Tier2 for hevc dec vaapi pathRuijing Dong1-1/+11
keep omx hevc decoding using the current mode, set dpb Tier2 for vaapi hevc decoding mode as default. Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14484>
2022-01-12radeon/vcn: enable dynamic dpb Tier2 support for h264 dec vaapi pathRuijing Dong2-13/+143
By disabling h264 enxtension flag to let vaapi application manage the dpb buffers. The calculation of the non_exist_flags for h264 reference frames needs to consider both frame number and POC in the reference picture list, set this flag only if both of the frame number and POC are not existed in the valid reference lists; otherwise, that reference frame is considered valid. Also enabled drm buffer in dynamic dpb Tier2. Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14484>
2021-12-30winsys/radeon: change surface_init flags to 64bitQiang Yu1-1/+1
RADEON_SURF_PRT is (1ull << 32). Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14223>
2021-12-08radeon/vcn: implement encoder dpb managementThong Thai3-14/+81
Previously, the number of previously encoded frames the encoder handled was 1 - the encoder now supports many more encoded pictures, so the encoder now has to keep track of multiple reconstructed pictures. v2: Add a check to make sure an array index is not negative (Boyuan) Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13915>
2021-12-08radeon: hardcode uvd/vce encoder not_referenced value to falseThong Thai2-2/+2
Sets the not_referenced parameter to be the same as the previously hardcoded frontends/va value (false) to ensure UVD/VCE encoding functionality remains unaffected by the change in frontends/va code. This commit will eventually be reverted once more testing is completed. Fixes: a90802ef644 ("frontends/va/enc: allow for frames to be marked as (not) referenced") Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13915>
2021-12-08radeon/vcn: increase encoder dpb sizeThong Thai4-58/+68
Base the number of reconstructed pictures the encoder allocates based on the number of reference pictures to be used for encoding. Also move the calculation and allocation of reconstructed pictures to VCN 1, from VCN 2. v2: Add back the accidentally deleted 'two_pass_search_center_map_offset' (Boyuan) Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13915>
2021-10-29winsys/amdgpu: remove an amdgpu_cs dereference from amdgpu_cs_add_bufferMarek Olšák1-0/+1
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
2021-10-29gallium/radeon: merge BO read/write usage flags with priority flagsMarek Olšák9-45/+42
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
2021-10-29gallium/radeon: remove unused RADEON_DEPENDENCY_START_FENCEMarek Olšák1-8/+0
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
2021-10-29gallium/radeon: remove/merge some BO priorities and remove holesMarek Olšák1-31/+24
The upper bits will be used by RADEON_USAGE_* Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
2021-10-29gallium/radeon: change the BO priority definitions to bitsMarek Olšák1-33/+29
This is for the next microoptimization. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
2021-10-28radeon/vcn: combine session init funcBoyuan Zhang1-29/+8
Combine the session init function for h.264 and hevc to reduce redundancy. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
2021-10-28radeon/vcn: combine encode params funcBoyuan Zhang1-52/+1
Combine the encode params function for h.264 and hevc to reduce redundancy. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
2021-10-28radeon/vcn: remove redundancy for vcn2 encBoyuan Zhang1-16/+0
Remove redundancy functions for vcn2 encode. Re-using the vcn1 quality params function as a result. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
2021-10-28radeon/vcn: update vcn2 enc interfaceBoyuan Zhang1-0/+2
Add missing parameters according to vcn 2 encode interface. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
2021-10-28radeon/vcn: update vcn1 enc interfaceBoyuan Zhang2-1/+11
Update vcn 1 encode interface, upgrade interface minor version from 2 to 9, and add necessary parameters accordingly. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
2021-10-28radeon/vce: Limiting max supported refernce frames to 1 for h264 encodingshanshengwang1-1/+1
VCE currently restricted max_supported reference frames to 1 Signed-off-by: shanshengwang <shansheng.wang@amd.com> Suggested-by: Suresh Guttula <suresh.guttula@amd.com> Acked-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13543>
2021-10-19winsys/amdgpu: remove force_chaining parameter from cs_check_spaceMarek Olšák1-3/+1
it's always false Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13400>
2021-10-18radeon_winsys.h: add a parameter to buffer_from_handlePierre-Eric Pelloux-Prayer1-1/+1
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13362>
2021-09-10radeonsi: remove the primitive discard compute shaderMarek Olšák1-23/+0
It doesn't always work, it's only useful on gfx9 and older, and it's too complicated. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4011 Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812>
2021-09-07radeon/vcn: Add FW header flag to enable VP9 header parsingVeerabadhran Gopalakrishnan2-0/+6
set flags to enable VP9 uncompressed header parsing in FW and extract quantization and loop filter parameters. Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12703>
2021-08-31radeon/vcn: add a handling of error for incorrect reference listsLeo Liu1-1/+8
Use the first dpb buffer instead of the NULL pointer sent to hardware. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12610>
2021-08-31radeon/vcn: reuse the dpb buffers when with the same size.Leo Liu1-6/+8
To avoid allocate/deallocate frequently. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12610>
2021-08-19radeon/vcn: set min value for num_temporal_layersBoyuan Zhang1-1/+1
Fixes: 51935d59 In the case where num_temporal_layers is not set (0), set it using the minimum value 1, otherwise the rate control settings will be missing. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Thong Thai <thong.thai@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12463>
2021-08-18radeon/vcn: check frame size change for vp9 header flagsBoyuan Zhang1-1/+2
Beside show_frame and error_resilient_mode, also need to check if frame size changes. FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS flag should be OFF if frame size changes. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12368>
2021-08-18radeon/vcn: track width and height of the last frameBoyuan Zhang2-0/+5
Adding last width/height to keep tracking the size of the last frame. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12368>
2021-08-18radeon/vcn: initilize num_temporal_layers for hevcBoyuan Zhang1-0/+1
Fixes: 51935d59 num_temporal_layers has not been initialized for hevc, which will cause hevc encode failure. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Thong Thai <thong.thai@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12434>
2021-08-13radeon/vcn: Enable the AV1 decode p010 modeLeo Liu1-8/+8
It will still support 8 bits dithering mode decode. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12307>
2021-07-26radeon/vcn/enc: change to per-temporal layer rate controlThong Thai4-41/+55
Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
2021-07-26radeon/vce: change rate ctrl struct to arrayThong Thai4-40/+40
Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
2021-07-26radeon/vcn/enc: H.264 SVC encodeThong Thai4-3/+416
Implement H.264 temporal, Scalable Video Coding (SVC) for VCN devices by sending the required parameters to the firmware, and creating H.264 NALU prefix and SEI scalability_info headers. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
2021-06-30radeon/vcn: calc_dpb_size should be based on dpb_typeSureshGuttula1-7/+8
This patch will fix the dpb size calculated for each dpb_type. Current implementaion always calculating based on DPB_MAX_RES.To fix this dpb_type should be decided before calc_dpb_size. Signed-off-by: SureshGuttula <suresh.guttula@amd.corp-partner.google.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11633>
2021-06-22radeon/vcn/enc: Add missing line to HEVC SPS header codeThong Thai1-0/+1
Add previously missing line in HEVC SPS header generation on VCN 1.0 devices, for when an image does not need to be cropped. Fixes: e62c7e7c6ca ("radeon: Add cropping to encoded H.265 when padding is used") Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11535>
2021-06-22radeon/vcn: use st_rps_bits only when it's setBoyuan Zhang1-2/+3
Fixes: c9baccb5 For certain player which doesn't implement st_rps_bits, or when st_rps_bits is set to 0 (e.g. it doesn't have rps explicitly defined in slice header), we don't set st_rps_bits and the related flag, since we don't skip parsing the rps structure in these cases. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11432>
2021-06-18radeon/vcn: allocate non-tmz context buffer for VCN2+Boyuan Zhang2-4/+7
By design, context buffer should be allocated as TMZ buffer for secure playback for VCN 1 only. For VCN 2&2+, context buffer should be moved out of TMZ. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11388>
2021-06-18radeon/vcn: move calc_dpb_size into create_decoderBoyuan Zhang2-24/+26
Dpb buffer size calculation should based on the values provided in player's decoder creation call. db_alignmet should be decided in decoder creation call as well. Therefore, move db_alignment and dpb buffer size calculation from rvcn_dec_message_decode to radeon_create_decoder function. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11378>
2021-06-08radeonsi: separate video hw info based on HW engine individuallyLeo Liu1-1/+1
This removes previous "has_hw_decode" and "uvd_enc_supported" and makes information more accuate for cases where HW decode, HW encode, and HW JPEG decode might partially available. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11201>
2021-06-04radeon/vcn/enc: use surface swizzle mode instead of linearLeo Liu1-2/+12
It will be capable to have encoder tiling supported via modifier Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Thong Thai <thong.thai@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11165>
2021-05-29radeon/vcn: enable parsing support for st_rps_bitsBoyuan Zhang2-0/+4
Set st_rps_bits in hevc message buffer and set corresponding flag to indicate that st_rps_bits will be used for parsing the short_term_ref_pic_set structure. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10889>
2021-05-24amd: add Beige Goby supportMarek Olšák1-0/+1
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10878>
2021-05-24amd: add Yellow Carp supportAaron Liu1-0/+1
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10878>
2021-05-05radeon/vcn: Use the correct pitch for chroma surface.Bas Nieuwenhuizen1-2/+2
The pitch of the chroma plane isn't necessarily half that of the luma plane, as tiling (and presumably even linear) swizzle modes apply some alignment. Fixes: 35e25ea1d07 ("ac/surface: allow non-DCC modifiers for YUV on GFX9+") Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10638>
2021-04-15radeon/vcn: handle tiled buffers when decodingSimon Ser1-1/+6
Set the swizzle mode when decoding. Add a safe-guard to make sure the provided surface isn't DCC, because we don't handle this situation. Signed-off-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Simon Ser <contact@emersion.fr> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
2021-04-14amdgpu,radeon: add full_reset_only param to ctx_query_reset_statusPierre-Eric Pelloux-Prayer1-0/+1
Using this boolean the caller tells if it wants to ignore resets fixed by a soft recovery. When true, amdgpu can skip the call to libdrm if no cs has been rejected (since only full gpu reset cause cs rejections). Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10179>
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-05 17:58:59 +0000